MEASUREMENT

FIELD

[0001] The present application generally relates to power measurement in an electric power system.

BACKGROUND [0002] Real-time measurement of power can be critical to power system operation. For example, in transmission systems, operators monitor power on key interconnections closely to maintain power flow according to scheduled values and evaluate stability against safe operating limits. Oscillations due to disturbances, malfunctioning equipment, or ambient inter-area modes can grow to dangerous levels and result in a rapid cascade of events and precipitate a wide-scale blackout. Time-synchronized, real-time power measurements can be used to detect and monitor and mitigate such oscillations. In distribution systems, in order to maintain reliability, there is an increasing need to monitor power in real-time and at a much more granular level than before as more distributed, variable sources of renewable generation, and storage and other new resources are connected to the grid. Distribution grids are becoming more actively (rather than passively) managed in real-time using synchronized, real-time measurements. Unfortunately, many power systems still rely on measurement techniques that are either low accuracy, high latency or not time- synchronized.

BRIEF DESCRIPTION OF THE DRAWINGS [0003] Reference will now be made, by way of example, to the accompanying drawings, which show example embodiments of the present application, and in which:

[0004] Figure 1 shows a simplified block diagram of a power measurement device; [0005] Figure 2 shows a simplified block diagram of one example embodiment of a power measurement circuit;

[0006] Figure 3 shows, in flowchart form, one example method for measuring power in a power system;

[0007] Figure 4 shows one example embodiment of a power calculation circuit; and

[0008] Figure 5 shows a simplified block diagram of one example embodiment of an energ measurement circuit.

DESCRIPTION OF EXAMPLE EMBODIMENTS

[0009] In one aspect, the present application discloses a method of obtaining time- synchronized, high-speed power measurements within a power system. The method includes obtaining, at a sampling rate, a delta-sigma modulated bitstream of a voltage measurement and a delta-sigma modulated bitstream of a current measurement of the power system;

generating a system frequency measurement from a fast-tracking, direct digital synthesizer circuit driven by at least one of the delta-sigma modulated bitstreams, wherein the system frequency measurement tracks the frequency of the power system; determining, at the sampling rate, power calculations from the delta-sigma modulated bitstreams of voltage and current measurements; over successive first measurement windows gated by the system frequency measurement, determining a power measurement for each first measurement window from the power calculations in that window; applying interpolation to two or more of the power measurements to determine an estimated power measurement over a second measurement window not intentionally aligned with any of the first measurement windows; and outputting the estimated power measurement with an associated timestamp.

[0010] In another aspect, the present application discloses a power measurement device to obtain time- synchronized high-speed power measurements within a power system. The device includes delta-sigma modulators to receive a voltage measurement from the power system and produce, at a sampling rate, a delta-sigma modulated bitstream of the voltage measurement and to receive a current measurement from the power system and produce, at the sampling rate, a delta-sigma modulated bitstream of the current measurement; a high-speed frequency tracking unit to track the frequency of the power system, including a direct digital synthesizer to generate a system frequency measurement from at least one of the delta-sigma modulated bitstreams; a power calculation circuit to receive the system frequency measurement and the delta-sigma modulated bitstreams and to determine, at the sampling rate, power calculations for the power system from the delta-sigma modulated bitstreams, and to determine, over successive first measurement windows gated by the system frequency measurement, a power measurement for each first measurement window from the power calculations in that window; an interpolator to apply interpolation to two or more of the power measurements to determine an estimated power measurement over a second measurement window not intentionally aligned with any of the first measurement windows; and a communication subsystem to output the estimated power measurement with an associated timestamp.

[0011] In yet another aspect, the present application includes non-transitory computer- readable media containing processor-executable instructions for carrying out one or more of the methods described herein.

[0012] In stating that the first measurement window and second measurement window are "not intentionally aligned", the present application means that each window is aligned to a respective clock signal (or time value series) and the clocks are independent, e.g. one of the windows may be aligned based on the system frequency and the other window may be aligned to an independent clock such as an independent time value series derived from a UTC (Coordinated Universal Time) clock.

[0013] Other aspects and features of the present application will be understood by those of ordinary skill in the art from a review of the following description of examples in conjunction with the accompanying figures.

[0014] Reference is first made to Figure 1, which shows a simplified block diagram of a power measurement device 10. The device 10 includes a Delta-Sigma Modulator (DSM) 12 for measuring the power quantity (voltage and/or current on one of the phases of a polyphase circuit) and producing a 1-bit signal or bitstream 14. It will be understood that conventional delta-sigma converters employ a low-pass filter at the output to remove the high frequency shaped quantization noise components of the delta-sigma modulation when converting bitstream to multi-bit data. In some embodiments, the device 10 does not employ such low pass filtering but, instead, retains the high frequency components. As noted above, for simplicity a single DSM 12 is illustrated in Figure 1. Some implementations may have two or more delta-sigma modulators for measuring current and voltage signals on one or more phases. In the case of a three-phase three- wire connection, four DSMs may be used so as to measure the requisite currents and voltages to determine 3-phase power. Similarly, in the case of a three-phase four- wire connection, six delta-sigma modulators may be used so as to measure current and voltage on all three phases.

[0015] The device 10 includes a signal processor 20. The signal processor 20 receives the bitstream 14 and performs signal analysis and measurements as described in greater detail below. In particular, the signal processor 20 is implemented to operate on the 1-bit DSM output bitstream 14 directly.

[0016] The signal processor 20 includes a 1-bit frequency tracking direct digital synthesizer (DDS) 30 that produces a power system frequency measurement 32 that is locked to and tracks the frequency on one phase of the power system. The DDS 30 may, in some embodiments, include a 1-bit dual frequency locked-loop (FLL) and phase-locked- loop (PLL) architecture. In many embodiments, FLL/PLL measurements are obtained from 3 phases and are collectively used to produce the power system frequency measurement 32, which addresses the possibility errors in the frequency measurement due to a low or distorted amplitude on one phase as a result of a fault or disturbance. In addition to the power system frequency measurement 32, the DDS 30 may output frequency tracking phasor signals for the other voltage or current of that one phase and for both current and voltage of the other phases of the power system. It will also be understood that in some implementations more than one power system frequency measurement 32 may be output, such as one signal measured from a generator, and another from a bus for the purpose of connecting the generator to the bus when the voltages synchronized, that is sufficiently equal in phase, voltage and frequency.

Examples of the DDS 30 and, in particular, a 1-bit FLL/PLL implementation, are described in US Patent No. 9,157,940 to Dionne, entitled "Power Measurement Device", the contents of which are hereby incorporated by reference.

[0017] The signal processor 20 may include a clock correction circuit 40 for correcting local oscillators (not illustrated) based on an external time source, such as from a global navigation satellite system (GNSS), e.g. a global positioning satellite (GPS) signal. Example methods and devices for correcting clock signals are described in PCT publication no. WO

2015/077859, to Dionne et al., entitled "Methods and devices for error correction of a signal using delta sigma modulation", filed November 28, 2013, the contents of which are hereby incorporated by reference.

[0018] The signal processor 20 further includes a power measurement circuit 50. The power measurement circuit 50 receives the delta-sigma modulated bitstreams 14 of voltage and current measurements and outputs one or more power measurements. In some embodiments, the power measurement circuit 50 produces real-time measurements of active, reactive and apparent power (P, Q & S).

[0019] The device 10 may also include a memory or buffer (not shown) for storing measurement data. It also includes a communication subsystem (not shown) for

communicating with a remote location. The communication subsystem may implement any of a variety of communication protocols and physical layer connections. In one example embodiment, the communication subsystem may implement Ethernet (10/100 Mbit or Gigabit, for example), GSM, W!MAX, PLC, etc. In some implementations the

communication subsystem may operate in accordance with multiple communication protocols.

[0020] The signal processor 20 may be implemented in a number of ways. In some embodiments, the signal processor 20 may be implemented using a field programmable gate array (FPGA). In some embodiments, it may be implemented using a suitable programmed general purpose microcontroller or microprocessor. In yet other embodiments, it may be implemented using a digital signal processor. In yet further embodiments, it may be implemented using an application-specific integrated circuit (ASIC). In some embodiments, the foregoing may be supplemented with discrete analog and/or digital components for implementing certain operations or aspects of the signal processor 20. The full range of possibilities will be apparent to those of ordinary skill in the art in light of the following description.

[0021] It will be appreciated that the simplified diagram shown in Figure 1 omits a number of components or elements that may be included in the device 10, such as debugging circuitry, local oscillator and/or correction circuitry for an internal clock, isolation hardware, power source circuitry, etc. [0022] Real-time measurement of power can be critical to power system operation. In transmission systems, power on key interconnections is monitored very closely to maintain power flow according to scheduled values and evaluate stability against safe operating limits. Oscillations in power due to disturbances, malfunctioning equipment, or ambient modes can grow to dangerous levels and result in a rapid cascade of events that precipitate a wide-scale blackout. Typical oscillations of this nature may be in the 0.1 to 5 Hz range and must be monitored in real-time and compensated for using high-speed power oscillation damping equipment. This necessitates the use of time synchronized power measurement devices to detect and accurately measure such oscillations at high speed, resolution and low latency. In distribution systems, in order to maintain reliability, there is an increasing need to monitor power in real-time and at a much more granular level than before as more distributed, variable sources of renewable generation, and storage and other new resources are connected to the grid. Distribution grids are becoming more actively (rather than passively) managed in realtime using synchronized, real-time measurements. Unfortunately, many power systems still rely on measurement techniques that are either low accuracy, high latency or not time synchronized.

[0023] Existing phasor measurement units may produce precise time synchronized phasor measurements, but usually do not include harmonics, have a 2-15 cycle latency, are slow, and have low accuracy during transient/dynamic conditions. In some cases, power measurement based on time synchronized phasor measurements is very sensitive to phase angle error.

[0024] Precise time synchronization of measurements is important to accurate power system measurement. There are three aspects to time synchronization. First is absolute time accuracy, which means that the measurements are taken and timestamped using a global time reference to a specified accuracy. The global time reference, e.g. Universal Time Coordinated (UTC), may be derived or obtained from an external time source, like GPS, in some cases. A second aspect of time synchronization is that the measurements, which are being made by distributed devices throughout the power system, be made at the same time and at the same rate. A third, and often overlooked, aspect is the use of the same measurement (observation) window length. When all three aspects are handled with sufficient care then measurements can be correlated between different locations without the need for extensive post-processing to correct for known and unknown errors, including time skew. Ensuring an improved dynamic response of such synchronized measurements to rapidly changing system conditions would also enable real-time correlation and response by operators and automatic control systems.

[0025] The present applicant has developed at least one power measurement circuit for use with 1-bit delta-sigma sampled system measurements using a 1 -second UTC- synchronized measurement rate. The measurements are highly accurate and include all spectral components from DC up to approximately 50kHz. However, the 1 -second update rate means that it is too slow for detecting oscillations and for use in critical real-time control applications. Moreover, the use of a UTC-driven measurement time or window will typically result in some oscillating error term because the measurement window includes a fractional (non-integer) number of cycles.

[0026] In accordance with one aspect of the present application, the power measurement circuit 50 uses the power system frequency measurement 32 generated by the DDS 30 to drive measurement of power, i.e. to gate or set the measurement window for the periodic calculation of active power and, in some embodiments, reactive and/or apparent power. By gating the calculation periodicity based on the power system frequency the problem of drift error is eliminated through synchronization of the measurement window to the cycles of power system frequency, which is enabled through the fast, accurate frequency tracking provided by the 1-bit DDS 30.

[0027] The power measurement circuit further features an interpolator to provide an estimated power measurement synchronized to a pre-determined UTC time and reporting period. The interpolator provides an estimate based on two or more of the power system measurements taken over sample windows gated by the system frequency, and may employ linear, quadratic, cubic or other interpolation mechanisms. In this manner, the power system measurement estimates from various distributed devices are synchronized to a common absolute time despite being taken at possibly different sample times based on different frequencies or phases in the system at specific locations.

[0028] By having the base measurement synchronized to the power system frequency, beat frequency error (an error term which oscillates at the frequency equal to the difference between the power system frequency and the measurement frequency) in the measurement can be eliminated. Interpolation provides accurate estimation during dynamic changes, while introducing zero error for steady state conditions.

[0029] Reference is now made to Figure 2, which shows a simplified block diagram of one example embodiment of the power measurement circuit 50. In this embodiment, the power measurement circuit 50 is configured to calculate power measurements in accordance with a first sampling period, i.e. over a first measurement window. In this example, the first measurement window is every half-cycle of the power system frequency; however, in other embodiments the calculation may occur over a longer window, such as a full-cycle, for example, or even longer, such as 10 cycles, 12 cycles, 150 cycles, 180 cycles, etc. In some instances, the power measurement circuit 50 may be configured to use staggered and overlapping measurement ½ cycle windows to generate power measurements more frequently than every ½ cycle. For example, if a ½ cycle measurement window is started every ¼ cycle, a new power measurement is available every ¼ cycle. This concept could be extended to obtain measurements every l/8 ^th cycle, l/16 ^th cycle, etc.

[0030] In this example embodiment, a zero-crossing detector 52 may be used to create a strobe signal 54 at the 0 and 180 degree points in the power system frequency measurement 32. The strobe signal 54 gates the power measurement circuit 50 to calculate a power measurement based on accumulated power readings, i.e. it signals the start and end of a measurement window

[0031] Figure 2 illustrates the power measurement circuit 50 for one pair of voltage and current bitstreams. It will be appreciated that, in some embodiments, the portion of the circuit indicated by reference numeral 56 may be replicated for other voltage and current bitstreams, i.e. for other phases of a polyphase power system. Reference numeral 58 indicates the incoming voltage and current bitstreams from respective delta-sigma modulators. It will be understood that readings of voltage and current on a phase of the power system are typically taken by way of a potential transformer (PT) and current transformer (CT), respectively, and the scaled down signals from the transformers modulated by respective delta-sigma modulators to create the delta-sigma modulated bitstreams 58 of voltage and current measurements. The bitstreams 58 are, in one embodiment, generated using a relatively high sample rate which, in at least one embodiment, is over 10 MHz. In one specific example, the sample rate is 12.5 MHz; although other delta-sigma sampling rates may be used in other embodiments.

[0032] The bitstreams 58 are input to a 1-bit power calculation unit 60, which effectively calculates instantaneous power. The output of the power calculation unit 60 is a multi-bit word. The delay through the power calculation unit 60 is a preset number of cycles (of the circuit clock frequency) dependent upon the design and architecture of the circuit. In one example implementation the delay may be 120 cycles, for example, which in this embodiment would amount to only about 10 microseconds. The values from the power calculation unit 60 are added to an accumulator 62. A count of values added to the accumulator 62 since last snapshot (and flush) of the accumulator 62 is also maintained. The strobe signal 54 gates calculation of the power measurement and causes the accumulator value to be output and scaled by a scaling unit 64. The scaling unit 64 may divide the accumulator value by the count of values (unless that division has been incorporated into the accumulator value already in some implementations). The scaling unit 64 may also compensate for the PT/CT ratio as well as error in some embodiments. In this example, this gives an average active power measurement (P) 66 every half-cycle of the power system frequency.

[0033] In the case of a polyphase system, the multiple active power measurements (66) are summed in a multi-bit adder 68 to give three-phase power. In particular, in a 3-phase, 4-wire connection, the active power measurements for three phases are summed; in a 3-phase, 3-wire connection, two active power measurements are summed. Thus the adder 68 outputs a three- phase active power measurement every half-cycle of the power system frequency, in this example.

[0034] The power measurement circuit 50 further includes an interpolator 70. The interpolator 70 determines an estimated power measurement by applying interpolation to two or more of the power measurements from the multi-bit adder 68. The interpolation may be linear, quadratic, cubic, or any other type of interpolation. Due to the generally sinusoidal nature of signals in the power system, some embodiments may use a quadratic or cubic interpolation over three or more of the three-phase active power measurements. The interpolation is carried out in accordance with a second sampling period or window. The second sampling period is typically based on a phasor measurement unit (PMU) reporting rate, based on UTC. Common example reporting rates are 240, 120, 60, 30, 20, 15, 12 and 10 times per second.

[0035] A timestamp corresponding to the gating of the first measurement window may be obtained from a local master time clock 44, which is synchronized to an external time source, such via a GPS receiver 42 for example. A latch 46 gated by the strobe signal 54 supplies the UTC timestamp to the interpolator 70. Accordingly, the timestamp is associated with the first measurement window over which the power measurement has been calculated.

[0036] The second measurement window is synchronized to the UTC local master time clock 44, and is gated at a desired reporting rate. In one example embodiment, a circuit (not shown) that receives a clock signal from the local clock 44 may be configured to output a pulse signal 72 at the desired reporting rate that corresponds to the second measurement window. That pulse signal 72 triggers the interpolator 70 to determine the estimated power measurement 74, which is then output. The estimated power measurement 74, together with a timestamp from the local clock at the pulse signal time, may then be output/transmitted locally to another part of the device containing this circuit or remotely to a central location. In another embodiment, this operation is implemented in software without a discrete pulse signal 72. The interpolator may receive the local clock signal and may determine, from knowing the timestamps associated with the power measurements, the local time, and the desired reporting frequency, the window over which to interpolate to produce the estimate power measurement plus a timestamp for the estimated power measurement. The timestamp may be selected to indicate the time at the beginning, middle, or end of the second measurement window, depending on the convention adopted for a particular implementation.

[0037] The power measurement circuit 50, in this example, also calculates apparent power (S). Apparent power is given by the product of voltage and current RMS measurements. Accordingly, the bitstreams 58 are input to RMS calculation units 80 (only one is illustrated for simplicity). RMS values for both current and voltage are determined by the RMS calculation units 80.

[0038] The RMS values from the RMS calculation units 80 are input to respective accumulators 82 (again, only one is shown for simplicity). The strobe signal 54 is used to cause the accumulators 82 to periodically output the respective accumulated RMS values therein, which are then scaled by respective scaling units 84 to produce RMS measurements for voltage and current respectively. These values are then multiplied by a multi-bit multiplier 86 to produce an apparent power measurement 88.

[0039] The apparent power measurements 88 for respective phases of the power system are summed by an adder 90 (in a polyphase system) and provided to an interpolator 92. The interpolator 92 functions similarly to the interpolator 70 in that it produces an estimated apparent power measurement 94 based on two, three or more of the apparent power measurements.

[0040] In some embodiments, the power calculation unit 60 and RMS calculation units 80 may be at least partly implemented using common circuit elements. An example of such an implementation will be described later below.

[0041] In some implementations, the power measurement circuit 50 may also estimate reactive power (Q). The determination of reactive power is based on the expression

Q=±sqrt(S ² -P ² ) (based on the IEEE 1459-2010 formula for non-active power). Accordingly, to perform this calculation, the measurements of active power P and apparent power S are taken using the same first measurement window. Those measurements are input to a square root operator 98 configured to square the operands, subtract them, and find the square root.

[0042] The expression only provides a magnitude for reactive power Q; the sign is determined from the phase angle difference between the voltage and current fundamental component. As described in US Patent No. 9,157,940, the 1-bit DDS 30 may provide accurate frequency tracking phasor measurement for each phase of voltage and current in a polyphase power system. Accordingly, the power measurement circuit 50 may include a sign-determination circuit 96 that produces a -1 or a +1 signal based on the difference between the voltage phase angle and the current phase angle. The sign-determination circuit 96 applies the +1 or -1 signal to the output of the square root operator 98 to produce a properly signed reactive power (Q) measurement.

[0043] The frequency/phasor measurement, in this example, has a nominal 14 ms group delay and is updated 32 times per cycle. As mentioned above, the delay through the example power and RMS calculation units 60, 80 is about 10 microseconds, based on a delay in the units 60, 80 of 120 cycles of the 12.5 MHz delta-sigma bitstreams 58. This means that the latest power calculations of active power P and apparent power S incorporate a delay of 10 microseconds (in this example). Accordingly, if the first sampling period is a 1 cycle window (at a power system frequency of about 60Hz), then the power measurements P and S will be within the same window as the frequency/phasor measurement. For a ½ cycle window, the latest angle measurements are associated with the previous P and S measurement. However, under almost all real- world conditions this mismatch would have a negligible impact on resulting measurements of reactive power, Q.

[0044] The signed reactive power (Q) measurements from multiple phases may be summed in an adder 97 and an interpolator 99 may be used to determine an estimated reactive power measurement over the second measurement window based on interpolation between reactive power measurements.

[0045] Reference is now made to Figure 3, which shows, in flowchart form, one example method 100 for obtaining time-synchronized high-speed power measurements within a power system. The method 100 is based on delta-sigma modulated sampling of voltage and current readings at relatively high rates. The sampling rate may be several MHz in some

embodiments. It may be over 10 MHz in some embodiments.. Accordingly, operation 102 indicates obtaining delta-sigma modulated bitstreams of voltage and current measurements.

[0046] As indicated by operation 104, at least one of the bitstreams is the input to a highly- accurate and fast frequency-tracking direct digital synthesizer that produces a measurement of the frequency of the power system. In a polyphase system, the system frequency

measurement may be based on, for example, the voltage bitstream from more than one phase. Frequency-tracking phasor measurement with respect to the current bitstream of that phase and the current and voltage bitstreams of other phases of the system may produce a set of phasor measurements to enable phase comparisons between the voltage and current signals and between phases.

[0047] In operation 106, power calculations are determined from the voltage and current bitstreams at the rate of the bitstreams. In operation 107, those calculations are averaged over a first measurement window to find a power measurement for that first measurement window. The length and periodicity of successive first measurement windows is based on the system frequency measurement so as to synchronize it to the frequency of the power system. As an example, the sampling period may be A/ _ps , where f _ps is the system frequency and A is a measurement-time scaling factor. For example, the measurement window may be 1 cycle of the system frequency when A=l. It may be a half cycle where A=0.5. Other values for A may be used in other embodiments.

[0048] As described in some example embodiments above, the power measurement involves continuous multiplication of the two bitstreams in operation 106, which can be implemented through filtering one bitstream and delaying the other bitstream, multiplying, then using an accumulator to accumulate the values from the multiplication. The continuous calculation of power from the voltage and current bitstreams occurs at the rate of the bitstreams, i.e. a multi- bit power measurement value is generated for every bit of the delta-sigma bitstreams. In operation 107 an average power measurement may be determined by dividing the

accumulated value in the accumulator by the number of measurements (values). Other implementations may realize the multiplication of the voltage and current measurements in another manner. The power measurement may include a calculation of active power, apparent power, reactive power, or two or more of these quantities.

[0049] The calculation of the power measurement in operations 106 and 107 may be carried out per phase in a polyphase power system, and those phase-specific power measurements may be summed in an adder to produce a polyphase (e.g. 3 -phase) power measurement. It will be appreciated that the operations 106 and 107 produce a series of power measurements at times set by the periodicity of the first sampling window, i.e. one measurement every window. In the case of a ½-cycle window, a power measurement is produced every ½-cycle of the system frequency.

[0050] In operation 108, interpolation is applied to two or more of the power measurements to obtain an estimated power measurement over a second measurement window

corresponding to a reporting time based on a local clock not synchronized to the system frequency. In many embodiments, the local clock is synchronized to an external clock source. This enables a plurality of dispersed measuring units to be synchronized to a common time source for the purpose of comparing measurements taken throughout the system at a common reporting time. Because the designated reporting time (e.g. every 200 ms UTC) is unlikely to correspond exactly to the measurement times set by the first measurement window, interpolation is used to ensure that the estimated power measurement is able to account for high-speed dynamic changes in the power system. The interpolation may be linear in some embodiments. In some embodiments, it may be quadratic or cubic. A variety of line or curve fitting algorithms may be used to find the estimated power measurement at the reporting time based on the two, three, or more power measurements within the second measurement window.

[0051] In operation 110, the estimated power measurement is output, together with a timestamp, which may correspond to the beginning, middle, or end of the second

measurement window, or some other time associated with the second measurement window depending on the implementation selected. The timestamp may be obtained from the local clock.

[0052] As mentioned above, the power calculation unit 60 and RMS power calculation units 80 may be at least partly implemented using common circuit elements. Reference is now made to Figure 4, which shows, in simplified block diagram form, one example embodiment of a power calculation circuit 200. The example power calculation circuit 200 receives an input delta-sigma modulated voltage measurement bitstream 202 and an input delta-sigma modulated current measurement bitstream 204. In this example, the bitstreams are 12.5MHz bitstreams, but other sampling rates may be used in other embodiments.

[0053] The bitstreams 202, 204 are each input to a respective filter, which in this case are shown as moving average filters 206, 208, respectively. The output of each filter 206, 208 is a multi-bit word. The moving average filter is one example filter that may be used to generate the filtered multi-bit signal from the delta-sigma modulated signal, but it is not the only such filter. Another filter that may be used in some embodiments is a multiple-pass moving average filter, which has characteristics of a Gaussian filter and a Blackman window filter. In yet other embodiments, the filter may be a cascaded integrator-comb (CIC) filter. In general, a suitable filter for the DSM signal is one in which the passband has no ripple and is linear phase, and which may be implemented without use of a multiplier. The filters 206, 208 are clocked at the same rate as the bitstreams 202, 204.

[0054] The bitstreams 202, 204 are also input to a respective delay circuit 210, 212. The delay circuit 210, 212 delays the bitstreams 202, 204 by a predetermined number of clock cycles to account for the delay through the filters 206, 208 sufficient to realign the bitstreams 202, 204 with the output of the multi-bit word from the filters 206, 208. In other words, the delay imposed by the delay circuits 210, 212 is the same as the delay resulting from propagation of the bitstreams 202, 204 through the filters 206, 208. [0055] The output multi-bit words from the filters 206, 208 are multiplied by the delayed bitstreams 202, 204 by respective multipliers 214, 216 to effective apply a sign to the multi- bit word. If the delta-sigma modulated bitstreams 202, 204 are in a 0/1 representation, they may be converted to a -1/+1 representation, either prior to the delay circuits 210, 212, within the delay circuits 210, 212, or after the delay circuits 210, 212, e.g. within the multipliers 214, 216. The respective multipliers 214, 216 produce the current and voltage squared

measurements for input to the accumulators 82 (Fig. 2).

[0056] The power calculation circuit 200 also includes a multiplier 218 that receives (in this example) the multi-bit word from the filter 206, reflecting the filtered current measurement, and multiplies it by the delayed voltage bitstream output by the delay circuit 212. This generates the P=VI active power measurement calculation, thereby producing the power measurement values for input to the accumulator 62 (Fig. 2).

[0057] The power measurement circuit 50 may be implemented together with an energy measurement circuit, particularly since they may share many of the same components.

Energy measurements are not needed at a high update rate (compared to power

measurements), so they may be carried out less frequently. In some cases, the calculation rate is every 200 ms, which corresponds to the rate prescribed by IEC 61000-4-30 power quality (PQ) measurement at nominal frequency and the rate for wind turbine PQ evaluation (IEC 61400-21).

[0058] Reference is now made to Figure 5, which shows, in block diagram form, an example energy measurement circuit 300. The energy measurement circuit 300 is structurally similar to the power measurement circuit 50 (Fig. 2); although, it will be noted that rather than taking a snapshot of the accumulators 62, 82 on a ½ cycle frequency tied to the measured power system frequency, the energy measurement circuit 300 takes a snapshot of the accumulators 62, 82 at pre-determined UTC-based times driven by a local clock 44 synchronized to an external time source, for example obtained from a GPS receiver 42. A delay 350 may delay the sampling signal to align the sampling signal from the local clock with the power measurement to account for propagation delay through power and RMS calculation units 360, 380.

[0059] It will also be noted that the energy measurement circuit 300 features accumulators 302, 304, 306 at the output from the adders instead of interpolators. The energy measurement circuit 300 provides accurate long term measurement of energy, as opposed to the accurate short term power estimate provided by the power measurement circuit 50.

[0060] It will be understood that the above-described RMS calculators may be implemented partly in hardware and partly in software. In some cases, the hardware components may include both discrete and integrated circuit components. In some embodiments, the implementation may include one or more field programmable gate arrays (FPGA). In some embodiments, the implementation may include one or more application-specific integrated circuits (ASIC). The selection of particular hardware components may be based upon cost, speed, operating environment, etc. The selection and programming of such components will be within the understanding of a person of ordinary skill in the art having regard to the detailed description provided herein.

[0061] In yet a further aspect, the present application discloses a non-transitory computer- readable medium having stored thereon computer-executable instructions which, when executed by a processor, configure the processor to execute part or all of any one or more of the processes described above.

[0062] Certain adaptations and modifications of the described embodiments can be made. Therefore, the above-discussed embodiments are considered to be illustrative and not restrictive.