Title:
METHODS FOR FORMING A TRANSISTOR
Document Type and Number:
WIPO Patent Application WO2006011939
Kind Code:
A3
Abstract:
Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate dielectric, forming a first pair of sidewall spacers along laterally opposite sidewalls of the gate electrode, etching a pair of source/drain region definitions on opposite sides of the electrode, depositing a silicon-germanium material selectively in the source/drain region definitions, and implanting a dopant in the deposited silicon-germanium material to form a source/drain region having a second conductivity.
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Inventors:
NOURI FARAN (US)
WASHINGTON LORI D (US)
MOROZ VICTOR (US)
WASHINGTON LORI D (US)
MOROZ VICTOR (US)
Application Number:
PCT/US2005/019328
Publication Date:
October 19, 2006
Filing Date:
June 02, 2005
Export Citation:
Assignee:
APPLIED MATERIALS INC (US)
NOURI FARAN (US)
WASHINGTON LORI D (US)
MOROZ VICTOR (US)
NOURI FARAN (US)
WASHINGTON LORI D (US)
MOROZ VICTOR (US)
International Classes:
H01L21/336; H01L29/165
Foreign References:
| US6121100A | 2000-09-19 | |||
| US20020053711A1 | 2002-05-09 | |||
| US20040084735A1 | 2004-05-06 |
Other References:
GHANI T ET AL: "A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nin Gate Length Strained Silicon CMOS Transistors", INTERNATIONAL ELECTRON DEVICES MEETING 2003. IEDM. TECHNICAL DIGEST. WASHINGTON, DC, DEC 8 - 10, 2003, NEW YORK, NY : IEEE, US, 8 December 2003 (2003-12-08), pages 978 - 980, XP010684238, ISBN: 0-7803-7872-5
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