Title:
METHODS OF RESOURCE OPTIMIZATION IN PROGRAMMABLE LOGIC DEVICES TO REDUCE TEST TIME
Document Type and Number:
WIPO Patent Application WO2004013967
Kind Code:
A3
Abstract:
Methods of optimizing the use of routing resources in programmable logic devices (PLDs) to minimize test time. A set of routing resources is identified that are not used in most designs, and a device model is provided to the user that prevents the use of these resources. Because the routing resources will never be used, they need not be tested by the PLD manufacturer, significantly reducing the test time. For example, each PLD within a PLD family is typically designed using a different number of similar tiles. Thus, smaller PLDs in the family include an unnecessarily large number of routing resources. These excessive routing resources can be disabled during implementation of a design. In another example, each tile along the edges of an array includes routing resources designed primarily to provide access to tiles that are not present. These redundant routing resources can be disabled during implementation of a design.
Inventors:
LAI ANDREW W
SIMMONS RANDY J
MANSOUR TEYMOUR M
TONG VINCENT L
LINDHOLM JEFFREY V
YOUNG JAY T
TROXEL WILLIAM R
KRISHNAMURTHY SRIDHAR
SIMMONS RANDY J
MANSOUR TEYMOUR M
TONG VINCENT L
LINDHOLM JEFFREY V
YOUNG JAY T
TROXEL WILLIAM R
KRISHNAMURTHY SRIDHAR
Application Number:
PCT/US2003/024349
Publication Date:
January 06, 2005
Filing Date:
August 04, 2003
Export Citation:
Assignee:
XILINX INC (US)
International Classes:
G06F17/50; (IPC1-7): G06F17/50
Domestic Patent References:
| WO2001041309A1 | 2001-06-07 |
Foreign References:
| US6188242B1 | 2001-02-13 |
Other References:
EMMERT J ET AL: "Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration", ANNUAL IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, XX, XX, 17 April 2000 (2000-04-17), pages 165 - 174, XP002196502
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