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Title:
METHODS AND SYSTEMS FOR IDENTIFYING FLAWS AND BUGS IN INTEGRATED CIRCUITS, FOR EXAMPLE, MICROPROCESSORS
Document Type and Number:
WIPO Patent Application WO/2023/035799
Kind Code:
A1
Abstract:
A method, computer program product, and/or system is disclosed for testing integrated circuits, e.g., processors, that includes: generating a software design prototype of the functional behavior of an integrated circuit to be tested; creating a lab All-Events-Trace (AET) normalized model of the integrated circuit, wherein the normalized model captures the functions of the integrated circuit and not the non-functional aspects of the integrated circuit; generating a lab scenario using the software design prototype and the AET normalized model of the integrated circuit for a particular cycle of interest, wherein the lab scenario contains initialization for all signals that have hardware information; and generating a replayed lab normalized AET for the particular cycle of interest.

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Inventors:
JOSEPH ARUN (IN)
ROESNER WOLFGANG (US)
PARUTHI VIRESH (US)
GHOSH SHILADITYA (IN)
RACHAMALLA SPANDANA (IN)
Application Number:
PCT/CN2022/108561
Publication Date:
March 16, 2023
Filing Date:
July 28, 2022
Export Citation:
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Assignee:
IBM (US)
IBM CHINA CO LTD (CN)
International Classes:
G06F11/22
Foreign References:
US7089517B22006-08-08
US20060025980A12006-02-02
CN103064013A2013-04-24
US5619512A1997-04-08
US6061283A2000-05-09
US20120216080A12012-08-23
Attorney, Agent or Firm:
LIU, SHEN & ASSOCIATES (CN)
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