SUBSTRATE NOISE

BACKGROUND

TECHNICAL FIELD

[0001] This disclosure generally relates to charge pumps, and more particularly, to charge pumps with reduced substrate noise.

DESCRIPTION OF RELATED ART

[0002] In recent years, there has been a constant effort to improve performance, add additional features, reduce cost, and occupy less real estate in semiconductor integrated circuits (ICs). Consequently, the speed of circuits is progressively increasing, ICs are becoming more densely packed, and more circuit blocks are introduced that share a common substrate.

[0003] One challenge with these advanced digital, mixed signal, or analog ICs is to minimize noise coupling between various parts of the system to avoid degraded performance or even malfunctioning. Coupling caused by parasitics can lead to unreliable performance of the IC. For example, in mixed-signal circuits, both sensitive analog circuits and high frequency digital circuits that are a source of noise may be present on a same IC, leading to undesired signal coupling between these two types of circuits via the conductive substrate. The more densely packed these circuits are, the more pronounced the substrate noise issue becomes.

[0004] An example high frequency and high power circuit is a charge pump, which is a DC to DC converter that uses capacitors as energy storage elements to provide a lower or higher voltage level from a reference input. A charge pump can introduce mixed-signal noise coupling via a common node, such as the substrate. The high frequency switching operations of a charge pump cause fluctuations in the underlying substrate voltage, which spreads through the common substrate causing variations in the substrate potential, affecting various components of the IC, including the sensitive analog section.

BRIEF DESCRIPTION OF DRAWINGS

[0005] The drawings are of illustrative embodiments. They do not illustrate all embodiments. Other embodiments may be used in addition or instead. Details that may be apparent or unnecessary may be omitted to save space or for more effective illustration. Some embodiments may be practiced with additional components or steps and/or without all of the components or steps that are illustrated. When the same numeral appears in different drawings, it refers to the same or like components or steps.

[0006] FIG. 1A illustrates a typical charge pump stage.

[0007] FIG. 1 B illustrates several waveforms related to the operation of the charge pump stage of FIG. 1A.

[0008] FIG. 2 illustrates a charge pump stage 200, consistent with an illustrative embodiment.

[0009] FIG. 3 illustrates several waveforms related to the operation of the charge pump stage of FIG. 2, consistent with an illustrative embodiment. DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Overview

[0010] In the following detailed description, numerous specific details are set forth by way of examples in order to provide a thorough understanding of the relevant teachings. However, it should be apparent that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components, and/or circuitry have been described at a relatively high- level, without detail, in order to avoid unnecessarily obscuring aspects of the present teachings. Some embodiments may be practiced with additional components or steps and/or without all of the components or steps that are described.

[0011 ] The methods and circuits disclosed herein generally relate to methods and circuits of providing low noise charge pumps. More particularly, the present disclosure describes active charge pumps that have a reduced substrate noise. A charge pump uses switching devices to control a voltage across a capacitor. In this regard, multiple stages may be used to progressively increase a reference voltage from stage to stage. The capacitor used in each stage is sometimes referred to as a "flying capacitor," which is cycled between a first supply (e.g., Vin) and a second supply (e.g., ground). Flying capacitors generally have parasitic capacitance to ground (e.g., when used as an external device) or to the substrate (e.g., when integrated on a chip). This parasitic capacitance acts as a conduit for coupling noise to other circuit components that share the same ground and/or substrate.

[0012] Reference now is made to FIG. 1A, which illustrates a charge pump stage 100 as may be found in various typical charge pumps. Charge pump stage 100 includes a flying capacitor 1 16, which has a first node (V _dr ive) 1 4. There is a first switch Θ1 (1 12) coupled between the first voltage supply (V _s +) at node 102 and Vdrive 1 1 , and a second switch Θ2 (120) coupled between the second voltage supply (V _s -) at node 130 and Vdrive 1 14. There is a parasitic capacitance C _p 122 between V _d ri _V e 1 14 and the substrate terminal. The substrate terminal is generally connected to ground or an external supply. The parasitic capacitance C _p 122 represents the total parasitic capacitance at the V _d nve node 1 14, which may include the parasitic capacitance of the flying capacitor 1 16, the first switch 1 12, the second switch 120, wiring parasitics at node 1 14, etc., as well as any parasitic at node 1 18. In one estimate, the parasitic capacitance 122 may be 1 /10 to 1/5 that of the actual flying capacitor 1 16, which may be in the nano-farad range.

[001 3] Reference now is made to FIG. 1 B, which illustrates several waveforms related to the operation of the charge pump stage 100 of FIG. 1A. The V _d ri _V e node 1 14 is cycled between a first voltage supply (V _s +) at node 102 and a second voltage supply (V _s -) at node 130, as illustrated by waveform 142. To that end, when switch Θ1 1 12 is ON, a path is created between Vs+ at node 102 and V _d ri _V e 1 14 to charge the flying capacitor 1 16, as illustrated by waveform 144. The flying capacitor 1 16 is discharged through the switch Θ2 120. Thus, when the switch Θ2 120 is ON, a path is created between the second voltage supply Vs- at node 130 and the Vdrive node 1 14, as illustrated in waveform 146. The voltage transitions on the flying capacitor 1 16 are usually very fast, one nanosecond risetime or less. Accordingly, the transient currents driven by the switches Θ1 1 12 and Θ2 120 are also very fast. The resulting di/dt creates large voltage transients through the substrate connecting wire inductance. The resulting noise current is illustrated in waveform 148 and provided by equation 1 below: [0014] I _N0 ise = p [Eq. 1 ]

[0015] Accordingly, the noise current l _NO ise is a function of the parasitic capacitance C _p 122 and the change in voltage dv at the Vdrive node 1 14. The current spikes 148 due to the sharp voltage edges of the flying capacitor 1 16 are generally difficult to suppress.

[0016] The applicant has identified that by using a configuration and a timing sequence discussed herein, the rush of current to/from the substrate during a charge/discharge operation can be actively controlled, thereby reducing the noise floor of the substrate of a charge pump stage. To that end, an input node of the flying capacitor is pre-charged at a first slew rate. The input node of the flying capacitor is charged at a second slew rate that is faster than the first slew rate but has a small voltage change at Vdrive. The input node of the flying capacitor is pre-discharged at a third slew rate. The input node of the flying capacitor is discharged at a fourth slew rate that is faster than the first slew rate but also of small magnitude. By virtue of the methods and architectures discussed herein, the substrate noise in a charge pump having a flying capacitor is reduced.

Example Implementation

[0017] FIG. 2 illustrates a charge pump stage 200, consistent with an illustrative embodiment. Charge pump stage 200 includes a flying capacitor 216, which is coupled between the Vdrive node 214 and an output 218. In various embodiments, the output node 218 may be coupled to one or more charge pump stages to achieve a desired output voltage.

[0018] There is a first switch Θ1 (212), sometimes referred to herein as the drive switch, coupled between the first voltage supply (V _s +) at node 202 and the Vdnve node 214, and a second switch Θ2 (120), sometimes referred to herein as the discharge switch, coupled between the second voltage supply (V _s -) at node 230 and the Vdrive 214. The first switch Θ1 (212) is configured to quickly charge the Vdrive node 214, whereas the second switch Θ2 (220) is configured to quickly discharge the Vdrive node 214.

[0019] In one embodiment, there is a first current source 204 coupled to the first voltage supply (Vs+) at node 202 and a second current source 210 coupled to the second voltage supply (Vs-). A third switch Θ3 (206) is coupled between the first current source (204) and the V _d rive node 214. A fourth switch Θ4 (208) is coupled between the V _d ri _V e node 214 and the second current source l ₂ (210).

[0020] The third switch Θ3 (206) is configured to pre-charge the V _d ri _V e node 214 at a slew rate that is substantially slower than that caused by the first switch Θ1 . For instance, the Θ3 period can be one-fourth the clock period. If the clock frequency were 1 MHz, the Θ3 period would be 250nsec, much slower than a 1 nsec uncontrolled edge. The fourth switch Θ4 (208) is configured to pre- discharge the V _d ri _V e node 214 at a slew rate that is substantially slower than that caused by the second switch Θ2 (220). In one embodiment, the slew rate of the third switch Θ3 (206) and the fourth switch Θ4 (208) are substantially similar. Equation 2 below provides the guidelines for the first current source 204 and the second current source 210, for an example embodiment.

[0021 ] and I ₂ ≥ 4 x C _p (V _s+ - V _s _) x F _osc [Eq. 2]

Where:

is the current through the first current source 204;

l ₂ is the current through the second current source 210;

C _p is the parasitic capacitance 222; and Fosc is the inverse of the period of switches Θ1 (212) and Θ2

(220).

[0022] By virtue of the relationship in equation 2 above, the charge pump stage 200 provides a pre-charge and a pre-discharge having a slew rate that is substantially slower than the slew rate of the charge switch Θ1 (212) and the discharge switch Θ2 (220), respectively.

[0023] In one embodiment, a separate current source 204 and/or l ₂ 208 are not necessary. For example, the switch Θ3 (204) may be configured such that it provides a reduced current between the first voltage supply Vs+ and the Vdrive node 214 that is consistent with equation 2 above. Similarly, the switch Θ4 (208) may be configured such that it provides a reduced current between the second voltage supply Vs- and the Vdrive node 214 consistent with equation 2 above. For example, if a field effect transistor is used as a switch, the width/length of the transistor may be adjusted to achieve the desired current through the transistor. It is believed that those skilled in the art are knowledgeable about the sizing of the different types of switches to achieve the desired current. Accordingly, the sizing of the switches is not discussed herein for brevity.

[0024] As discussed previously, there is a parasitic capacitance C _p 222 between Vdrive node 214 and the substrate terminal. While the parasitic capacitance C _p 222 has been illustrated by way of example only and not by way of limitation to ground, in various scenarios, the parasitic capacitance C _p 222 may be to any other node, such as the substrate, the first supply (Vs+), the second supply (Vs-), or any other node of the charge pump stage 200. [0025] The parasitic capacitance C _p 222 represents the total parasitic capacitance at the V _dr ive node 214, which may include the parasitic capacitance of the flying capacitor 216, the first switch 212, the second switch 220, wiring parasitics at node 214, wiring parasitics at node 218, etc.

[0026] Reference now is made to FIG. 3, which illustrates several waveforms related to the operation of the charge pump stage 200 of FIG. 2, consistent with an illustrative embodiment. The Vdrive node 214 is cycled between a level provided by a first voltage supply (V _s +) at node 202 and a second voltage supply (V _s -) at node 230, as illustrated by waveform 310. Significantly, the charge pump stage 200 is configured in such a way to prevent a current spike to the ground or substrate. To that end, each hard charge by the switch Θ1 (212) is preceded by a pre-charge via switch Θ3 (206). Similarly, each hard discharge by switch Θ2 (220) is preceded by a pre-discharge by switch Θ4 (208). Put differently, each charge cycle includes a pre-charge and a hard charge, and every discharge cycle includes a pre-discharge and a hard discharge.

[0027] For example, the Vdrive node 214 is pre-charged to a predetermined voltage level at a first slew rate by turning ON switch Θ3 (206), as indicated by waveform 340. Accordingly, a path is created between the first current source 204 and the V _d ri _V e node 214, thereby pre-charging the V _d nve node 214, having a parasitic capacitance C _p 222, to a predetermined voltage, which may be at or slightly below Vs+, due to the effective resistance drop of the switch Θ3 (206), which in turn is due to flying capacitor 216 charge current, as indicated by level 362.

[0028] In various embodiments, during the charge cycle, the switch Θ3 (206) is turned ON before the switch Θ1 (212) is turned ON. The switch Θ1 may be kept ON while switch Θ3 is ON (see dotted line of waveform 340 and its relationship to waveform 320) with little change in waveform 310. Thus, at T ₀ , the switch Θ3 (206) is ON until Ti to T ₃ . At T ₂ , the switch Θ1 is turned ON and kept ON until T ₃ . Thus, the pre-charge may have a time window that overlaps with the hard charge.

[0029] Similarly, during a discharge cycle, the V _d rive node 214 is pre-discharged to a second predetermined voltage (at or below Vs-) at a second slew rate, by turning ON switch Θ4 (208), as indicated by waveform 350. Accordingly, a path is created between the second current source 210 and the V _d rive node 214, thereby pre-discharging the V _d rive node 214 to a second predetermined voltage, which may be at or slightly above Vs-, as indicated by level 364. Thus, at T ₃ the switch Θ4 (208) is turned ON. In various embodiments, the switch Θ4 (208) is kept ON until T ₄ to T ₆ . Put differently, the switch Θ4 (208) is turned OFF before the second switch Θ2 (220) is turned ON, or kept ON until the next pre-charge cycle begins at T ₆ (see dotted line in waveform 350).

[0030] The slew rate during a pre-charge is provided by equation 3 below. [0031] _t = /c _P [Eq- 3]

Where:

dv is the change in voltage at the V _d rive node 214;

dt is the time for the voltage change at the V _d nve node 214; is the current through the first current source 204; and C _p is the parasitic capacitance 222.

[0032] In one embodiment, the pre-charge current provided by the first current source 204 is relatively small (e.g., in the order μΑ or tens of μΑ), thereby providing a slow slew rate). In contrast, the current provided through the first switch Θ1 (212) may be up to a thousand times larger, providing a second slew rate that may be largely uncontrolled and significantly faster than that of the pre- charge. Accordingly, by using the pre-charge, the injected substrate current is not only smaller (see a relatively small bump 366 during a hard charge) but also spread over time, as indicated by waveform 360. The pre-discharge operation is similar to the above and therefore not repeated here for brevity. By virtue of the pre-charge and the pre-discharge discussed herein, the substrate noise floor is reduced.

[0033] It should be noted that, in one embodiment, due to the slow slew rate, much charge is not transferred to the flying capacitor 216 via the third switch Θ3 (206) during a pre-charge operation. Thus, the switch Θ1 (212) performs the charge transfer to the flying capacitor 216 during a charge operation via switch Θ1 (212). In this regard, since the Vdrive node 214 almost arrived (see level 362 in waveform 310) at Vs+ level, the voltage at the Vdrive node 214 jumps to the Vs+ level when the switch Θ1 is turned ON at T ₂ . Switches Θ4 and Θ2 provide similar waveforms during a discharge cycle.

CONCLUSION

[0034] The components, steps, features, objects, benefits, and advantages that have been discussed are merely illustrative. None of them, nor the discussions relating to them, are intended to limit the scope of protection in any way. Numerous other embodiments are also contemplated. These include embodiments that have fewer, additional, and/or different components, steps, features, objects, benefits, and/or advantages. These also include embodiments in which the components and/or steps are arranged and/or ordered differently. [0035] For example, in various embodiments, a switch may be in the form of a field effect transistor (FET, such as a PFET, NFET, and/or JFET), bipolar device (e.g., NPN and/or PNP), any combination thereof, or any other suitable active or passive device based on the particular implementation. It is believed that those skilled in the art are familiar with the structure and general operation and implementation of a switch based on different technologies.

[0036] Unless otherwise stated, all measurements, values, ratings, positions, magnitudes, sizes, and other specifications that are set forth in this specification, are approximate, not exact. They are intended to have a reasonable range that is consistent with the functions to which they relate and with what is customary in the art to which they pertain.

[0037] Except as stated immediately above, nothing that has been stated or illustrated is intended or should be interpreted to cause a dedication of any component, step, feature, object, benefit, advantage, or equivalent to the public, regardless of whether it is or is not recited in the claims.

[0038] It will be understood that the terms and expressions used herein have the ordinary meaning as is accorded to such terms and expressions with respect to their corresponding respective areas of inquiry and study except where specific meanings have otherwise been set forth herein. Relational terms such as "first" and "second" and the like may be used solely to distinguish one entity or action from another, without necessarily requiring or implying any actual relationship or order between them. The terms "comprises," "comprising," and any other variation thereof when used in connection with a list of elements in the specification or claims are intended to indicate that the list is not exclusive and that other elements may be included. Similarly, an element preceded by an "a" or an "an" does not, without further constraints, preclude the existence of additional elements of the identical type.

[0039] The Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separately claimed subject matter.