CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit under 35 U.S.C. Section 119(e) of the following co-pending and commonly-assigned application:

U.S. Provisional Patent Application Serial No. 62/451,993, filed on January 30, 2017, by Yanghyo Kim, Yuan Du, and Mau-Chung F. Chang, entitled "MILLIMETER- WAVE CMOS TRANSCEIVER WITH PCB ANTENNA FOR CONTACTLESS WAVE-CONNECTORS," attorneys' docket number 30435.325-US-P1 (2017-434-1), which application is incorporated by reference herein.

This application is also related to the following commonly-assigned applications and patents:

U.S. Utility Application No. 14/456,922, filed on August 11, 2014, by Sai-Wang Tam and Mau-Chung F. Chang, entitled "MILLI-METER-WAVE- WIRELESS- INTERCONNECT (M2W2 - INTERCONNECT) METHOD FOR SHORT-RANGE COMMUNICATIONS WITH ULTRA-HIGH DATA RATE CAPABILITY," attorneys' docket number 30435.209-US-Cl (2009-445-3), now U.S. Patent No. 8,971,421, issued March 3, 2015, which application is a continuation of co-pending and commonly- assigned U.S. Utility Application No. 13/377,124, filed on December 8, 2011, by Sai- Wang Tam and Mau-Chung F. Chang, entitled "MILLI-METER-WAVE- WIRELESS- INTERCONNECT (M2W2 - INTERCONNECT) METHOD FOR SHORT-RANGE COMMUNICATIONS WITH ULTRA-HIGH DATA RATE CAPABILITY," attorneys' docket number 30435.209-US-WO (2009-445-2), now US. Patent No. 8,817,891, issued August 26, 2014, which application is a national stage under 35 U.S.C. Section 371 of and claims the benefit under 35 U.S.C. Section 365 (c) to co-pending and commonly- assigned P.C.T. International Application No. PCT/US2010/038033, filed on June 9, 2010, by Sai-Wang Tam and Mau-Chung F. Chang, entitled "MILLI-METER- WAVE- WIRELE S S -INTERCONNECT (M2W2 - INTERCONNECT) METHOD FOR SHORT- RANGE COMMUNICATIONS WITH ULTRA-HIGH DATA RATE CAPABILITY," attorneys' docket number 30435.209-WO-U1 (2009-445-2), which application claims the benefit under 35 U.S.C. Section 119(e) of co-pending and commonly-assigned U.S.

Provisional Patent Application Serial No. 61/185,946, filed on June 10, 2009, by Sai- Wang Tam and Mau-Chung F. Chang, entitled "MILU-METER- WAVE-WIRELESS- INTERCONNECT (M2W2 - INTERCONNECT) METHOD FOR SHORT-RANGE COMMUNICATIONS WITH ULTRA-HIGH DATA RATE CAPABILITY," attorneys' docket number 30435.209-US-P1 (2009-445-1); and

U.S. Utility Application No. 13/993,807, filed on June 13, 2013, by Mau-Chung F. Chang and Sai-Wang Tam, entitled "PERIODIC NEAR FIELD DIRECTORS (PNFD) FOR SHORT-RANGE MILLI-METER- WAVE- WIRELESS-INTERCONNECT

(M2W2-INTERCONNECT)," attorneys' docket number 30435.220-US-WO (2010-728- 2), now U.S. Patent No. 9,634,737, issued April 25, 2017, which application is a national stage under 35 U.S.C. Section 371 of and claims the benefit under 35 U.S.C. Section 365 (c) to co-pending and commonly-assigned P.C.T. International Application No.

PCT/US2011/065576, filed on December 16, 2011, by Mau-Chung F. Chang and Sai- Wang Tam, entitled "PERIODIC NEAR FIELD DIRECTORS (PNFD) FOR SHORT- RANGE MILLI-METER- WAVE-WIRELESS-INTERCONNECT (M2W2-

INTERCONNECT)," attorneys' docket number 30435.220-WO-U1 (2010-728-2), which application claims the benefit under 35 U.S.C. Section 119(e) of co-pending and commonly-assigned U.S. Provisional Patent Application Serial No. 61/424,554, filed on December 17, 2010, by Mau-Chung F. Chang and Sai-Wang Tam, entitled "PERIODIC NEAR FIELD DIRECTORS (PNFD) FOR SHORT-RANGE MILLI-METER- WAVE- WIRELESS-INTERCONNECT (M2W2-INTERCONNECT)," attorneys' docket number 30435.220-US-P1 (2010-728-1); all of which applications and patents are incorporated by reference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention.

This invention relates to a millimeter-wave complementary metal-oxide- semiconductor (CMOS) transceiver with a printed circuit board (PCB) antenna for contactless wave-connectors.

2. Description of the Related Art.

(Note: This application references a number of different publications as indicated throughout the specification by one or more reference numbers within brackets, e.g., [x]. A list of these different publications ordered according to these reference numbers can be found below in the section entitled "References." Each of these publications is incorporated by reference herein.)

Because of the increasing demand for data bandwidth in multimedia applications, the industry has come up with new interconnect standards, such as Thunderbolt™, USB (Universal Serial Bus) 3.0, DP (DisplayPort), HDMI (High-Definition Multimedia Interface), GbE (Gigabit Ethernet), etc. As a result, a data rate of 10 Gigabits per second (Gb/s) per channel is no longer uncommon in the consumer market.

However, as each interconnect standard evolves, serious challenges remain with regard to bandwidth scalability, power, and other fundamental physical limitations, such as mechanical reliability, thermal constraints, and overall system form-factor. Often times, connectors play important role in each generation because of their non-scalable nature and inherent discontinuities between physical layers, which causes non-ideal behavior.

Non-ideal behavior results in high-speed signals undergoing distortion, inter- symbol interference (ISI), and reduced signal-to-noise ratio (SNR). Although one can invest more resources in packaging and connector technologies [1], much effort is focused on the digital signal processing based pre-emphasis and equalization, which leads to a complicated transceiver architecture requiring calibration, software, and more power.

Meanwhile, recent research has suggested to remove the physical connection and replace it with short-distance wireless connectors. [2] The fundamental advantage comes from an available wide fractional bandwidth around a carrier frequency and its non- contacting air-interface.

Thus, there is a need in the art for improved methods of wireless data

transmission. The present invention satisfies that need.

SUMMARY OF THE INVENTION

To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a millimeter-wave CMOS transmitter or receiver flip-chip mounted on a PCB and an antenna deposited on the PCB, comprising a contactless wave-connector for wireless transmission.

In one embodiment, a transceiver is comprised of at least two contactless wave- connectors for transmitting and receiving millimeter-wave signals. A first one of the contactless wave-connectors is comprised of a transmitter and an antenna, and a second one of the contactless wave-connectors is comprised of a receiver and an antenna. The first one of the contactless wave-connectors is positioned opposite to the second one of the contactless wave-connectors, and the antenna of the first one of the contactless wave- connectors is positioned a specified distance of about 2 mm or less from the antenna of the second one of the contactless wave-connectors. The antenna of the first one of the contactless wave-connectors transmits the millimeter-wave signals that are received by the antenna for the second one of the contactless wave-connectors.

In one embodiment, the transmitter and/or receiver is a complementary metal- oxide-semiconductor (CMOS) device. Each of the contactless wave-connectors comprises a printed circuit board (PCB), and the CMOS device is flip-chip mounted on the printed circuit board, and the antenna is a folded-dipole antenna fabricated on the printed circuit board. The CMOS device and the antenna fit within an area of the printed circuit board that is about 1 mm by 3 mm or less.

The transmitter generates an on-off keying (OOK) modulated carrier signal using an oscillator (OSC), and the OOK modulated carrier signal is combined with data at a mixer to generate the millimeter-wave signals. The OOK modulated carrier signal is at least a 125 GHz signal, and the millimeter-wave signals are at least a 10 Gb/s signal.

The receiver uses a low noise amplifier (LNA) to amplify the millimeter-wave signals, which are down-converted to a baseband signal through a self-mixer, without using a frequency-synthesizer or carrier-synchronization, in order to output the data. The self-mixer uses a feedback-based trans-impedance amplifier.

BRIEF DESCRIPTION OF THE DRAWINGS

Referring now to the drawings in which like reference numbers represent corresponding parts throughout:

FIG. 1 A is a block diagram of a millimeter- wave transceiver system of the present invention.

FIG. IB illustrates a pair of contactless wave-connectors, according to one embodiment of the present invention.

FIG. 1C illustrates the elements of transmitter (TX) and receiver (RX) chipsets, according to one embodiment of the present invention.

FIG 2A is a graph of measured and extrapolated dielectric constant versus frequency (GHz) of a PCB, according to one embodiment of the present invention.

FIG. 2B is a graph of manufacturer provided and extrapolated loss tangent versus frequency (GHz) of the PCB, according to one embodiment of the present invention. FIG. 3 A is a side view of the air-coupling between the transmitter and receiver chipsets, according to one embodiment of the present invention.

FIG. 3B is an image of the top of a chipset, according to one embodiment of the present invention.

FIG. 3C is a graph of a simulated SI 1 parameter (dB) versus frequency (GHz) for an antenna, according to one embodiment of the present invention.

FIG. 3D is a graph of a simulated S21 parameter (dB) versus frequency (GHz) for an antenna, according to one embodiment of the present invention.

FIG. 4A is a schematic of a proposed CMOS transmitter, according to one embodiment of the present invention.

FIG. 4B is a three-dimensional (3D) model of a CMOS chipset flip-chip bonded to a printed circuit board, according to one embodiment of the present invention.

FIG. 4C is a graph of a simulated S21 parameter (dB) versus frequency (GHz) for a CMOS chipset flip-chip bonded to a printed circuit board, according to one

embodiment of the present invention.

FIG. 4D is an image of the top of a die for the CMOS transmitter, according to one embodiment of the present invention.

FIG. 5A is a schematic of a proposed CMOS receiver, according to one embodiment of the present invention.

FIG. 5B illustrates a link budget analysis of a proposed CMOS receiver, according to one embodiment of the present invention.

FIG. 5C is a graph of magnitude (dB) versus frequency (GHz) for the CMOS receiver, according to one embodiment of the present invention.

FIG. 5D is a graph of conversion loss (dB) versus input power (dBm) for the CMOS receiver, according to one embodiment of the present invention.

FIG. 5E is an image of the top of a die for the CMOS receiver, according to one embodiment of the present invention. FIG. 6A shows an output spectrum measurement captured from the CMOS transmitter, according to one embodiment of the present invention.

FIG. 6B shows a measured 14 Gb/s eye-diagram, according to one embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

In the following description of the preferred embodiment, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration a specific embodiment in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.

Overview

As interconnect technology advances, the need for higher bandwidth rises as well. A 10 Gb/s data rate is no longer surprising in the consumer market. For instance, a new USB 3.1 standard is equipped with a maximum bandwidth of 10 Gb/s. The inventors' previous work cross-referenced above has a limitation in bandwidth (6 Gb/s), because the carrier frequency is around 60 GHz.

This invention, on the other hand, is based on at least a 125 GHz carrier frequency, and achieves at least a 10 Gb/s data rate, and more preferably, a data rate of about 14 Gb/s. The invention includes the following elements:

• New Antenna and Flip-Chip Assembly: Unlike the inventors' previous work cross-referenced above, a new miniature antenna structure was developed for use on an inexpensive FR4 PCB (e.g., an FR4HR substrate), and the TX and RX chipsets are assembled on the PCB using a flip-chip process. The PCB and chipset assembly can be modular as well, which means it can be deployed and connected to any other system. • New Transmitter Architecture: A new transmitter exploits advanced CMOS technology to generate a 125 GHz carrier signal in order to increase the fractional bandwidth to support more than a 10 Gb/s data rate.

• New Down-Converting Self-Mixer: On the receiver side, a new self- mixing down-converter uses a feedback-based trans-impedance amplifier.

This allows for higher bandwidth than the inventors' previous work cross- referenced above, in order to support more than a 10 Gb/s data rate.

This invention can be deployed anywhere connectors are required. Examples include Thunderbolt™, USB 3.0, DP, HDMI, GbE, etc., and other interconnect standards. The major difference comes from the concept of a non-contact-based connector.

125 GHz Transceiver

FIG. 1A is a block diagram of a millimeter-wave (125 GHz) transceiver system where ultra-short distance (about 2 mm or less) contactless wave-connectors (CWCs) replace conventional mechanical connectors. This transceiver system can be used for consumer interconnect applications.

The contactless wave-connectors of this invention exploit 125 GHz CMOS TX and RX chipsets, and a compact PCB antenna, to realize high-speed (>10 Gb/s), low-cost, and energy-efficient connector solutions. An on-off keying (OOK) modulation technique is utilized for a non-coherent transceiver architecture. In addition, the antenna is designed on a standard PCB for compatibility with an existing infrastructure. The CMOS TX and RX chipsets are assembled with the antenna on the PCB through a flip-chip process.

The contactless wave-connector can be installed essentially anywhere in a given network topology as illustrated by the example in FIG. 1 A. In this example, an application host 100 is comprised of a processor 101, memory 102, and bridge 103, wherein the bridge 103 connects to a bus 104, for example, a PCI Express bus, having one or more ports attached thereto for connecting to various peripherals, for example, a network port 105 (e.g., a GbE port) that interfaces to a LAN/WAN 106, a data port 107 (e.g., a USB port) that interfaces to a mobile device 108, and/or a video port 109 (e.g., an HDMI or Thunderbolt™ port) that interfaces to a display 110. Each interface 111 between a port 105, 107, 109, and a peripheral 106, 108, 110, is comprised of two pairs of transmitters (TX) 112A and receivers (RX) 112B on two pairs of contactless wave- connectors 113, wherein each pair of transmitter TX 112A and receiver RX 112B communicates wirelessly via a pair of contactless wave-connectors 113.

FIG. IB is a schematic that further illustrates a pair of contactless wave- connectors 113, which are labeled as 113 A and 113B. The contactless wave-connectors 113 A, 113B are each comprised of a PCB 114 having a CMOS chipset 115 and an antenna 116 thereon. In one embodiment, each of the transmitters TX 112A and the receivers RX 112B comprises a CMOS chipset 115, which are referred to herein as CMOS TX chipset 115 A and CMOS RX chipset 115B, respectively, and a TX antenna 116A and an RX antenna 116B, respectively. However, other devices may be used in other embodiments.

As noted above, there are two pairs of CMOS TX chipsets 115 A and CMOS RX chipsets 115B in each interface 111 : (1) a contactless wave-connector 113 A comprised of a CMOS TX chipset 115 A on the port side connected via antennae 116A, 116B to a contactless wave-connector 113B comprised of a CMOS RX chipset 115B on the peripheral side, and (2) a contactless wave-connector 113B comprised of a CMOS RX chipset 115B on the port side connected via antennae 116B, 116A to a contactless wave- connector 113 A comprised of a CMOS TX chipset 115 A on the peripheral side, in order to provide full-duplex communications.

As shown in FIG. IB, contactless wave-connector 113B is positioned opposite to contactless wave-connector 113 A, with its antenna 116B a short distance above the antenna 116A of connector 113 A, so that the antenna 116A of connector 113 A can transmit millimeter- wave signals 117 that are received by the antenna 116B of connector 113B. However, the positions of the contactless wave-connectors 113 A, 113B may be reversed.

FIG. 1C illustrates the elements of the CMOS TX chipset 115 A and antenna 116A, and the CMOS RX chipset 115B and antenna 116B. In this invention, the CMOS TX chipset 1 ISA generates an OOK modulated 125 GHz carrier signal using a 125 GHz oscillator (OSC) 118, which is combined with input data 119 at a mixer 120, and the antenna (Ant.) 116A radiates the modulated signal as electromagnetic energy 117 to the antenna (Ant.) 116B. The CMOS RX chipset 115B uses a low noise amplifier (LNA) 121 to amplify the modulated signal, which is down-converted to a baseband signal through a self-mixer 122, without using a frequency-synthesizer or carrier- synchronization [3], and then output as data 123.

Antenna

FIG 2A is a graph of measured and extrapolated dielectric constant versus frequency (GHz) of an FR4HR substrate used as the PCB for simulation, and FIG. 2B is a graph of manufacturer provided and extrapolated loss tangent versus frequency (GHz) of the FR4HR substrate used as the PCB. Before designing the antenna structure, the inventors first characterized the FR4HR substrate by designing a transmission line (TL) calibration structure [4]. By measuring scattering parameters of different lengths of TL through a vector network analyzer, the inventors extracted the dielectric constant of a 3 mil and a 10 mil thickness for the substrate up to 67 GHz and extrapolated up to 200 GHz as shown in FIG. 2A. For the loss tangent, the inventors used manufacturer provided data up to 10 GHz and again extrapolated up to 200 GHz shown in FIG. 2B.

FIG. 3 A is a side view of the air-coupling, chip-to-antenna, flip-chip assembly, and an illustration of ground planes for impedance matching. Two contactless wave- connectors 113 A and 113B are shown, wherein connector 113 A is comprised of a CMOS TX chipset 1 ISA and an antenna 116 A, and connector 113B is comprised of a CMOS RX chipset 11SB and an antenna 116B. Connector 113B is positioned opposite to connector 113 A, with its antenna 116B a short distance above the antenna 116A of connector 113 A, so that the antenna 116A of connector 113 A can transmit millimeter-wave signals 117 that are received by the antenna 116B of connector 113B.

In this example, each antenna 116A, 116B is a 125 GHz folded-dipole antenna fabricated on its respective PCB 114. A ground plane 124 is placed about 13 mils underneath the antenna 116 A, 116B to act as a reflecting surface (close to λ/4 at 12S GHz). With the ground plane 124 specified, the antenna 116A, 116B dimensions are designed to match with a 100 Ω differential impedance. Then, a rectangular cavity 125 having dimensions of about 1.7 mm by 0.8 mm is formed by via- walls 126 of ground plane 127 to provide a higher directivity.

The CMOS TX and RX chipsets 115 A, 115B are directly mounted to their respective PCBs 114 by a flip-chip process using solder bumps 128. In each connector 113 A, 113B, a transmission line having a length of about 0.5 mm connects the CMOS TX and RX chipsets 115 A, 115B and antennae 116A, 116B with the 3 mil-depth ground plane 127 to maintain the 100 Ω differential characteristic impedance. When positioned opposite each other, the antennae 116A, 116B for the CMOS TX and RX chipsets 115 A, 115B are separated by a specified distance, which in one embodiment comprises about 2 mm or less.

FIG. 3B is an image of the top of a contactless wave-connector 113 that emphasizes that the flip-chip CMOS chipset 115 and antenna 116 together can fit within an area of about 1 mm by 3 mm on the PCB 114. The antenna 116 has a length of about 1.7 mm and a width of about 0.8 mm, and the antenna 116 is connected to the flip-chip CMOS chipset 115 by the transmission line having a length of about 0.5 mm.

FIG 3C is a graph of a simulated SI 1 parameter (i.e., reflection coefficient or return loss) versus frequency (GHz) looking into the antenna 116 port. Specifically, FIG. 3C represents how much power is reflected from the antenna 116. The return loss in FIG. 3C is maintained below -8 dB over a 40 GHz bandwidth.

FIG 3D is a graph of a simulated S21 parameter (i.e., the transmission

performance from one antenna to the other side of the antenna) versus frequency (GHz) showing the air-coupling loss performance. Specifically, FIG. 3D represents the transmission performance between the TX antenna 116A to the RX antenna 116B through an air-coupling of about 2 mm. The transmission performance experiences no worse than 12 dB loss over a 40 GHz bandwidth. Notice how the amplitude variation is confined within 4 dB as opposed to conventional connectors, which may induce more than 30 dB of notch in frequency response [5].

The above study indicates that the proposed air-coupling channel using the contactless wave-connectors 113 A, 113B can transmit more than 20 Gb/s of baseband data without requiring power hungry equalization or pre-emphasis. CMOS Transmitter

FIG. 4A is a schematic of a proposed CMOS TX chipset 115 A. The CMOS TX chipset 115A adapts an OOK modulation to enable an energy-efficient architecture. A reference (REF) signal 119 drives an on-chip 14 GHz phase-locked loop (PLL) 129, which clocks an on-chip Pseudo Random Bit Sequence (PRBS) (27-1) generator 130, which generates a 14 Gb/s data stream that drives a mixer's 120 tail current device. In order to perform the up-conversion, a free-running 125 GHz oscillator (OSC) 118 generates a 125 GHz carrier signal and drives the mixer's 120 differential pair through a transformer. After the up-conversion, the mixer 120 directly drives the off-chip feed-line and antenna 116A through a transformer without using an additional power amplifier.

From the link budget study explained in the next section, the inventors

intentionally avoided designing a power amplifier (PA). That is, the oscillator 118 generates enough power to transfer energy to the CMOS RX chipset 115B through an air- coupling channel.

FIG. 4B is a 3D model of the CMOS chipset 115 bonded to the PCB 114. Also shown are the ground plane 124 and solder bumps 128. For the CMOS-to-PCB flip-chip assembly shown in FIG. 4B, the inventors had to increase the on-chip pad 131 size to 100 um diameter, in return adding significant amount of capacitance as compared to a design library based pad. To perform output matching with this constraint, the inventors implemented a pad-tapped matching shunt inductor 132. From HFSS (High Frequency Structure Simulator) simulations, the CMOS-pad/flip-chip-bump (80 um diameter)/PCB- pad contributes 2.8 dB loss. Adding from the result of the TX antenna 116A to the RX antenna 116B in FIG 3D, the final end-to-end transmission efficiency becomes 16 dB at 125 GHz. Here again, the amplitude of S21 is maintained within 4 dB variation over a 40 GHz span. The CMOS TX chipset 115 A generates 0 dBm output power at the input of on-chip CMOS-pad while consuming 35 mW of power.

FIG 4C is graph that shows the flip-chip S21 transmission loss and total link transmission performance versus frequency (GHz), including the TX and RX side of the flip-chip assembly, antenna and 2 mm air-coupling channel.

FIG. 4D is a photograph of the die for the CMOS TX chipset 115 A, showing the placement and dimensions of the oscillator 118 and mixer 120, as well as the phase- locked loop 129 and Pseudo Random Bit Sequence generator 130.

CMOS Receiver

FIG. 5 A is a schematic of a proposed CMOS RX chipset 115B including a 1 -stage low-noise amplifier (LNA) 121 and feedback-based self-mixer 122, FIG. 5B shows a link budget analysis, FIG. 5C is a graph that shows the LNA 121 gain, FIG. 5D is a graph that shows the self-mixer 122 conversion loss, and FIG. 5E is a die-photo of the CMOS RX chipset 115b. As shown in FIG. 5 A, the CMOS RX chipset 115 A starts with a matching transformer for the antenna 116B and provides 10 dB of gain via the 1 -stage low-noise amplifier (LNA) 121. The link budget analysis in FIG. SB reveals that the noise floor of the CMOS RX chipset 115B begins at -70 dBm considering the 28 GHz bandwidth (double-side band of 14 Gb/s data). Going through 15-19 dB of transmission loss, the - 20 dBm input signal (RF IP and RF IN) from the antenna 116B arrives at the front-end of the CMOS RX chipset 115A. The LNA 121 amplifies the signal up at -10 dBm, and the front-end adds 10 dB of noise figure as shown in FIG. 5C. In addition, 15 dB of minimum SNR is added to the floor to achieve a bit-error-rate (BER) of 10 ^"12 for the non- coherent OOK de-modulation. Although the -10 dBm modulated signal further undergoes 21 dB of self-mixing 122 conversion loss, as shown in FIG. 5D, with the updated noise floor at -45 dBm, the system has room for another 14 dB of SNR margin. Unlike the resistor-loaded self-mixer design in [3], the inventors employed a self-mixer 122 that uses a feedback-based trans-impedance amplifier in order to deliver a wider down-conversion bandwidth.

Lastly, high-speed buffers 133 amplify the down-converted 14 Gb/s baseband signal, and the resulting output signals (OP and ON 123, and Sensing Bias 133) are used to drive a scope for output spectrum and eye-diagram measurements, shown in FIGS. 6A and 6B. The CMOS RX chipset 115B consumes 25mW, and its die-photo is shown in FIG. 5E, including the LNA 121, self-mixer 122 and drivers 133.

Experimental Results

FIG. 6A shows the output spectrum measurement captured from the CMOS TX chipset 115 A, and FIG. 6B shows a measured 14 Gb/s eye-diagram.

To demonstrate the radiated power from the CMOS TX chipset 115 A, the inventors first measured the modulated output spectrum using a W-band horn antenna and harmonic mixer. Although 125 GHz is actually not within the W-band region, given the output power from the CMOS TX chipset 115 A and the conversion loss from the harmonic mixer, the inventors were able to capture the CMOS TX chipset 115A output spectrum and confirmed that indeed there is carrier signal power at 124.7 GHz and a modulated sideband, as shown in FIG. 6A.

After confirming radiated power with modulation, the inventors set up a data link between the CMOS TX chipset 115A and CMOS RX chipset 115B. First, a 55 MHz reference clock 119 is provided for the 14 GHz PLL 129 to be locked. The same 55 MHz reference clock 119 is used for triggering an oscilloscope. Then, the CMOS RX chipset 115B is placed underneath the CMOS TX chipset 115 A with a 2 mm air-gap. The down- converted and amplified signal is fed into the scope to measure the 14 Gb/s of eye- diagram, as shown in FIG. 6B. As the wide-opened eye-diagram indicates at 71.4 ps, there is a margin to go beyond 14 Gb/s.

Conclusion

This invention demonstrates a contactless wave-connector for consumer oriented interconnect solutions that provides wide-bandwidth with a reduced form factor and power consumption. The demonstrated 125 GHz CMOS TX and RX chipsets combined on a PCB with an antenna achieves a 14 Gb/s data rate without using complex and power hungry equalization circuits. The CMOS TX and RX chipsets are implemented in TSMC 65 nm CMOS technology and occupies 0.5 mm x 0.3 mm of the CMOS TX and 0.5 mm x 0.4 mm of the CMOS RX silicon area. The CMOS TX and RX chipsets consume 35 mW and 25 mW of DC power, respectively, achieving 4.28 pj/bit energy efficiency.

References

The following references are incorporated by reference herein: 1. D. G. Kam and J. Kim, "40-Gb/s Package Design Using Wire-Bonded Plastic Ball Grid Array," IEEE Transactions on Advanced Packaging, vol. 31, no. 2, pp. 258-266, 2008.

2. K. Kawasaki, et al., "A Millimeter-Wave Intra-Connect Solution," IEEE Journal of Solid-State Circuits, vol. 45, no. 12, pp. 2655-26642010.

3. Y. Kim, et al., "High-Speed mm- Wave Data-Link based on Hollow Plastic Cable and CMOS Transceiver," IEEE Microwave and Components Letters, vol. 23, no. 12, 2013.

4. N. K. Das, et al., "Two Methods for the Measurement of Substrate Dielectric Constant," IEEE Transactions on Microwave Theory and Techniques, vol. 35, no. 7, 1987.

5. Y. Du, et al., " A 16 Gb/s 14.7 mW Tri-Band Cognitive Serial Link Transmitter with Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection in 28 nm CMOS," IEEE Symposium on VLSI Circuits, 2016.

Summary

The foregoing description of one or more embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.