received by the International Bureau on 03 May 2019 (03.05.2019)

1. A mixer, comprising:

four cells wherein each cell has a drain terminal, a source terminal and a gate terminal;

wherein the drain terminals of the first and second cells are connected at a first RF input terminal;

wherein the drain terminals of the third and fourth cells are connected at a second RF input terminal;

wherein the source terminals of the first and third cells are connected at a first IF terminal;

wherein the source terminals of the second and fourth cells are connected at a second IF terminal;

wherein the gate terminals of the first and fourth cells are connected at a first LO terminal;

wherein the gate terminals of the second and third cells are connected at a second LO terminal;

wherein each cell comprises first and second series connected devices;

wherein a ratio of a gate width of the first series connected device to a gate width of the second series

connected device in each cell is between one to one and one to four .

2. The mixer of claim 1, wherein the first device and the second device is a field effect transistor.

3. The mixer of claims 1 or 2 , wherein the first device is connected to the source terminal of the cell and the second device is connected to the drain terminal of the cell.

4. The mixer of any one of claims 1 - 3, wherein the first device and the second device is a high electron mobility transistor (HEMT).

5. The mixer of any one of claims 1 - 4, wherein a first device source is connected to a first frequency source and a second device drain is connected to a second frequency source.

6. The mixer of any one of claims 1 - 5, wherein gates of the devices are connected to a local oscillator to have common DC gate bias voltage.

7. The mixer of claim 6, wherein half of the gates of the devices receive a 180 degrees out of phase local oscillator signal .

8. The mixer of any one of claims 1 - 7, wherein one or more of the plurality of active devices comprises one or more from the group consisting of HEMT, CMOS and BJT.

9. A method of reducing a third harmonic of an RF signal in a mixer comprising a plurality of unit cells, the unit cells being connected in a ring with an RF input and LO input and having a IF output, the method comprising:

providing at least a pair of active devices in each of said unit cells, each of said active devices having a pair of current carrying electrodes and at least one control

electrode;

connecting the at least a pair of active device in each of said unit cells so said current carrying electrodes are coupled in series with each other and also connected to current carrying terminals of an associated united cell;

connecting the at least a pair of active device in each of said unit cells so said control electrodes are coupled in parallel with each other and also connected to a control terminal of the associated united cell; and

adjusting a size[s] of at least one semiconductor element in each of the pair of active devices in each of said unit cells relative to another semiconductor element in each of said unit cells to reduce said third harmonic.

10. The method of claim 9 wherein the size of the

semiconductor element in each of the pair of active devices in each of said unit cells which is adjusted is a width of a gate of each of the pair of active devices in each of said unit cells .

11. The method of claims 9 or 10 wherein the size of the semiconductor element in each of the pair of active devices in each of said unit cells which is adjusted is an area of an emitter of each of the pair of active devices in each of said unit cells.

12. A mixer, having an intermediate frequency (IF) side and a radio frequency (RF) side, the mixer comprising:

a plurality of unit cells each comprising a plurality of active devices of different sizes arranged in series to reduce or inhibit generation of a non-linear third harmonic by the mixer .

13. The mixer of claim 12, wherein a size ratio of the active devices in each unit cell is at least 1:2 (IF side: RF side).

14. The mixer of claim 12, wherein a size ratio of the active devices is between 1:2 and 1:4 (IF side: RF side).

15. The mixer of any one of claims 12 - 14, wherein the plurality of active devices in each unit cell are connected in series between current carrying electrodes of said active devices while control electrodes of said active devices in each unit cell are connected in parallel.

16. The mixer of any one of claims 12-15, wherein the series connection of the active devices in each unit cell comprises a connection of a drain of a first active device connected to a source of a second active device.

17. The mixer of any one of claims 12 - 16, wherein a source of first active device is connected to IF side and a drain of a second device drain is connected to the RF side.

18. The mixer of any one of claims 12 - 17, wherein gates of the plurality of active devices are connected to have the same DC gate bias voltage.

19. The mixer of any one of claims 12 - 18, wherein half of the gates of the plurality of active devices are connected 180 degrees out of phase with respect to a remaining half of the gates .

20. The mixer of any one of claims 12 - 19 is a resistive mixer and wherein a single balanced resistive mixer includes two unit cells, a double balanced resistive mixer includes four unit cells and a double-doubly balanced mixer includes eight unit cells.

21. The mixer of any one of claims 12 - 20 wherein the active devices of different sizes arranged in series have different conductances .

22. The mixer of claim 21 wherein the active devices of different sizes arranged in series also have different output capacitances .

23. A method for producing a unit cell used in a mixer, the method comprising: providing a plurality of active devices of different sizes connected in series in said unit cell.

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24. The method of claim 23 wherein active devices in said unit cell having differing conductances and capacitances.

25. A unit cell for use in a mixer, the unit cell comprising a plurality of active devices of different sizes connected in series .

26. The unit cell of claim 25 wherein the plurality of active devices comprises a pair of FETs, a first one of the pair of FETs having a first gate width and a second one of the pair of FETs having a second gate width and wherein a ratio of the first gate width to the second gate width is between one to one and one to four.

27. The unit cell of claim 25 wherein the plurality of active devices comprises at least a pair of FETs, each FET having at least two current carrying electrodes and at least one gate electrode, the at least two current carrying electrode of the at least a pair of FETs being connected in series and the at least one gate electrode of the at least a pair of FETs being connected in series.

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