Title:
MIXER
Document Type and Number:
WIPO Patent Application WO/2019/203044
Kind Code:
A1
Abstract:
The present invention cancels parasitic capacitance over a wide bandwidth, increases off-impedance, and improves frequency conversion efficiency. A negative capacitance circuit 2 is connected between the drain and the source of a mixer transistor 1. The negative capacitance circuit 2 is thereby connected in parallel to a parasitic capacitance Cp produced between the drain and the source of the mixer transistor 1, and this negative capacitance circuit 2 connected in parallel makes it possible to cancel the parasitic capacitance Cp over a wide bandwidth.
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Inventors:
JO TERUO (JP)
HAMADA HIROSHI (JP)
NOSAKA HIDEYUKI (JP)
HAMADA HIROSHI (JP)
NOSAKA HIDEYUKI (JP)
Application Number:
PCT/JP2019/015300
Publication Date:
October 24, 2019
Filing Date:
April 08, 2019
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE (JP)
International Classes:
H03D7/12; H03D7/00
Foreign References:
JP2002164745A | 2002-06-07 | |||
JPS60157317A | 1985-08-17 | |||
US20150372844A1 | 2015-12-24 |
Attorney, Agent or Firm:
YAMAKAWA, Shigeki et al. (JP)
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