The invention relates to a ΣΔ modulator and a ΣΔ A/D converter.

Technical Background of the invention The emergence of powerful digital signal processing in CMOS VLSI technology creates the need for high-resolution A/D converters that can be integrated in fabrication technologies optimized for digital circuits and systems. However, the same scaling of VLSI technology that makes possible the continuing and dramatic im¬ provements in digital signal processing also severely con¬ straints the dynamic range available for implementing the inter¬ faces between the analog and the digital representation of sig¬ nals. Oversampled AD converters based on ΣΔ modulation use sam¬ pling frequencies well above the Nyquist rate in order to ex¬ change resolution in time for resolution in amplitude.

The ΣΔ conversion technique exists since many years. Technologi¬ cal advances make the technique practical and their use wide¬ spread. The converters are used in applications such as communi¬ cation systems, consumer and professional audio, industrial weight scales, and precision measurement devices. The key fea¬ ture of the ΣΔ converters is that they are the only low-cost conversion method which provides both high dynamic range and flexibility in converting low-bandwidth input signals (see Ste¬ ven R. Norsworthy, Richard Schreier and Gabor C. Temes in "Delta-Sigma Data Converters" from John Wiley & Sons, 1997.

The performance of digital signal processing systems is gener¬ ally limited by the precision of the digital input signal which is achieved at the interface between the analog and the digital signal representation. ΣΔ modulation based A/D conversion tech¬ nology is a cost effective approach for high-resolution convert-

Bestatigungskopie ers which can ultimately be integrated on digital signal- processor ASICs. Known ΣΔ converters employ ΣΔ modulators built with active analog components. Such analog integrated circuits have high design costs. The resulting oversampling A/D convert¬ ers then achieve a relatively high resolution with more than 12 bits and Nyquist rates above 50 kHz, and the development trends are towards even higher Nyquist rates.

However, the development costs of these components makes inte¬ gration of ΣΔ converters less interesting for application areas, as for certain sensor-signal A/D conversions, where lower reso¬ lutions and lower Nyquist rates are sufficient.

Summary of the invention It is therefore an object of the invention to provide a ΣΔ modu¬ lator, which can be directly integrated, e.g. on digital signal- processor ASICs.

It is a further object of the invention to provide a ΣΔ modula¬ tor, which does not use any active analog components to reduce integration costs.

It is another object of the invention to provide a ΣΔ modulator, which can be implemented in a software driven control unit .

It is a further object of the invention to provide a ΣΔ con¬ verter having the advantages of use of the ΣΔ modulators accord¬ ing to the invention.

Therefore, a new architecture for a first-order ΣΔ modulator is proposed, that uses as the only analog components a resistor and a capacitor to realize the (lossy) analog integrator-part of the modulator. Because there is no need for active analog components to realize the ΣΔ modulator, it is possible in implementing the "digital-only" ΣΔ A/D converter directly in an FPGA (Field Pro¬ grammable Gate Array) . Alternatively, it is possible to imple¬ ment the approach in the software of a microprocessor.

The "digital-only" implementation of the proposed ΣΔ A/D con¬ verter greatly enhances compatibility: Any digital FPGA or mi¬ croprocessor can be programmed to implement the necessary ΣΔ- based A/D conversion directly on chip or in software, respec¬ tively, without using any additional active analog components. An important advantage then is that new applications can be de¬ signed with the high assurance of a first-right implementation, as digital circuit designs provide, thus eliminating the higher design risks of mixed analog-digital designs.

Although the new architecture has limited resolution due to theoretical limitations imposed by the used lossy integrator, there is a broad range of application areas, mainly in sensor- data analog-to-digital conversion. It is to be noted that the simplicity of the approach outweights resolutions limited to something in the range of 8 to 10 bits and Nyquist rates consid¬ erably lower than that of conventional ΣΔ A/D converters.

In such a sigma-delta modulator all active analog components are replaced by a single D-flip-flop. The resulting basic "digital only" sigma-delta modulator circuit (Fig. 2) shows the behavior of a "lossy sigma-delta modulator" discussed by Feely/Chua. As "lossy sigma-delta modulators" used in sigma-delta A/D convert¬ ers suffer from a limited conversion resolution, another, im¬ proved, "digital-only" sigma-delta modulator is presented. The modified "digital-only" sigma-delta modulator, using an addi¬ tional dither generator, results in sigma-delta A/D converters with a significantly increased resolution. Both, the basic and the improved "digital-only" sigma-delta modulators enable very low cost implementations in programmable logic devices and mi¬ croprocessors.

Brief description of the drawings A solution for said object of the invention is achieved with a device with the features of claim 1.

Further objects and advantages are achieved through the features of the subclaims . Exemplary embodiments of the invention are disclosed in the following description in which: Fig. 1 shows a schematic of a ΣΔ modulator according to prior art, Fig. 2 shows a schematic of a ΣΔ modulator according to a first embodiment of the invention, Fig. 3 shows a schematic of a ΣΔ modulator according to a sec¬ ond embodiment of the invention, Fig. 4 shows a schematic of a ΣΔ converter according to the in¬ vention, Fig. 5 a graphic representation of a simulated devil's stair¬ case, Fig. 6 shows a block diagram of the test environment for over- sampled AD converters, Fig. 7 a graphic representation of a devil's staircase obtained in hardware tests, Fig. 8 shows a test input signal y [n] (dashed) and demodulated output signal y[n] (solid) , Fig. 9 shows a schematic of a ΣΔ modulator according to a third embodiment of the invention, Fig. 10 shows a schematic of a ΣΔ modulator according to a modi¬ fied third embodiment of the invention, Fig. 11 shows the network of Fig. 10, and Fig. 12 a block diagram of a further test environment using the oversampling A/D converter structure with a warping unit .

Fig. 1 shows a ΣΔ modulator according to prior art. A voltage Vin is added to a feedback voltage Vfeedback at the adder 1. The re¬ sulting summed voltage signal is integrated in integrator 2, passes a quantizer 3 and a sample & hold circuit 4 to provide the digital signal Vmod.

Fig. 2 shows a schematic of a ΣΔ modulator according to a first embodiment of the invention. Upon comparison of Fig. 1 with Fig. 2, the D-flip-flop 10 (DFF) realizes the quantizer 3, the sam- ple-and-hold 4 and the negative feedback (negative input in sum¬ mer 1) by using the inverted DFF output for feedback. The D- flip-flop 10 (DFF) can be implemented in an FGPA or as a digital input to a microprocessor. The DFF represents a threshold in¬ put/output port of the involved FPGA or the microprocessor, re¬ spectively. The DFF is clocked by the oversampling frequency fQ and processes an analog input 11 according to formula (1) :

where T0 is the oversampling interval, T =l/f . Note that this

DFF 10 acts as quantizer in the ΣΔ converter and that it pre¬ pares the negative feedback by a sign change. The D-flip-flop 10 combines the function of an quantizer and a sample & hold unit.

The current source /„ , reference numeral 12, represents the ana¬ log input signal to be converted to digital form. In the shown main application this current signal comes from a photo-diode, but any sensor whose output signal is a current, or can be con- verted to a current, can be interfaced by the circuit to a digi¬ tal hardware.

The input current signal in , 12 and the feedback current signal i (with logically negative sign) , reference numeral 13, are summed in node 14. It is assumed that there is no current flow into the DFF to input 11. This is equivalent to the assumption that if flows in line portion 15 to node 11. Line portion 15 can, of course, be omitted, when feedback current signal 13 is con¬ nected to node 14. The capacitance C1 reference numeral 16, acts as an integrator for the total current and the resulting voltage across it is the input to the clocked quantizer-block DFF. In¬ verted output 17 of the DFF 10 is connected via the resistor R having the numeral 18 to line 13 and therefore to node 14.

The operation of the circuit in Fig. 2 can be modeled for left- open right-closed time intervals (nT0,(n+I)T0] by formula (2)

where we have defined the equivalent input voltage v by vs=R-is, and where v [n] is the capacitor voltage at the end of the previ¬ ous interval ((n-\)T0,nT0], ve[n]=ve(nT0) .

To obtain a circuit description in the form used by other au¬ thors, it is useful to transform the state variable v (t) in formula (2) into a new state variable u(fc) according to

In this new state the circuit is described by formula (3)

u.=f-- \ λ u+—1 (x-sffi(u[n])), RC RC where sgn(-) denotes the signum function, and the new input x(t) is related to v (t) by x=-\l(Vdd /2)-vs . The output of the trans¬ formed circuit is sgn(u[n]) and is a sequence of numbers "+1" and "-1" which may by symbolically represented by "bits" 1 (+1) and 0 (-1) . The output of the proposed circuit, q(vc[n]) , is a se¬ quence of numbers V and 0 and is related to the output of the transformed circuit by q(vc[n])=(sgn(u[n])+l))-VM/2.

Because we are only interested into the output sequence sgn(u[π]) and the sequence of states at the end of the left-open time intervals (nT0,(n+\)T0], u(t -(n+\)T0)u[n+\] , we solve formula (3) for these time intervals (nT0,(n+\)T0] and evaluate at t =(n+\)T0. Superimposing the free response due to initial conditions u(nT0+) =u[n] being the final state of the previous interval

((n-\)T0,nTϋ] (superscript "+" indicating that the argument nT0 be¬ longs to the left-open interval (nT0,(n+\)T0] ) , and the forced re¬ sponse due to the input x(t) -sgn (u [n] ) , t e(nT0,(n+]T0], it is ob¬ tained, after evaluating at t =(n+\)T0 , the following first-order difference equation formula (4) : u[n+\]=pu[n]+(\-p)(x[n+\]-sgn(u[n])), where g =l-/> . Here the feedback gain p is given in terms of the parameters of the circuit, R and C1 and the oversampling inter¬ val T by p =exp{-ro/(RC)) , and the input gain g is, as indicated, related to p by g=l-p.

The input x[π+l] in formula (4) is related to the true input x(t) in the differential equation (3) as follows: If x(t) is a piecewise constant signal, that is, it is a constant inside the intervals (nT0,(n+])TQ\, x[n+l] denotes these constant values and the description formula (4) is an exact discrete equivalent of formula (3) . If x(t) is not a piecewise constant signal, it may¬ be assumed in practice that it is slowly time-varying with re¬ spect to the oversampling-interval duration TQ and that it is bounded. From the mean-value theorem of the integral calculus it is known then that x[n+l] is a sample of x(fc) at some time in¬ stant ζ ≡(nT0,(n+Y)T0]. Likewise we may interpret x[n+l] as an aver¬ age value of x(t) in (nT0,(n+Y)T0] (the RC combination in the cir¬ cuit filters the signal x(t)) .

We note that the difference equation (4) is the single-loop lossy ΣΔ system analyzed by other authors such as OrIa Feely and leon 0. Chua in "The effect of integrator leak in Sigma-Delta modulation" in IEEE Trans. Circuits Syst . , 38 (11) : 1293-1305, No¬ vember 1991. Compared to the sigma-delta modulator analyzed in said reference, this modulator has the additional constraints: '■""f^l' g=l-p that is, the loss p of the discrete-time equivalent modulator in equation (4) is given by the design of the analog realization — the time constant RC — and by the selected oversampling fre¬ quency f =l/T ; and the input gain g of the discrete-time equiva¬ lent modulator in (4) is fixed once the feedback gain p is se¬ lected. Intuitively, it is clear that designing a feedback gain p as close to 1 as possible is preferable, because p approaching 1 means approaching the ideal non-lossy integrator situation; however, it can be seen that in the limit p—»1 the input gain g to the (for p=l ideal) accumulator becomes zero, killing the ap¬ proach.

We next discuss some basic theoretical limitations of the lossy ΣΔ modulator circuit, that is, we discuss the effects of p<l, Feely and Chua discuss in their paper as mentioned above the lossy sigma-delta modulator (4) for DC input signals: For modu¬ lators with ideal integrator and constant input, the output of the system (when averaged over a "long enough" time period) equals the input; for integrators with leak, however, they show that the plot of input versus average-output is no longer linear but has a fractal "staircase" structure, the devil's staircase. Therefore, the resolution of the modulator is limited by the width and the displacement of these steps.

Figures 7 and 8 in said paper show the devil's staircase of the constant-input x to average-output map of a lossy sigma-delta modulator with p=0.8 for -l≤x≤l. We have reproduced such a devil's staircase by the curve "devil's staircase" in Fig. 5 together with the characteristics of a "uniform quantization" of the interval -l≤x≤l with £>=4 bits. Note that this low 4bit reso¬ lution is used to make clearly visible the characteristics of the resulting staircase; as shown below, the circuit according to the invention achieves a much higher resolution. It can be seen that the widest step of the devil's staircase appears in the vicinity of zero inputs. The reference Feely and Chua gives for the width of this widest step a value of 2 (1-p) / (1+p) .

If the final goal of our complete sigma-delta converter is to obtain a uniform quantization of the interval -l≤x≤l with b bits, as Fig. 5 shows for Jb=4bits, we argue that the widest step-width must be smaller than the aimed-at resolution. Formula (5)

is obtained for lower limits of the allowable loss p. Table 1 shows the minimally needed loss values that are, in the best case, necessary to achieve a uniform quantization with b bits; "best case" means that we use an averaging of the sigma-delta modulator output bit-stream over a "long enough" time period, that is, that we use a sufficiently powerful decoding in the subsequent digital processing stage.

Table 1:

In the example shown in Fig. 5 the mentioned displacements of the steps in the devil's staircase with respect to the "ideal y-x" characteristic is seen. We argue that the errors introduced by these displacements can be removed by employing a pre-warping in the decoder. So the displacements of the steps from the "ideal y=x" positions are the lesser problem, but no decoder can remove the errors due to non-zero step widths in the devil's staircase (the sigma-delta modulator according to the invention) is just not able to distinguish inputs lying in intervals of same height of the devil's staircase. The accompanying loss of resolution is a non-linear function of the input, and the great¬ est loss of resolution occurs in the neighborhood of the ra¬ tional numbers with lowest denominators, see also the discussion in Feely and Chua.

As far we have not yet discussed the influence of the non-unity gain g of the sigma-delta modulator. Feely and Chua note that a non-unity gain g has only an influence on how quickly the modu¬ lator's output sgn(u[n]) enters periodicity: sgn(u[π]) latches onto its periodic cycle as soon as the state u [ή] enters the re¬ gion [g(x-l) ,g(x+l) ) . For the ΣΔ modulator with g=l-p we now ar¬ gue as follows: If we like to obtain a better resolution, we must realize a larger p according to Table 1. Such a larger p consequently gives a smaller g=l-p, and the latching interval [g(x-l) ,g(x+l) ) becomes smaller. Therefore, we expect that it takes more ΣΔ modulator clock cycles for sgn(u [n] )—the ΣΔ modu¬ lator output bit-stream—to enter periodicity.

To find the number of sigma-delta modulator clock cycles needed for u[n] to enter into the interval [g(x-l) ,g{x+l) ) , we have programmed an exhaustive search over possible DC input values x[n+l] =const=x and initial conditions u[0] , determining the maximum number of clock cycles needed to enter said interval . In the rectangle (-l≤x≤l) x (-l≤u [0] <1) we find for p-pmin and g=l-p the results compiled in Table 2.

Table 2

Although we have done experiments with various resolutions of the rectangle (-l≤x≤l) x (-l≤u [0] <1) , and we have always obtained the values given in Table 2, these experiments are of course no proof for correctness. Nevertheless, we are convinced that the obtained figures for the number of clock cycles needed for sgn(u[n]) to enter periodicity are, at least, good indications.

An idea to reduce the maximum number of clock cycles needed to enter the latching interval is to use "dither noise:" We add to the Dc input value to be converted random numbers, x\-$x+w[ή] with w[n] a low-variance noise sequence, and hope that the bit se¬ quence sgn(u[n]) sooner enters periodicity. A consecutive ques¬ tion then is whether sgn(u[.n]) stays, in the presence of noise, on its periodic cycle. We have found, however, that "dither noise" does not help; on the contrary, it increases the maximum number of needed clock cycles, with larger noise levels leading to stronger increases. To verify that the arguments above are correct for the analog- digital circuit in Fig. 2, we have performed simulations with

MATIOAB / S IMULINK .

Concerning the minimally needed loss-values pm±n for a target resolution, we find by our mixed-signal simulations that our circuit indeed achieves the expected resolutions. As an example, the curve "simulated staircase" in Fig. 5 shows the obtained staircase for p = pmm(4bits) =0.8667 , g=l-p. Simulations for bits Jbe{5, 6, 7, 8, 9, 10} with values of p according to Table 2 yield corresponding results. As the steps in the respective staircases become very small and are hardly visible, we do not present here the respective graphs.

Fig. 5 shows uniform quantization for £>=4bits, devil's staircase obtained as average output of a single-loop lossy sigma-delta modulator with p=0.8 and g=l, and the staircase obtained by simulating the mixed analog-digital circuit for

Concerning the latching onto limit cycles, our simulations of the analog-digital circuit in Fig. 2 re-obtain the worst-case values given in Table 2. Unfortunately, these worst-case values are quite high: For a ten bit resolution, for instance, they suggest that we would have to wait 2834 clock cycles before we could start with the averaging in the decoding procedure. These worst-case arguments are, however, only valid if we operate our ΣΔ modulator with a sample-and-hold running at the Nyquist rate. When we sample a signal with a sample-and-hold running at Ny¬ quist rate, then the sampled sequence of Dc values are independ¬ ent of each other and, therefore, of the initial conditions, be¬ cause the initial conditions are the final conditions of the last operation interval Operating the ΣΔ modulator without a sample-and-hold unit does not produce the worst-case situation.

Furthermore, these worst-case values are not realistic in the case of time-varying input signals. Therefore, we have simulated an exhaustive search over possible Dc input values x[n+l] =constx and initial conditions u[0] to determine the number of clock cy¬ cles needed to enter periodicity. There is a wide valley with a low number of needed clock cycles to enter periodicity. This ob¬ servation clearly indicates that the worst case figures are not too relevant for time-varying signals to be converted. To under¬ pin this claim, we have performed mixed-signal simulations with a sinusoidal input-signal applied to our ΣΔ modulator, and have traced the sequences of input values and initial conditions. These two sequences then define a locus in the plane "DC in¬ put/initial condition" . The simulation results indicate that for time-varying input signals the needed number of clock cycles to enter periodicity is in fact very low: It is true that the no¬ tion "needed number of clock cycles to enter periodicity" is not well defined for time-varying input signals as it is for Dc input signals. We here cross-compare only to gain an idea of what hap¬ pens in the much more complicated situation of time varying in¬ puts. For our sinusoidal input-signal simulations we have seen that said path stays, after an initial downhill movement due to intentionally used worst-case initial conditions for the com¬ plete simulation, always in the bottom of the valley of the landscape.

Fig. 6 shows a block diagram of the test environment for over- sampled AD converters: The ΣΔ modulators are operated in real¬ time, and the deconding procedures run off-line. To test and to characterize ΣΔ modulators built according to the invention in hardware, we have built a test environment for oversampling AD converters. Fig. 6 shows its block diagram. Whereas this test environment lets the modulator part of over- sampling converters run in real time, associated decoding algo¬ rithms may be tested and characterized by an off-line post¬ processing on a host computer. This off-line decoding facility allows easy experimentation with alternative decoding procedures proposed in the literature, but applies to bit-streams from modulators running in real time on true analog hardware compo¬ nents. The ΣΔ modulator according to Figure 2 runs, as men¬ tioned, in real time and is driven by a test current-signal source. This current source is controlled by a software running on a real-time DSPACE system (see "Real-time development system, autobox with dsllO3 board, 2004, dspace.com) , allowing to freely generate signal forms of the analog current-signal to be con¬ verted. The bit stream of the ΣΔ modulator under test is clocked into a GECKO system (see Marcel Jacomet et al. "On a development environment for real-time information processing in systems-on- chip solutions" in IEEE 14th Symposium on Integrated Circuit and System Design, SBCCI' 04, Brazil. 10-15 September 1991), where it is converted to 32bit wide packets that are in turn read-back to the DSPACE system. Presently, the DSPACE systems runs at clock fre¬ quencies of up to 7OkHz, and the ΣΔ modulator can run at 50OkHz. ΣΔ modulator bit-streams collected on the DSPACE system can be read-back to the host computer for later off-line processing, but the host computer can program the DSPACE software for test- signal generation as well.

First measurements on our test environment concern Dc input sig¬ nals; they confirm our theoretical and simulation results. The curve measured staircase for pmm(4bits) in Fig. 7 very well com- pares to the curve theoretical devil's staircase pmn(4bits) . For comparison we also supply the curve measured staircase pmιn(lObits) . Fig. 7 shows uniform quantization for jb=4bits, devil's staircase obtained for pmm{4bits) , measured staircase for pmm(4bits) , and meas¬ ured staircase for pmn(\Obits) .

Concerning the dynamic performance of the novel ΣΔ modulator, we have setup an overall experiment—including the decoding stage—as follows: On the MATLAB level we generate a sinusoidal signal y [n] with frequency fg±n and sampling frequency fo=5OOkHz. A resampled version of this signal y [n] is sent to the digital-to-analog converter of the DSPACE system running at a sampling frequency of 7OkHz. This DSPACE output signal controls our current-source gen¬ erating the input signal for the ΣΔ modulator under test. The ΣΔ modulator is clocked with 50OkHz to generate its bit stream. Our test-environment reads the generated bit-stream and passes it to the off-line decoding stage realized in MATLAB. Here we presently only use a sine2 filter. The resulting sample sequence y[n] is next compared to the original signal y [n] , see Fig. 8. Note that

we have not yet applied a sine2 corretion to the output signal y[n] , which exlains the reduced amplitude of the output signal as well as its shift in time in Figure 8.

For a numerical comparison we compute the error sequence

^D-"] =yo[n]~y[n] > an<3 in turn its power P&, to finally obtain the signal-to-error ratio 101Og1 {p0/pA) < where P is the power of the original signal yQ [n] . We have carried-out the discussed power computations in the frequency domain. We find a signal-to- error ratio of approximately 45 dB. Computing the signal-to-error ratio with respect to an ideal reference signal means that we assume an ideal output signal from the DSPACE analog output . Since the DSPACE digital-to-analog converter has 14 bits resolu¬ tion, the output signal is not an ideal sinusoid. The error due to this non-ideality is, by the present experiment, attributed to our ΣΔ converter. Furthermore, non-idealities of the current source in our test environment likewise introduce errors that are attributed to our ΣΔ converter. To attribute all the errors due to the test environment to the device under test is incor¬ rect. Therefore, the obtained results are worst-case-results for our ΣΔ converter. First guesses indicate that our test environ¬ ment adds about 6 dB to the signal-to-error ratio, leading to the conclusion that the obtained measurements correspond to a reso¬ lution of the expected 8 bits. The described experiment has been repeated for various input signal frequencies f . , yielding re¬ sults of comparable performance.

Fig. 8 shows a test input signal y [n] (dashed) and demodulated output signal y[n] (solid) for a sinusoidal frequency with a sine2 decoding filter of length L=2-256, and ΣΔ modulator parameter p=0.9922.

We have proposed a novel architecture for a first-order ΣΔ modu¬ lator that needs no active analog components. We have shown here that for Dc and sinusoidal input signals our approach achieves resolutions of more than 8bits. We have obtained our measurement results on a versatile test environment for oversampling con¬ verters. With the presented "digital-only" ΣΔ modulator we im¬ plement AD converters in FPGA' s and in the software of micro¬ processors: We have realized our novel "digital-only" ΣΔ modula¬ tor in AD converters used in a prototype of an e-commerce prod¬ uct. This application involves an optical data-channel with four photo-diode receivers. Four oversampling AD converters based on our new "digital-only" ΣΔ modulator run concurrently on one ARM7TDMI microprocessor. Each AD converter has a resolution of 7 bits and a Nyquist rate of IkHz.

Fig. 3 shows an alternative embodiment of the modulator accord¬ ing to the invention. Same features have received same numerals. The node 14 is connected to an input 21 of a standard microproc¬ essor 20, having an output 27, connected to the resistor 18 as in Fig. 2. This enables the software implementation of the quan¬ tization and sample-and-hold process as well as generating the inverted output signal with software instructions within the mi¬ cro processor 20.

Fig. 4 shows a schematic of a ΣΔ converter according to the in¬ vention, comprising a sigma-delta modulator as shown in Fig. 2 or 3 and digital filters and downsamplers . This enables the con¬ version of an input signal, e.g. from a photo-diode or another current source, to a digital output signal, using only digital components and no active analog components.

Fig. 9 shows a third embodiment of the modulator according to the invention. Same features have received same numerals. The node 14 is connected to an input current id . It has been found that an additional current source iΛ might model th analog noise in the circuit but it can also describe an artificial current source to inject an additional dither current. Fig. 10 shows an alternative embodiment of the modulator according to Fig. 9, wherein a digital dither generator 30 is used in connection with a network module 31, connected to node 14. The inverting input of the dither generator 30 is connected with the oversampling frequency f .

Formula 4 changes to: «[n + l]= p u[n] + g(x[n + \]+ w[n + \]-sgn(u[n])) (Formula ( 6 ) ) , where w[ ] is the discrete time equivalent of the dither current id . In the situation that the dither vv[ ] is a white Gaussian

noise sequence with zero mean and variance σ2 =0.01. Using for¬ mula 6 , it can be seen that in the vicinity of input DC values zero, the initial Devils' s staircase is no longer existing. The blindness of the Devils' s staircase for he interval around zero is remeded.

The dither current source can be realized digitally and com¬ prises a digital dither generator 30 having a clock input termi¬ nal 32 connected to the clock terminal f0 of the D-flip-flop 10, and a binary output vector 33 having a with of at least 1 bit. Furthermore there is a passive feedback network 31 with binary input vector 33 and one analog output 34 connecting the binary output vector 33 of the digital dither generator 30 with the current input terminal via the node 14.

According to another embodiment, not shown in the drawings, the clock input terminal of the digital dither generator may not be connected to the clock terminal of the D-flip-flop, but run syn¬ chronously or asynchronously, especially at a higher frequency.

The digital dither generator 30 can be a digital pseudo-random generator or a sine generator with appropriate amplitude and frequency.

As shown in Fig. 11 the passive feedback network 31 can be real¬ ized by one to more resistors 35, whereas one terminal of each resistor is connected to the analog output 34 of the network 31, and the other terminals of the resistors being the binary input vector 33 of the network 31. The D-flip-flop and the digital dither source can be provided with programmable logic devices such as FPGA/CPLD (field pro¬ grammable gate array / cellular programmable logic device) , and the current input signal can be directly connected to an input port of said programmable logic device and connected via the re¬ sistor element and a network to output ports of said programma¬ ble logic device.

Furthermore the D-flip-flop and the digital dither source can be provided with a microprocessor and the current input signal is then directly connected to an input port of said microprocessor and is connected via the resistor element and a network to out¬ put ports of said microprocessor.

The embodiment according to Fig. 9 or 10 can lead to an oversam- pling A/D converter using a lossy ΣΔ modulator with dither that has no longer the resolution restrictions of the usual lossy ΣΔ modulators. Two performance characterizations are investigated: First, upon consideration of DC input signals only, in princi¬ ple, any desired resolution might be obtained if the accumula¬ tion length is only sufficiently large; in this respect, the lossy ΣΔ modulator with dither behaves similarily to a non-lossy ΣΔ modulator. Second, a setup of a more practical oversampling A/D converter is considered, no longer having an unpractically large accumulation length and show its performance when convert¬ ing sinusoidal input signals.

The A/D converters are realized by using the lossy ΣΔ modulator with dither followed by some decoder, the usual structure of oversampling A/D converters. The decoder can consist of a simple linear filter followed by a static post-warping table lookup. Such a post-warping characteristic can be generated by the fol¬ lowing experiments: For DC input values to the lossy ΣΔ modula¬ tor with dither swept from -1 to 1 in steps of width 1/210, 106 modulator output bits have been accumulated for each DC input value to generate one DC input/output characteristic. 3119 such input/output characteristics have been generated and as post- warping characteristic the mean of them has been taken. This post-warping characteristic was used in connection with the em¬ bodiment shown in Fig. 12.

For characterizing the potential of the lossy ΣΔ modulator with dither when converting DC input signals, a simple averaging de¬ coder is used as linear filter, followed by post-warping, with very large accumulation length. This is done to experimentally verify the hypotheses that the lossy ΣΔ modulator with dither can in the limit of infinite accumulation length obtain the per¬ formance of an ideal (non-lossy) ΣΔ modulator with its infinitly high resolution. Upon analysis of the complete DC characteristic when averaging over 10 ΣΔ modulator output bits, the quantiza¬ tion of the obtained characteristic to 5 bits was compared to an ideal 5-bit quantizer. Because the underlying ΣΔ modulator (6) uses a feedback gain p = 0.8667, good for at most 4 bits in the non-dither case, the results show an increase in resolution of at least 1 bit.

Fig. 12 shows a practical setup using the oversampling A/D con¬ verter structure, wherein the decoder is realized as the cascade of two 512-point moving average filters followed by the static post-warping as explained above. The bit stream of the modulator 40 is filtered by a sine2 filter 41, being a cascade of two 512- point moving averagers, whose output is post-warped in a warping unit 42.

To prove that the performance of lossy ΣΔ modulators is improved by dither injection, the very low-resolution modulator with feedback gain p = 0.8667 is used. A sinusoidal input signal is fed to the A/D converter and the ΣΔ modulator is run at a fre¬ quency of 100 MHz. This leads to a corresponding distorted out¬ put signal. To obtain a signal-to-distortion ratio characteriza¬ tion, the error signal (in-put signal minus output signal) is computed, the error-signal energy determined, and the input- signal energy to this error-signal energy related (excluding the initial transient portions of the signals from the computation) .

It has been found that the lossy ΣΔ modulator with-out dither merely obtains a signal-to-distortion ratio of less than about 18 dB, corresponding to less than about 3 bits, (1 bit corre¬ sponding to approximately 6 dB) , that the lossy ΣΔ modulator without dither but with post-warping achieves more than 25 dB hence about 4 bits as suggested by the p = 0.8667 feedback gain, and that the lossy ΣΔ modulator with dither achieves, for not too high frequencies, more than 38 dB corresponding to about 6 bits. This shows that even with very simple structures, 2 bits are gained while dithering.

For the proposed architecture of a first-order ΣΔ modulator that needs no active analog components, dither-signal injection can overcome the inherent resolution limitations of lossy ΣΔ modula¬ tors and improve the results. Although the embodiments according to the above description just reported on experiments using white Gaussian noise as dither signal, additional experiments indicate that other dither signals such as binary random dither or even deterministic high-frequency sinusoidal dither work as well. Furthermore, results for a loss g = l - p = l - 0.8667 were presented that achieves without dither only a 4 bits DC resolution. This parameter had been selected to obtain more il¬ lustrative graphical presentations; obviously, corresponding re¬ sults are obtained for lower loss values leading to initially higher DC resolutions, but one discovery is that there is a principal distinction between a lossy ΣΔ modulator on one hand, and a lossy ΣΔ modulator with dither injection on the other hand in that the former has an inherently limited resolution, whereas the later seems to have no such resolution limitation and is in this respect similar to an ideal ΣΔ modulator.

More generally concerning practical integrated circuit implemen¬ tations of EA modulators, integrator leakage due to finite op- amp gain is inevitable and leads to lossy ΣΔ modulators and the accompanying inherent resolution limitation. In integrated cir¬ cuit implementations noise is inevitable as well, and that such noise might already have a positive dithering effect, possibly re-moving the resolution limitation or at least improving the resolution. With "digital-only" ΣΔ modulators, A/0 converters are implemented in FGPA' s and in the software of microproces¬ sors, e.g. in a price-sensitive e-commerce product. These appli¬ cations involve optical data-channels with photo-diode receivers and over-sampling A/D converters based on "digital-only" ΣΔ modulators running concurrently on ARM microprocessors.