RFSTREAM AMERICA INC (US)
KAMATA TAKATSUGU (JP)
US6911861B2 | 2005-06-28 | |||
US7224210B2 | 2007-05-29 | |||
US6407622B1 | 2002-06-18 |
CLAIMS
What is claimed is:
1. A current source circuit comprising:
biasing circuit comprising a plurality of metal oxide semiconductor (MOS)
transistors for generating a biasing current; and load circuit comprising at least one MOS device for receiving the biasing current and generating a MOS current through the MOS device,
wherein a change in the biasing current due to temperature or process variations is
approximately offset by a change in the MOS current due to the temperature or process
variations.
2. The current source circuit of claim 1, wherein: temperature or process variations cause an increase in the biasing current and an
increase in the resistance of the MOS device, whereby the increase in the resistance of the
MOS device causes a decrease in the MOS current which approximately offsets the increase in the biasing current.
3. The current source circuit of claim 1 , wherein:
temperature or process variations cause a decrease in the biasing current and a
decrease in the resistance of the MOS device, whereby the decrease in the resistance of the MOS device causes an increase in the MOS current which approximately offsets the decrease in the biasing current.
4. The current source circuit of claim 1, wherein: the load circuit further comprises a resistor, the load circuit receiving the biasing
current and generating a resistor current through the resistor; and a change in the resistor current due to temperature or process variations is
approximately offset by a change in the MOS current due to the temperature or process
variations to produce an approximately constant current sum across temperature and process variations.
5. The current source circuit of claim 4, further comprising:
current mirror circuit, coupled to the biasing circuit, for generating an output
current equal to the sum of the resistor current and the MOS current, the output current being approximately constant across temperature or process variations.
6. The current source circuit of claim 1, wherein the biasing circuit generates the biasing
current based on transconductance of the MOS transistors of the biasing circuit.
7. The current source circuit of claim 6, wherein the biasing circuit comprises:
first transistor pair for generating a first transconductance between a reference
voltage and the load circuit; and
second transistor pair for generating a second transconductance between the reference voltage and ground.
8. The current source circuit of claim 7, wherein the first transistor pair comprises a size four times as large as the second transistor pair.
9. The current source circuit of claim 1, wherein the biasing circuit comprises: first and third transistors, wherein a gate of the third transistor is coupled to a drain of the third transistor, a source of the third transistor is coupled to a gate of the first
transistor, and a source of the first transistor is coupled to the load circuit; and
second and fourth transistors, wherein a drain of the second transistor is coupled to
the source of the third transistor, a source of the second transistor is coupled to ground, a gate of the second transistor is coupled to a source of the fourth transistor and to the drain of the first transistor, and the gate of the third transistor is coupled to the gate of the fourth
transistor,
wherein the gate to source voltage of the third transistor (V GS3 ) plus the gate to source voltage of the first transistor (V GSI ) plus the voltage across the resistor (I r *R) of the load circuit is equal to the gate to source voltage of the fourth transistor (V GS4 ) plus the
gate to source voltage of the second transistor (V GS2 ), as represented by the equation:
10. A current source circuit comprising: means for generating a biasing current;
means for receiving the biasing current and generating a current through a metal
oxide semiconductor (MOS) device (MOS current),
wherein a change in the biasing current due to temperature or process variations is approximately offset by a change in the MOS current due to the temperature or process variations.
11. The current source circuit of claim 10, wherein:
temperature or process variations cause an increase in the biasing current and an increase in the resistance of the MOS device, whereby the increase in the resistance of the MOS device causes a decrease in the MOS current which approximately offsets the increase in the biasing current.
12. The current source circuit of claim 10, wherein:
temperature or process variations cause a decrease in the biasing current and a decrease in the resistance of the MOS device, whereby the decrease in the resistance of
the MOS device causes an increase in the MOS current which approximately offsets the
decrease in the biasing current
13. The current source circuit of claim 10, wherein the means for receiving the biasing current further comprises:
means for generating a resistor current through a resistor, wherein a change in the
resistor current due to temperature or process variations is approximately offset by a change in the MOS current due to the temperature or process variations to produce an approximately constant current sum across temperature and process variations.
14. The current source circuit of claim 13, further comprising:
means for generating an output current equal to the sum of the resistor current and
the MOS current, the output current being approximately constant across temperature or process variations.
15. The current source circuit of claim 10, wherein the means for generating the biasing
current comprises a means for generating the biasing current based on transconductance of one or more MOS transistors. 16. A method for generating a current, the method comprising:
generating a biasing current;
receiving the biasing current and generating a current through a metal oxide
semiconductor (MOS) device (MOS current),
wherein a change in the biasing current due to temperature or process variations is approximately offset by a change in the MOS current due to the temperature or process
variations.
17. The method of claim 16, wherein: temperature or process variations cause an increase in the biasing current and an increase in the resistance of the MOS device, whereby the increase in the resistance of the
MOS device causes a decrease in the MOS current which approximately offsets the
increase in the biasing current.
18. The method of claim 16, wherein:
temperature or process variations cause a decrease in the biasing current and a
decrease in the resistance of the MOS device, whereby the decrease in the resistance of
the MOS device causes an increase in the MOS current which approximately offsets the
decrease in the biasing current.
19. The method of claim 16, further comprising:
generating a resistor current through a resistor, wherein a change in the resistor
current due to temperature or process variations is approximately offset by a change in the MOS current due to the temperature or process variations to produce an approximately
constant current sum across temperature and process variations; and generating an output current equal to the sum of the resistor current and the MOS
current, the output current being approximately constant across temperature or process
variations.
20. The method of claim 16, wherein generating the biasing current comprises generating
the biasing current based on transconductance of one or more MOS transistors. |
A MOSFET TEMPERATURE COMPENSATION CURRENT
SOURCE
CROSS-REFERENCES TO RELATED APPLICATIONS
This application claims the benefit of U.S. Provisional Patent Application No.
60/660,728, filed March 11, 2005, entitled "A MOSFET Temperature Compensation Current Source."
FIELD OF THE INVENTION
The present invention is directed towards the field of temperature compensation
current sources.
BACKGROUND OF THE INVENTION
Current sources are components commonly used in metal oxide semiconductor
field effect transistors (MOSFETs). These current sources can be sensitive to temperature or process variations and produce an unstable and variable output current across a range of temperatures and process variations. Typically, current sources are designed to provide
a constant current across temperature or process variations using junction diodes. Figure
1 shows a conventional current source 100 implementing a junction diode 105 to achieve
band gap voltage under full complementary metal oxide semiconductor (CMOS) processes. Under CMOS processes, however, junction diodes require large areas on a circuit.
Therefore, there is a need for a constant current source that does not vary
significantly with temperature or process variations that requires less area on a circuit.
SUMMARY OF THE INVENTION
Some embodiments provide a current source that generates a constant current
using metal oxide semiconductor (MOS) transistors. A biasing circuit generates a biasing
current based on the transconductance of the MOS transistors. A load circuit generates a
load current from the biasing current. In one embodiment, the load circuit comprises a resistor coupled in parallel with a MOS device (e.g., MOS transistor) having a resistance
(R MOS ). The load current comprises the sum of a resistor current, which flows through the
resistor, and a MOS current that flows through the MOS device.
The biasing current generated by the biasing circuit is constant except under temperature or process variations which may cause the biasing current to increase or decrease (due to the effect of temperature or process variations upon the transconductance
of the MOS transistors). An increase or decrease in the biasing current (caused by
temperature or process variations) produces an increase or decrease, respectively, in the
resistor current that flows through the resistor of the load circuit. Temperature or process
variations, however, also have an effect on the resistance value (R MOS ) of the MOS device of the load circuit and cause the resistance value R MOS to increase or decrease. The
changes in the resistance value R MOS also causes a change in the MOS current that flows
through the MOS device, whereby the change in MOS current offsets the change in the
resistor current to produce a relatively constant load current.
For example, if temperature or process variations cause the biasing current to increase, the resistor current through the resistor of the load circuit increases. These
temperature or process variations, however, also cause the resistance R MOS of the MOS device of the load circuit to increase, thereby causing the MOS current through the MOS
device to decrease. Therefore, the decrease in the MOS current approximately offsets the increase in the resistor current to produce a relatively constant load current of the load
circuit. Likewise, if temperature or process variations cause the biasing current to decrease, the resistor current through the resistor of the load circuit decreases. These
temperature or process variations, however, also cause the resistance RM O S of the MOS
device of the load circuit to decrease, thereby causing the MOS current through the MOS
device to increase. Therefore, the increase in the MOS current approximately offsets the
decrease in the resistor current to produce a relatively constant load current of the load circuit. As such, the changes in the biasing current due to temperature or process
variations is, in effect, approximately offset by a change in the MOS current (of the MOS
device of the load circuit) due to the same temperature or process variations. Thus, the load current is relatively constant because variations of the biasing current and the resistor current are offset by variations of the MOS current across
temperature or process variations. An output current of the current source is also equal to
a sum of the resistor current and the MOS current. In one embodiment, the output current is output from a current mirror circuit that mirrors the load current as the output current.
In some embodiments, the current source produces a stable output current (I out ) that does not vary significantly across temperatures and process variations, the current source being
implemented without use of a junction diode.
In one embodiment, the biasing circuit comprises first and second transistor pairs.
The first transistor pair generates a first transconductance between a reference voltage and the load circuit, and the second transistor pair generates a second transconductance
between the reference voltage and ground. For this embodiment, the first transistor pair
comprises a size greater than the second transistor pair (e.g., four times the size)
BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a conventional current source implementing a junction diode.
Figure 2 is a block diagram illustrating a constant current source of some
embodiments.
Figure 3 is a block diagram illustrating detail of a constant current source of some
embodiments.
Figure 4 is a flowchart showing a method for generating a constant current using metal oxide semiconductor (MOS) transistors.
Figure 5 is a circuit analysis diagram of a non-constant current source.
Figure 6 is a circuit analysis diagram of the constant current source of Figure 3.
Figure 7 is a graph that shows the output currents of a constant current source and
a non-constant current source as a function of the transconductance parameter KP.
DETAILED DESCRIPTION
The disclosure of U.S. Provisional Patent Application No. 60/660,728, filed March 11, 2005, entitled "A MOSFET Temperature Compensation Current Source," is hereby expressly incorporated herein by reference.
Although the present invention is described below in terms of specific exemplary
embodiments, one skilled in the art will realize that various modifications and alterations may be made to the below embodiments without departing from the spirit and scope of
the invention. In the discussion below, Section I describes a constant current source and a
method for generating a constant current. Section II describes characteristics of a non-
constant current source and a constant current source. And Section IH discusses output currents of current sources as a function of the transconductance parameter.
I. Constant Current Source
Figure 2 is a block diagram illustrating a constant current source 200 of some
embodiments. The constant current source 200 comprises a biasing circuit 205, a load
circuit 210, and a current mirror circuit 215. The biasing circuit 205 comprises a plurality
of metal oxide semiconductor (MOS) transistors for generating a biasing current based on transconductance of the MOS transistors.
The load circuit 210 is coupled to the biasing circuit 205 and comprises at least
one resistor and at least one MOS device coupled in parallel with the at least one resistor.
As described below, the MOS device of the load circuit 210 is a MOS transistor. In other
embodiments, however, the MOS device is any other type of metal oxide semiconductor device. The load circuit 210 receives the biasing current from the biasing circuit 205 and
generates a constant load current from the biasing current. In particular, the load circuit
210 generates a resistor current (I r ) that flows through the resistor and a MOS current (I t )
that flows through the MOS transistor, the load current being the sum of a resistor current
and the MOS current. The load current is relatively constant because variations of the resistor current are offset by variations of the MOS current across temperature or process variations (i.e., the resistor and MOS currents balance each other to produce a constant
load current).
The current mirror circuit 215 is coupled to the biasing circuit 205 and generates
an output current (I 0Ut ) equal to a sum of the resistor current (I r ) and the MOS current (I t ). The current mirror circuit 215 mirrors the load current of the load circuit 210 as the output
current (I out ). In some embodiments, the current source 200 produces a stable output
current (I out ) that does not vary significantly across temperatures and process variations, the current source being implemented without use of a junction diode.
If the current source 200 is to produce a constant output current of value A, the
first current has a value of B, and the second current has a value of C, then A = B + C. If
the first current changes in value, the second current balances the first current so that the
output current is still approximately equal to A. For example, if temperature or processing
variations cause the first current to increase in value to equal (B + delta), the value of the
second current would thereby decrease in value to approximately equal (C - delta) so that the sum of the first and second currents is still approximately equal to A. Conversely, if
temperature or processing variations cause the first current to decrease in value to equal
(B - delta), the value of the second current would thereby increase in value to
approximately equal (C + delta) so that the sum of the first and second currents is still approximately equal to A.
Figure 3 is a block diagram illustrating detail of a constant current source 300 of
some embodiments. The constant current source 200 comprises a biasing circuit 205, a
load circuit 210, and a current mirror circuit 215.
The biasing circuit 205 comprises a plurality of metal oxide semiconductor (MOS)
transistors Q1 (305), Q2 (310), Q3 (315), and Q4 (320). As shown in Figure 3, a gate of the transistor Q3 is coupled to a drain of transistor Q3, a source of transistor Q3 is
coupled to a gate of transistor Q1, and a source of transistor Q1 is coupled to the load
circuit, a drain of transistor Q2 is coupled to the source of transistor Q3, a source of transistor Q2 is coupled to ground, a gate of the transistor Q2 is coupled to a source of
transistor Q4 and to the drain of transistor Q1, and the gate of the transistor Q3 is coupled to the gate of transistor Q4.
The biasing circuit 205 receives a starting current (I sta ) and generates a regulated biasing current based on transconductance of the MOS transistors Q1 (305), Q2 (310), Q3
(315), and Q4 (320). In particular, the biasing circuit 205 comprises a first transistor pair Q1 (305) and Q3 (315) and a second transistor pair Q2 (310) and Q4 (320). The first
transistor pair Q1 (305) and Q3 (315) generates a first transconductance between a
reference voltage and the load circuit 210. The second transistor pair Q2 (310) and Q4
(320) generates a second transconductance between the reference voltage and ground.
The load circuit 210 is coupled to the biasing circuit 205 and comprises a resistor 325 coupled in parallel with a MOS transistor Q8 (330). The load circuit 210 receives the
biasing current from the biasing circuit 205 and generates a constant load current from the
biasing current. The load circuit 210 generates a resistor current (I r ) through the resistor
325 and a MOS current (I t ) through the MOS transistor 330, whereby load current equals
resistor current (I r ) + MOS current (I t ).
The biasing current generated by the biasing circuit 205 is constant except under
temperature or process variations which may cause the biasing current to increase or
decrease (due to the effect of temperature or process variations upon the transconductance
of the MOS transistors Q1 to Q4 of the biasing circuit 205). An increase or decrease in the biasing current (caused by temperature or process variations) produces an increase or decrease, respectively, in the resistor current (I r ) through the resistor 325 of the load
circuit 210. Temperature or process variations, however, also have an effect on the
resistance value (R MOS ) of the MOS device 330 of the load circuit 210 and cause the
resistance value R MOS to increase or decrease. The changes in the resistance value R MOS also causes a change in the MOS current (I t ) that flows through the MOS device 330, whereby the change in MOS current (I t ) offsets the change in the resistor current (I r ) to
produce a relatively constant load current.
For example, if temperature or process variations cause the biasing current to
increase, the resistor current (I r ) through the resistor 325 of the load circuit 210 increases. These temperature or process variations, however, also cause the resistance R MOS of the
MOS device 330 of the load circuit 210 to increase, thereby causing the MOS current (I t )
through the MOS device 330 to decrease. Therefore, the decrease in the MOS current (I t )
offsets the increase in the resistor current (I r ) to produce a relatively constant load current
of the load circuit 210. Likewise, if temperature or process variations cause the biasing current to decrease, the resistor current (I r ) through the resistor 325 of the load circuit decreases. These temperature or process variations, however, also cause the resistance
R MOS of the MOS device 330 of the load circuit to decrease, thereby causing the MOS
current (It) through the MOS device to increase. Therefore, the increase in the MOS
current (I t ) offsets the decrease in the resistor current (I r ) to produce a relatively constant load current of the load circuit. As such, the changes in the biasing current due to
temperature or process variations is, in effect, approximately offset by a change in the
MOS current (of the MOS device of the load circuit) due to the same temperature or
process variations. Thus, the load current is relatively constant because variations of the
biasing current and resistor current (I r ) are offset by variations of the MOS current (I t ) across temperature or process variations.
As shown in Figure 3, the voltage drop through transistors Q1 and Q3 and the
resistor 325 is equal to the voltage drop through transistors Q2 and Q4. This can be shown
by the following observations:
• the voltage at the gate of transistor Q3 is equal to the voltage at the gate of
transistor Q4 (indicated by point V in Figure 3);
• the gate to source voltage of Q3 (V GS3 ) plus the gate to source voltage of Q1
(V GS1 ) plus the voltage across the resistor 325 (I r *R) is equal to the gate to
source voltage of Q4 (V GS4 ) plus the gate to source voltage of Q2 (V GS2 ) SO that:
• the drain to source voltage of Q8 (V DSS ) is equal to the voltage across the resistor 325 (I r *R) so that:
As such, in some embodiments, the first transistor pair Q1 (305) and Q3 (315)
comprises transistors that are larger in size than the transistors of the second transistor pair Q2 (310) and Q4 (320) to accommodate the additional voltage drop (I T *R) across the
resistor 325 (which lies in the voltage drop path of transistors Q1 and Q3). In one
embodiment, the size of transistors Q1 and Q3 are four times the size of transistors Q2 and Q4.
The current mirror circuit 215 is coupled to the biasing circuit 205 and comprises
a plurality of MOS transistors Q5 (335), Q6 (340), and Q7 (345). As shown in Figure 3,
transistor Q5 is coupled to transistor Q3 and mirrors current flowing through transistors
Q3 and Q2; transistor Q6 is coupled to transistors Q5 and Q4 and mirrors current flowing through transistors Q4 and Q1; and transistor Q7 is coupled to transistor Q6 and mirrors current flowing through transistor Q6 and sources the output current. The current mirror
circuit 215 further comprises a resistor that couples the source of transistor Q7 to ground.
The current mirror circuit 215 mirrors the load current of the load circuit 210 to generate
an output current (I out )- The generated output current (I out ) is equal to a sum of the resistor current (I r ) across the resistor 325 and the MOS current (I t ) across transistor Q8 (330) of
the load circuit 210 so that:
using metal oxide semiconductor (MOS) transistors. The method 400 begins by generating (at 405) a biasing current (e.g., using a biasing circuit comprising a plurality of MOS transistors), the biasing current being generated based on a transconductance of at
least one MOS transistor. For example, the method may generate the biasing current by
generating a first transconductance between a reference voltage and a load circuit and
generating a second transconductance between the reference voltage and ground.
The method then generates (at 410) a constant load current from the biasing
current (e.g., using a load circuit comprising a resistor and a MOS transistor in parallel),
the load current comprising a resistor current and a MOS current, wherein variations of
the resistor current are offset by variations of the MOS current across temperature or process variations. The method then generates (at 415) an output current equal to a sum of
the resistor current and the MOS current, the output current being approximately constant
in value across temperature or process variations.
II. Current Source Characteristics
Characteristics of the constant current source can be better understood by first examining the characteristics of a non-constant current source that produces an output
current that varies significantly across temperature or processing variations. As known in the art, a transconductance parameter (KP) of a current source has a high correlation to
temperature or processing variations and varies significantly along with temperature or processing variations. As such, the transconductance parameter of a current source is typically used to correlate variations in the output current of the current source to
variations in temperature or processing. Thus, a current source that produces significant
variations in its output current as the transconductance parameter of the current source
varies is also considered to produce significant variations in its output current with
temperature or processing variations (as discussed further below in relation to Figure 7).
Such a current source is sometimes referred to as a KP dependent current source.
Figure 5 is a circuit analysis diagram of a KP dependent current source 500 that
does not produce a constant current across temperature or processing variations. Note that
in comparison with the constant current source 300 of Figure 3, the KP dependent current
source 500 does not have a MOS device connected in parallel with resistor R so that there
is no offsetting MOS current. Thus the output current (I out ) of the KP dependent current source 500 is equal to the current (I) across the resistor R. As discussed below in relation
to Figure 7, the current (I) across the resistor R varies significantly across temperature or
processing variations.
To determine temperature compensation (TC) as a function of output current (J D )
for the KP dependent current source 500 of Figure 5:
Given:
k = gain of current source circuit;
W = width of gate channel;
L - length of gate channel;
N = transistor size multiplication factor between Q1 and Q2 and between Q4 and Q3 (e.g., if Q1 and Q4 are four times larger than Q2 and Q3 , N = 4);
KP = transconductance parameter (AJV 2 );
I D = drain current;
V TH - threshold voltage;
V GS = gate-source voltage;
V DS = drain-source voltage; and
T= temperature,
then:
As such, temperature compensation (TC) as a function of output current (I D ) can
be represented by the equation:
α = the temperature compensation value at resistor R.
To determine the value of the output current (I D ):
where:
then:
For example:
Other characteristics of the MOSFET KP dependent current source 500 of Figure 5 are
shown by the following equations:
US2006/008633
thus:
Figure 6 is a circuit analysis diagram of the constant current source 300 of Figure
3. Characteristics of the constant current source 300 are shown by the following
equations:
Given:
then:
when (/ r = I t ) :
III. Output Current as a Function of the Transconduεtance Parameter KP
As discussed above, the transconductance parameter KP of a current source varies
significantly with temperature or processing variations and can be used to correlate the
output current of the current source to variations in temperature or processing. A current
source that produces significant variations in its output current as the transconductance parameter KP of the current source varies is also considered to produce significant
variations in its output current with temperature or processing variations.
Figure 7 is a graph that shows the output currents of a constant current source and a non-constant current source as a function of the transconductance parameter KP of the current sources across a range of KP values from a lower boundary to an upper boundary
(assuming that temperature or process variations of KP are +/- 30%). A first graph line
705 shows the output current of a non-constant current source as a function of the transconductance parameter KP of the current source. In particular, the first graph line 705
shows the output current of the KP dependent current source 500 of Figure 5 where the
output current is equal to the current (I r ) across the resistor R. As shown in Figure 7, the
output current of the KP dependent current source 500 varies significantly across the
various values of KP. This indicates that the output current of the KP dependent current
source 500 would also vary significantly across temperature or process variations.
A second graph line 710 shows the output current of the constant current source
300 of Figure 3 as a function of the transconductance parameter KP of the current source,
whereby the output current is equal to a resistor current (I r ) across a resistor R and a MOS
current (I t ) across a transistor. As shown in Figure 7, the output current of the constant
current source 300 is relatively constant within various values of KP that reflect typical operating conditions (indicated by the dashed lines). This indicates that the output current
of the constant current source 300 would also be relatively constant across temperature or
process variations. This is due to the fact that as the value of the resistor current (I r ) varies
over various values of KP, the values of the MOS current (I t ) varies to offset the
variations of the resistor current (I r ) to maintain a relatively constant output current (I out )-
One of ordinary skill will recognize that the invention can be embodied in other specific forms without departing from the spirit of the invention, even though the
invention has been described with reference to numerous specific details. In view of the
foregoing, one of ordinary skill in the art would understand that the invention is not to be
limited by the foregoing illustrative details, but rather is to be defined by the appended
claims.