Title:
MULTI-ADDEND ADDITION CIRCUIT FOR STOCHASTIC CALCULUS
Document Type and Number:
WIPO Patent Application WO/2019/174263
Kind Code:
A1
Abstract:
A multi-addend addition circuit for a multi-addend addition of polarized indication in stochastic calculus relates to the field of digital circuits. The multi-addend addition circuit comprises: a buffer circuit, and a calculation circuit. The buffer circuit is used for storing data to be buffered for at least one cycle and outputting same. The calculation circuit is used for processing multiple bit stream data and buffered data and outputting one bit stream data and the data to be buffered, wherein the output bit stream data is the value of a quotient obtained by dividing the sum of summed data and the buffered data by a coefficient of diminution, and wherein the output data to be buffered is a remainder obtained by diving the sum of all summed data by the end of the current cycle by the coefficient of diminution, the summed data being the number of bit streams having a value of 1 in multiple first bit stream data. Calculation results of each cycle are in part saved by means of the buffer circuit, thus improving the calculation accuracy of the multi-addend addition circuit.
Inventors:
ZHANG JIAN (CN)
TANG YANGYANG (CN)
TANG YANGYANG (CN)
Application Number:
PCT/CN2018/113353
Publication Date:
September 19, 2019
Filing Date:
November 01, 2018
Export Citation:
Assignee:
HUAWEI TECH CO LTD (CN)
International Classes:
G06F7/50
Foreign References:
| CN105512724A | 2016-04-20 | |||
| CN205959185U | 2017-02-15 | |||
| CN105027076A | 2015-11-04 | |||
| CN105718240A | 2016-06-29 | |||
| US9496875B1 | 2016-11-15 |
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