A Multi-bit Sigma-Delta Modulator with reduced number of bits in feedback path

FIELD OF THE INVENTION

This invention relates to sigma-delta modulators, to digital-to-analogue converters having a sigma-delta modulator, and to methods of converting a signal.

BACKGROUND OF THE INVENTION Sigma-delta (σδ) modulators are employed in analogue-to-digital converters

(ADCs). US6404368 discloses in Figure 3 and its accompanying text a σδ modulator to be used in an over-sampling type ADC, which includes an analogue σδ modulator coupled to a digital σδ modulator. The analogue σδ modulator includes a digital-to-analogue converter (DAC) which converts a one-bit feed-back signal to an analogue signal, an analogue adder or subtractor which calculates a difference between an output signal transmitted from the DAC and an analogue input signal. The analogue σδ modulator also has an analogue integrator, which integrates output signals transmitted from the analogue adder or subtractor, and a first quantizer which converts an output signal transmitted from the analogue integrator, into a digital signal. The digital σδ modulator includes a digital adder or subtractor which calculates a difference between an output signal transmitted from the first quantizer and the one-bit feed-back signal, a digital integrator which integrates output signals transmitted from the digital adder or subtractor, a second quantizer which converts an output signal transmitted from the digital integrator into a one-bit digital signal, and a delay element which delays the one-bit digital signal transmitted from the second quantizer and feeds the thus delayed signal back as the one-bit feed-back signal. Since the feedback signal transmitted to the analogue modulator is a one-bit signal, distortion caused by non-linearity error of the DAC can be reduced.

DISCLOSURE OF INVENTION According to a first aspect of the invention there is provided a sigma-delta modulator comprising: a summing stage for generating an error signal as the difference between an input signal and a feedback signal;

a loop filter coupled to an output of the summing stage for filtering the error signal; a multi-bit quantizer coupled to an output of the loop filter for quantizing the filtered error signal; - a digital filter coupled to an output of the multi-bit quantizer; and a feedback path coupling an output of the digital filter to the summing stage for providing the feedback signal to the summing stage, wherein the feedback signal has fewer bits than a number of bits produced by the multi-bit quantizer and there is no other feedback path coupling the output of the digital filter to an input of the digital filter. The use of a multi-bit quantizer helps reduce quantization noise and the feedback having fewer bits helps reduce non-linearity errors, which can arise in the feedback path.

The σδ modulator of the prior art mentioned above has separate feedback loops for the analogue σδ modulator and for the digital σδ modulator. In contrast, the invention has no feedback path coupling the output of the digital filter to an input of the digital filter other than the feedback path coupling the output of the digital filter to the summing stage. In other words, the σδ modulator of the invention may have only a single feedback path, that feedback path being the feedback path coupling the output of the digital filter to the summing stage. This means that there is less or no need for a multiple loop stability analysis. It can therefore be easier to design or adjust the loop filter for stable operation of the σδ modulator, whether the loop filter is arranged as a first order filter or as a higher order filter.

Any features may be added, to create different embodiments of the invention, and some embodiments will be described below. According to a second aspect of the invention there is provided a sigma-delta modulator comprising: a summing stage for generating an error signal as the difference between an input signal and a feedback signal; a loop filter coupled to an output of the summing stage for filtering the error signal; a multi-bit quantizer coupled to an output of the loop filter for quantizing the filtered error signal; a digital filter coupled to an output of the multi-bit quantizer;

a feedback path coupling an output of the digital filter to the summing stage for providing the feedback signal to the summing stage, the feedback signal having fewer bits than a number of bits produced by the multi-bit quantizer, and wherein the digital filter has an order greater than one in a passband of the sigma-delta modulator (200).

By providing, after the multi-bit quantizer, a digital filter having an order greater than one, the digital filter can have a gain difference between inside and outside of the passband of the σδ modulator sufficient to provide improved suppression of the quantization noise in the feedback signal. Also, the remaining quantization noise can be less correlated with the input signal. This means the remaining noise tends to be less concentrated in the frequencies predominating in the input signal, which means less distortion of the output at the frequencies of interest. This can be applied in a σδ modulator, or in any feedback type modulator where there is a big noise source which can be suppressed by providing gain in front of it. As in the first aspect, the use of a multi-bit quantizer helps reduce quantization noise. The feedback having fewer bits helps reduce non-linearity errors.

An additional feature of some embodiments is the frequency response of the digital filter having a substantially flat gain profile outside of the passband of the sigma-delta modulator (200). A notable consequence of the flat gain is that there will be little or no effect on the characteristics of the loop filter. This means that there is little or no need to alter a conventional loop filter to accommodate the digital filter and the feedback signal having fewer bits. This can enable an increase in performance with little or no burden of redesigning and optimizing the loop filter. This can otherwise be a considerable burden, for example in cases where there are multiple adjustments such as filter coefficients, and where it is time consuming to make adjustments without adding instability, or for other reasons.

Furthermore, in some cases, costs in redesign, manufacturing and retesting can be saved, or the design of the loop filter can be made simpler or more effective by providing the flat gain characteristic.

An additional feature of some embodiments is the difference in gain of the digital filter inside and outside of the passband of the sigma-delta modulator being greater than or equal to 201ogio((2 ^y -l)/(2 ^z -l)) dB, where y is the number of bits of the feedback signal and z is the number of bits of the multi-bit quantizer. This can provide improved suppression of quantization noise.

An additional feature of some embodiments is the frequency response of the combination of the loop filter and the digital filter having a first order roll-off of gain outside of the passband of the sigma-delta modulator. This can provide stability of the sigma-delta modulator loop. According to a third aspect of the invention there is provided a method of converting a signal comprising: generating an error signal as the difference between an input signal and a feedback signal; filtering the error signal; - quantizing the filtered error signal using a multi-bit quantizer; filtering the quantized and filtered error signal using a digital filter; and generating the feedback signal from an output signal of the digital filter; wherein the feedback signal has fewer bits than a number of bits produced by the multi-bit quantizer and there is no other feedback of the output signal of the digital filter to an input of the digital filter.

According to a fourth aspect of the invention there is provided a method of converting a signal comprising: generating an error signal as the difference between an input signal and a feedback signal; - filtering the error signal; quantizing the filtered error signal using a multi-bit quantizer; filtering the quantized and filtered error signal using a digital filter; generating the feedback signal from an output signal of the digital filter; wherein the feedback signal has fewer bits than a number of bits produced by the multi-bit quantizer; and wherein the digital filter has an order greater than one inside a passband of the sigma-delta modulator.

Any of the additional features can be combined together and combined with any of the aspects. Other advantages will be apparent to those skilled in the art, especially over other prior art. Numerous variations and modifications can be made without departing from the claims of the present invention. It should be noted that it is not intended to exclude from the signal-delta modulator according to the second aspect of the invention, and the method of converting a signal according to the fourth aspect of the invention, the possibility of feedback to the digital filter.

BRIEF DESCRIPTION OF THE DRAWINGS

How the present invention may be put into effect will now be described, by way of example only, with reference to the accompanying drawings, in which: Fig. 1 is a block diagram of a continuous-time σA modulator,

Fig. 2 is a block diagram of a continuous-time σδ modulator in which the quantizer is linearily modelled,

Fig. 3 is a block diagram of an example analogue loop filter, for use in the modulator of Figure 1, or in embodiments of the invention, Fig. 4 shows the loop filter transfer function (H), noise transfer function

(NTF), and signal transfer function (STF), for the modulator of Figure 1,

Fig. 5 shows a simulated frequency response of a 4 ^th order σδ modulator using the filter of Figure 3, with a full scale input signal,

Fig. 6 shows a 1-bit and a 5-bit modulator output signal, as alternatives for comparison,

Fig. 7 shows the output spectrum of a 4 ^th order 1-bit and a 4 ^th order 5-bit σδ modulator, as alternatives for comparison,

Fig. 8 shows a σδ modulator architecture according to an embodiment of the invention, Fig. 9 shows a linearised model of the σδ modulator architecture of Figure 8,

Fig. 10 shows graphs of example filter frequency response characteristics, for use in embodiments,

Fig. 11 shows another embodiment, showing a converter having a modulator and an additional digital filter, Fig. 12 shows the output spectra of a conventional modulator and of an embodiment of the invention, having a 5 ^th order 5-bit σδ modulator.

MODES FOR CARRYING OUT THE INVENTION

By way of introduction to the embodiments, the operation of a known σδ modulator such as can be used for an ADC will be discussed. An ADC using a σδ modulator (which will be termed a σδ ADC) can provide a performance benefit in terms of allowing a high dynamic range of signals to be received for a small amount of power consumption. The power advantage of using such an σδ ADC is only maximized if the digital filter following the σδ modulator can be implemented efficiently. The highly over sampled output of a σδ

modulator places extra processing burden into the digital domain resulting in increased power consumption. The analogue side of the ADC (a 1-bit ADC/DAC and filter) can be relatively simple. The digital side performs filtering and decimation and makes the ADC inexpensive to produce in practice. The principle of operation of the σδ modulator is well known. In summary, an input analogue information signal is fed to a feedback loop comprising a continuous-time analogue filter such as an integrator for noise shaping, followed by a quantizer which samples the signal and a feedback path using a DAC. The output signal of the σδ modulator is a stream of bits at a highly oversampled rate. The oversampled bitstream is optionally fed to subsequent digital processing which converts the bitstream to a lower rate representation of the information signal by decimation and digital filtering, to provide a stream of values with more bits, and a lower sample frequency. The oversampling frequency is set to kf _s , where f _s is the Nyquist sampling frequency and k is the oversampling ratio. The oversampling causes the noise floor to drop in the same bandwidth. The signal-to-noise ratio (SNR) in the frequency range O-fs is the same as before, but the noise energy has been spread over a wider frequency range. σδ ADCs exploit this effect by following the 1-bit ADC with a subsequent digital filter. An example of an embodiment of the invention having such a subsequent digital filter, SF, is shown in Figure 11, described below. The RMS noise is reduced, because most of the noise is removed by this subsequent digital filter. This action enables σδ ADCs to achieve wide dynamic range from a low-resolution quantizer. By summing an error voltage, which is the difference between the input signal and a feedback signal, the loop filter in the form of an integrator function, acts as a lowpass filter to its input signal. Most of the quantization noise is pushed into higher frequencies where it is removed by digital filtering. Oversampling and integrating has changed not the total noise power, but its distribution.

The subsequent digital filter can average the 1-bit data stream, improve the ADC resolution, and remove quantisation noise that is outside the band of interest. It determines the signal bandwidth, settling time, and stopband rejection. The subsequent digital filter is after the σδ modulator, and should not be confused with the digital filter of the σδ modulator as described below. A comparative example illustrating some features of a σδ modulator 100 is shown for reference purposes in Figure 1. The σδ modulator 100 comprises an analogue input 15 for receiving an input signal X, an analogue loop filter 20, a multi-bit quantizer 30 with sample frequency f _s , a digital output 17 for providing an output signal Y, a feedback DAC 40 for calculating the analogue representation of the quantized signal, and a summing

stage 10 for calculating an error signal as the difference between the input signal X and the quantized signal. To the σδ modulator 100 a sample frequency of f _s = k x 2 x few is applied, where few is the signal bandwidth. The oversampling ratio k indicates how many times the sample frequency is higher than the sample frequency defined by Nyquist. In order to have a high signal-to-noise ratio the quantizer 30 should have a high-resolution.

In order to calculate the analogue representation of the quantized signal, the DAC 40 should have the same resolution as the quantizer 30. Unfortunately in practice it is difficult to provide such a DAC 40 with sufficient linearity, due to non-linearities in the feedback. DAC 40 quantization noise can fold back into the signal bandwidth, which decreases the maximum signal-to-noise-and-distortion ratio (SDNR). Furthermore non- linearities in the DAC 40 will also cause harmonic distortion of the input signal.

The σδ modulator 100 of Fig. 1 can be modelled with the scheme shown in Fig. 2, where the quantizer 30 is replaced by a quantization noise source having a noise N and a gain C, which represents the gain of the quantizer. From this model the transfer function can be calculated as:

CH

Y = X + -N (1)

1 + CH 1 + CH

where H is the transfer function of the loop filter 20. For the loop filter 20, a low pass filter implemented with integrators is assumed, which has very high gain for low frequencies and has a certain order roll-off for higher frequencies. At low frequencies the signal X at the input 15 is amplified to the output 17 with a factor of one because of the high gain in the loop filter 20, and the quantization noise is suppressed with this gain. At high frequencies the loop filter 20 has a low gain and the noise rises with the loop filter order. This is an arbitrarily chosen σδ converter. It can be of any order and any number of bits. In Fig. 3, a block diagram of a 4 ^th order loop filter is shown as an example.

This can be used in embodiments of the invention such as the embodiment of Fig. 8. It can be implemented using analogue circuitry or digital circuitry. A first integrator 70 is followed by a first clipping circuit 80. An output of the first clipping circuit 80 is amplified by a first amplifier 90 having a gain ai. The output of the first clipping circuit 80 is also fed along a chain of further integrators 72, 74, 76 and clipping circuits 82, 84, 86 coupled in series. At each stage, the output of each clipping circuit 82, 84, 86 is fed to respective amplifiers 92, 94, 96 having respective gains a _{l s} a ₂ , a ₃ and a ₄ . The outputs of the amplifiers 90, 92, 94, 96 are

summed by a summing stage 98 to provide the overall output of the loop filter 20. Filters of other orders can be provided by altering the number of integrators in the chain.

For high frequencies, the loop transfer function is reduced to first order by the feed-forward gain coefficients a ₂ , a ₃ and a ₄ to ensure loop stability. The clip levels are implemented to ensure stability at large amplitude input signals.

In Figure 4, the transfer function H of the 4 ^th order loop filter 20 is shown (upper of the three lines) together with the closed loop Signal Transfer Function (STF, middle line of the three lines) and Noise Transfer Function (NTF, lower of the three lines). The STF and NTF are defined below :

STF = - = -^L (2a)

X 1 + C.H ^V '

NTF = I = (2b) N 1 + C.H

The order of the loop filter can be read from the plot and indeed is 4 ^th order.

The noise transfer function rises 4 ^th order with frequency.

In the STF a bump is present, caused by the limited phase margin of the loop filter H. At high frequencies the loop has to return to first order for loop stability, but lowering the return-to-first-order frequency will reduce the suppression of quantization noise in the signal bandwidth, which is unwanted. So a trade-off has to be made between phase margin and suppression of quantization noise.

A simulated frequency response of the σδ modulator 100 of Figure 1 is shown in Figure 5. The signal-to-noise ratio calculated from the plot is 68 dB in a 2MHz bandwidth at a sample rate of 153.6 MHz. The 4 ^th order noise shaping can be recognized in the spectrum.

The quantizer 30 and DAC 40 in a σδ modulator 100 are normally of the same resolution and can be 1-bit or multi-bit. An output bit-stream of a 1-bit and a 5-bit σδ modulator are displayed in Figure 6, together with an ideal input sine wave, where n is the number of quantization levels, respectively 2 and 32 . The 1-bit stream varies between 1 and - 1, while the 5 -bit stream is close to the ideal, that is the analogue sine wave prior to quantization.

When comparing the two bit-streams it is easy to see that the quantization noise is smaller when a multi-bit quantizer and DAC combination is used. The improvement in quantization noise, going from 2 level to a higher number of levels 2 ^W , for a w-bit quantizer, can be calculated with the formula below :

This formula indicates an improvement of approximately 6dB for each bit of a multi-bit quantizer. When comparing the sinewaves in Figure 6, which indicate the maximum input signal, another thing that can be seen from the bit-streams is that the input amplitude can be larger in a multi-bit modulator when compared to a 1-bit modulator. The maximum signal-to-quantization-noise ratio (SQNR) is given by the following formula:

where Vj _{n max w} is the maximum amplitude of the input signal for a w-bit quantizer, which has 2 ^W quantization levels, and V. _o is the maximum amplitude of the input signal for

a 1-bit quantizer, which has 2 levels.

A simulated noise amplitude of a 1-bit and 5 -bit modulator is shown in Figure

7 for a resolution bandwidth (RBW) of 1OkHz, the lower of the two lines being for the 5 -bit modulator, and the upper line being for the 1-bit modulator. From simulation a SQNR of

67.7dB is derived for the 1-bit modulator and a SQNR of 101. IdB for the 5-bit modulator. This is an improvement of about 33dB when going from 1-bit to 5-bit. A theoretical estimation yields 29.8 dB improvement in SQNR from formula 3 and 2.9 dB from formula 4. A problem of multi-bit σδ modulators is the linearity in the DAC 40. Due to non-linearities in the feedback DAC 40, quantization noise can fold back into the signal bandwidth, which decreases the maximum achievable SNDR. Furthermore non-linearities in the DAC 40 will also cause harmonic distortion of the input signal.

Static and dynamic non-linearities can occur in the feedback DAC 40. Static non-linearities originate from mismatches in the feedback DAC 40 unit cells. These unit cells implemented with resistors, capacitors or current sources are used to create the different output levels in the DAC 40 and when there are mismatches in these unit cells the transfer curve of the DAC 40 will not be a straight line. Based on experience, static DAC linearities of about 60-70 dB are achievable, depending on the implementation of the unit cell. To reduce the static non-linearities in the DAC 40, Dynamic Element Matching (DEM) and Data Weighted Averaging (DWA) techniques can be used, of which the topologies are well known and will not be discussed here. Dependent on their implementation, extra chip area and a higher sample frequency is often needed to facilitate the improvement scheme. Furthermore the improvement in SNDR is only small.

The second non-linearity that occurs in multi-bit modulators is of the dynamic kind. A dynamic non-linearity occurs when switching charges are not the same at every DAC output level, for example due to parasitics. At high speeds this becomes more severe and has to be considered very carefully in circuit design and layout.

A special kind of 1-bit modulator is a 1.5 bit modulator. In this modulator both the quantizer 30 and feedback DAC 40 have three levels (+1, 0, -1). In the middle level, the feedback current is zero, which is easy to implement in circuit design. In 1.5 bit modulators good static linearity of the feedback DAC 40 is rather easy to achieve. In prior multi-bit σδ modulator solutions, the feedback DAC 40 is also multi- bit, and the dynamic linearity problem can solved in different ways:

Dynamic Element Matching / Data Weighted Averaging. This class of techniques to linearise the DA 40 is limited by the order of the loop filter 20, and often needs a higher clock frequency than the sample frequency f _s used for the σδ modulator 100. Barrel shifting of unit elements. In this technique the unit cells of the DAC 40 are rotated in use, which gives only a small improvement in linearity.

Calibration of current sources. The calibration of current sources improves the linearity of the DAC 40, and linearities up to 14-bit are shown in publications, but this kind of linearising techniques is quite complicated to design. The embodiments of the invention involve a different approach, but these known approaches, or features of them can also be combined with the different approach of the embodiments described.

The embodiments of the invention described relate to apparatus or methods for providing more linear feedback to a multi-bit modulator. In some embodiments a σδ

modulator is provided comprising a signal processing chain with successively a loop filter, an n-bit quantizer, a digital filter and a 1-bit quantizer. Some embodiments of the invention as will be described below can comprise in addition to the standard noise shaping loop filter 20 and a multi-bit quantizer 30, a digital filter for filtering the output of the multi-bit quantizer 30 and a 1-bit quantizer for quantizing the output of the digital filter and providing the output signal Y and the feedback signal. On the one hand the 1-bit quantizer is inherently linear. On the other hand the presence of the multi-bit quantizer 30 enables part of the loop-filtering to be handled by the digital filter. Alternatively, a further multi-bit quantizer can be used in place of the 1-bit quantizer. The digital filter can have a frequency characteristic which can be shaped more flexibly so as to provide a much better suppression of the noise in the frequency region of interest, without being subject to process imperfections. Where gain is provided by the digital filter, it is not essential that a single filter provides the gain characteristic; instead the digital filter can be implemented as two or more filters in series, such as one to provide the gain in the first frequency band of interest, and another to provide a flat gain at higher frequencies.

Additional features can be as follows. These features are not necessarily essential to all embodiments; they can be omitted or substituted.

The digital filter can have an order greater than one in the passband of the σδ modulator. The gain characteristic of the digital filter outside of the passband of the σδ can have a flat gain profile. The feedback signal can comprise a 1-bit signal. The feedback signal can comprise a most significant bit of an output of the digital filter. The loop filter 20 can comprise any of a continuous time filter, a switched capacitor filter, or a digital filter. In the case of a digital filter, a converter would be used to convert the analogue input to a digital signal for input to the digital loop filter 20. The loop filter 20 can comprise a first order or higher order filter. The loop filter 20 can comprise an integrator. The digital filter can have a gain in the passband of the σδ modulator which exceeds the gain outside the passband of the σδ modulator by at least 201ogio((2 ^y -l)/(2 ^z -l)) dB, where y is the number of bits of the feedback signal and z is the number of bits of the multi-bit quantizer 30. The frequency response of the combination of the loop filter and the digital filter may have a first order roll- off of gain outside of the passband of the sigma-delta modulator. The analogue loop filter 20 and digital filter can be implemented as a bandpass filter, yielding a bandpass σδ modulator.

The above mentioned US6404368 document needs stability analysis of multiple loops, while the embodiments of the present invention only have one loop. To

contrast with US6404368, a simulation of a σδ ADC in accordance with the invention is also described below.

Referring to the embodiment of the σδ modulator 200 shown in Figure 8, elements which are identical to those of Figure 1 have the same reference numerals. The feedback loop contains the loop filter 20 discussed above, the multi-bit quantizer 30, a digital filter 50, and a 1-bit quantizer 60. If we leave out the digital filter 50 and the 1-bit quantizer 60, the loop would be a conventional σδ loop (as in Figure 1), with the loop filter 20 providing the noise shaping function, and the multi-bit quantizer 30 lowering the quantization noise by 6x dB, where x is the number of bits of the multi-bit quantizer, as discussed above. The DAC 40 should be linear to avoid high frequency quantization noise folding back into the signal band.

Gain greater than OdB in the passband of the σδ modulator 200 may be introduced between the multi-bit quantizer 30 and 1-bit quantizer 60 by the digital filter 50. The digital filter 50 can suppress the quantization noise introduced by the 1-bit quantizer 60. An output 117 can be taken from after the 1-bit quantizer 60. An alternative to the 1-bit quantizer 60 is to use multiple bits, provided fewer bits are taken than the number of bits provided by the multi-bit quantizer 30 to the digital filter 50. Other elements can be added into the loop to suit particular applications. The σδ modulator presented in Figure 8 can be linearised, which leads to the model presented in Fig. 9. In Fig. 9, Qi represents the quantization noise of the multi-bit quantizer 30, and Q ₂ represents the quantization noise of the 1-bit quantizer 60. The output signal Y at the output 117 can be calculated in terms of the input signal X at the input 15 as:

1 + HF 1 + HF ^π 1 + HF ^z

where H is the transfer function of the loop filter 20, F is the transfer function of the digital filter 50, Qi is the quantization noise due to the multi-bit quantizer 130, and Q ₂ is the quantization noise due to the 1-bit quantizer 60. As can be seen from the formula above, when the loop filter 20 and the digital filter 50 have a high gain in the pass band of the σδ modulator 200, the input signal X is amplified by one to the output signal Y in the passband. Qi is suppressed by the gain of the loop filter 20, as in a conventional σδ modulator. Q ₂ is suppressed by the product of H and F, and is even more suppressed compared to Q ₁ , if the digital filter 50 has a high gain in the passband of the σδ modulator 200. Alternatively, the

digital filter 50 need not have a high gain provided it has a high gain difference of at least 201ogio((2 ^y -l)/(2 ^z -l)) dB between the passband and outside of the passband of the σδ modulator. To get the full advantage of the multi-bit quantizer 30, Q ₂ has to be below Q ₁ , calculated to the output 17. As described above, adding a bit in the multi-bit quantizer 30, would lower quantization noise introduced by the multi-bit quantizer 30 by about 6dB.

So, compared to the 1-bit quantizer 60, the performance of the σδ modulator 200 would be about 6.z dB better. If an example of a 5-bit quantizer is taken, this would mean that the quantization noise of the 5-bit quantizer when used for the multi-bit quantizer 30 is about 3OdB below that of the 1-bit quantizer 60. This means that the digital filter 50 needs more than about 3OdB of gain in the passband to get Q ₂ below Q ₁ , to get the full advantage of the multi-bit quantizer 30 together with the 1-bit quantizer 60, which inherently provides a linear feedback path. Alternatively, the digital filter 50 needs at least about 3OdB gain difference between the passband and outside of the passband of the σδ modulator. The exact figures can be calculated as 201ogio((2 ^y -l)/(2 ^z -l) dB. Fig. 10 shows three graphs of the amplitude of the frequency response. The left graph is an example of the response H | of loop filter 20; the middle graph shows an example of the response | F of the digital filter 50; and the right graph shows the combined response HF | of the loop filter 20 and the digital filter 50. As mentioned above, the digital filter 50 should have high gain, or a high gain difference, in a first band of frequencies, for example in the bandwidth of the input signal X, or equivalent Iy in the passband of the σδ modulator, to suppress the level of the quantization noise Q ₂ below the level of Qi. The gain at higher frequencies should be lower, preferably by at least 201ogio((2 ^y -l)/(2 ^z -l) dB. Another constraint is that the digital filter 50 should not jeopardize the stability of the loop. Hence in some embodiments, to reduce or avoid instability of the loop, the digital filter 50 should have flat gain outside of the passband of the σδ modulator, in order to avoid excessive phase shift at high frequencies, which can make the loop unstable.

If the group delay at high frequencies introduced by the digital filter 50 is kept low, the loop will remain stable with little or no change to the set of gain coefficients in the loop filter 20 compared with the gain coefficients required for the loop filter 20 for a conventional σδ modulator 100. Thus, the frequency response of the combination of the loop filter and the digital filter can provide a first order roll-off of gain outside of the passband of the sigma-delta modulator.

From the right-hand graph in Figure 10 it can be seen that in the signal bandwidth there is more gain compared to the left graph (the difference is |F|). The

quantization noise of Q ₂ will not only be suppressed by the loop filter 20 but also by the digital filter 50. From the same graphs it can be seen that the stability of the σδ modulator 200 remains unchanged, compared with a conventional σδ modulator 100, because the frequency response of the digital filter 50 is flat and does not have excessive phase shift at high frequencies. Because the stability of the loop filter 20 is determined by the feedforward gain coefficients a _{l s} a ₂ , a.3, a ₄ of the analogue loop filter 20, no additional feedback paths will be required. This helps make the design of such a σδ modulator much simpler.

In the graphs of Figure 10, the transition in the frequency response H of the loop filter 20 between a first order response and a higher order response occurs at the same frequency as the bandwidth of the digital filter 50. However this is not an essential requirement, and the transition may occur at a higher or lower frequency.

Advantageously the gain profile of the digital filter 50 should be flat, and not exceed one outside the passband of the digital filter 50. In order to ensure the stability of a feedback loop, typically the first order slope of the gain profile of the filtering in the loop, in this case the combination of the loop filter 20 and the digital filter 50, has to go through OdB .

The loop filter 20 of a conventional σδ modulator 100 has this first order slope, so if another slope in the characteristic is added into the loop, it will tend to become unstable. Therefore, by providing the digital filter 50 with a gain profile that is flat, and does not exceed one outside the passband of the digital filter 50, the coefficients of a conventional σδ modulator 100 typically do not need to be altered. Clearly the gain characteristic can be a band pass characteristic, with lower gain at frequencies above and below the signal band.

Fig. 11 shows an embodiment of an analogue-to-digital converter 300 employing the σδ modulator 200 shown in Figure 8. The output signal Y of the σδ modulator 200 is fed to an input of a subsequent digital filter 70 having a transfer function SF.

In Fig. 12, the output spectrum over a range of 100 Hz to 300 MHz on a logarithmic scale, of a conventional 5 ^th order σδ modulator 100 comprising a 5-bit quantizer is shown (lower plot). The figure also shows the output spectrum of the new architecture according to the invention (upper plot), which in this case is also implemented with a 5 ^th order loop filter 20 and a 5-bit quantizer 30. The σδ modulator 200 in this case uses a digital filter 50 which has 3OdB gain in the passband of 50OkHz and OdB gain at higher frequencies.

The signal-to-noise ration (SNR) of the new σδ modulator 200 is 134.3dB, about 4dB worse compared to the conventional σδ modulator 100 which has a SNR of 138.4dB. This is due to the gain of the digital filter 50. As indicated above, the gain of the

digital filter 50 in the pass band of the σδ modulator 200, or gain difference inband and out- of-band, should be at least 201ogio((2 ^y -l)/(2 ^z -l) dB. This is not the case in this example; the gain is 3OdB which is just enough to attenuate Q ₂ to the same level as Qi, which means the total noise rises by 3dB compared to the conventional σδ modulator 100. This can be improved by increasing the gain, or inband and out-of-band gain difference, in the digital filter 50. At high frequencies the quantization noise is higher for the new architecture compared to the conventional architecture. This is the quantization noise of the 1-bit quantizer because the digital filter 50 has OdB gain at high frequencies.

Embodiments of the invention can benefit from the fact that there is a multi-bit quantizer 30 in the loop, can benefit from the advantages of a 1-bit inherently linear feedback DAC 40, and can have a higher degree of digitization because a multi-bit DAC which has to be very linear, (therefore needing precision analogue parts) is replaced by a digital filter.

An example application in a radio frequency (RF) receiver or other system can have an ADC comprising the σδ modulator 200 and followed by an adaptable digital filter for channel selection or noise removal, or other purpose. A detector determines a level of interference from outside the desired signal band, and feeds this information forward to the adaptable filter. Other analogue circuitry stages can precede the ADC, and other digital processing stages can follow the adaptable digital filter. There can also be other digital processing stages before the adaptable filter, such as automatic gain control (AGC). The arrangement can form part of a wireless receiver, or can be applied to other systems susceptible to changing interfering signals. The interference information can optionally be fed forward to other subsequent circuit stages such as an equalizer, or a demodulator for example. The amount of processing by these subsequent stages can be adjusted according to the information, to suit different conditions. For example the number of least significant bits used can be changed or a number of filtering stages changed to save power consumption.

Also, optionally the detector can be fed from the analogue signal before the ADC. In this case, a relatively simple filter can be implemented in the detector by means of analogue components, or the signal can be converted to digital format and a simple digital filter can be implemented with a relatively low number of coefficients and a relatively low update rate.

In a receiver having an adaptable digital filter and a σδ ADC, the adaptable digital filter can combine the decimation function for the ADC and the channel filter function. This can be implemented in an ASIC (application specific integrated circuit) or FPGA (field programmable gate array) type circuit, or can be carried out by a DSP (digital

signal processor), as desired. A DSP can be provided for subsequent digital processing such as demodulation, equalization and so on.

The receiver can have an antenna, and conventional analogue circuitry such as an RF filter, followed by a mixer for mixing a local oscillator signal LO. An analogue low pass filter is followed by the σδ ADC. This feeds a digital signal to the adaptable digital filter, which is adapted according to the unwanted signal information, to adapt the channel filter function to optimize it for power efficiency. The detector can be much simpler than the adaptable digital filter, to save power or reduce complexity. Notably, the adaptation of the digital filter processing can be relatively autonomous, in other words independent of higher levels of software controlling a system or applications using the circuitry, and so need not add complexity to the interface to such software. The detection information can include power levels, averaged levels, frequencies, frequency ranges, comparisons to thresholds, comparisons to wanted parts of the signal, combinations of these and so on.

Another application as an alternative to an ADC is a digital-digital noise shaper. In this embodiment, the arrangement of Figure 8, or of Figure 11 can be used, with the loop filter 20 being a digital filter, and the input signal X being a digital signal rather than an analogue signal. The quantizer 30 in this case acts as a re-sampler, taking a number of samples at a low quantization level, and outputting a single sample at a higher quantization level. Also, the DAC 40 can be omitted from the feedback path and the summing stage 10 implemented digitally. Other variations and additions can be envisaged within the scope of the claims.

The present invention has been described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. Where the term "comprising" is used in the present description and claims, it does not exclude other elements or steps. Where an indefinite or definite article is used when referring to a singular noun e.g. "a" or "an", "the", this includes a plural of that noun unless something else is specifically stated. The term "comprising", used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. References to numerical values or ranges are approximate.