FILTER

TECHNICAL FIELD

The present invention relates to digital signal processing, and more specifically, to multi-rate digital signal processing systems and methods.

BACKGROUND

In almost every activity involving electrical devices, some manner of data transmission is necessary to enable communication between the devices. This communication may be transmitted between the devices over a communication channel such as copper wires, optical fibers, wireless communication channels and storage media. The transmitted data may be represented as an electromagnetic signal such as, for example, an electrical voltage, radio wave, microwave or an infrared signal. The signal may be transmitted as an analog signal, which is a transfer of a continuously varying signal, or the signal may be transmitted as a digital signal, which is a transfer of discrete messages that may be represented as a code modulated on the transmission carrier as, for example, a baseband transmission or a passband transmission. The discrete messages may be represented as a bit stream or a digitized analog signal.

In many communication systems, a signal transmitted from a sending device to a receiving device often involves transmission of the signal across different communication media. Such a hybrid transmission path may sometimes require that different data rates be transmitted on particular media due to different capabilities of the media, different quality of service (QoS) requirements or different service level agreements, for example. Sometimes a signal transmitted from a sending device to a receiving device includes traversal of only a single communication medium, but an amount of data provided by the sending device may exceed a capacity of the communication medium.

In that regard, there can be a need to convert the sampling rate of a digital signal from a higher to a lower sampling rate to reduce processing speed requirements

U_

or resources. A rational fraction rate change of D can be implemented by first up- sampling by a sample rate U, then by filtering the interpolated signal to remove the interpolation images and finally down-sampling by a sample rate D. However, this is not an efficient method to implement in hardware as it may require higher processing speeds and more resources to initially up-sample the signal by a factor of U than the hardware will support or is economically feasible.

Changes to sampling rates can be efficiently implemented through a digital filter called a polyphase Finite Impulse Response (FIR) Rate Change Filter (RCF). The RCF may be implemented as a polyphase FIR filter, in which every output sample y(m) is generated by multiplying the input stream with a subset (phase) of the filter coefficients and summing the resulting products according to the following equation:

(Eq. 1):

Where:

Ntap is the number of taps, i.e., the number of coefficients per phase;

h is the filter impulse response;

x is the input stream;

y is the output stream;

U is the up-sampling factor;

D is the down-sampling factor;

Lx is the length of the input stream x;

L x U

m is the index of output stream y, with length

D

n is the filter tap index;

Ι ^L α ^J I is the rounding function towards minus infinity, i.e., the floor function; and

Γ ¹ αΐ ¹ is the rounding function towards plus infinity, i.e., the ceiling function.

The up-sampling and down-sampling factors are simply determined by the ratio of the filter input and output sample rates. For example, a stream having rate changed from 500 MHz to 400 MHz, the U and D factors could be any combination of integers that produces a ratio of 0.80. The up-sampling and down-sampling factors could be, for example: U=40 and D=50. The length of the filter impulse response is partly determined by the up-sampling factor:

(Eq. 2): Filter impulse response length = Ntap * U.

In recent communication systems, sample data rates are becoming faster, while requiring complex digital signal processing functions. These rates can be too fast to be realizable in digital hardware using a direct method of implementation in existing technologies such as Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs).

When the procession speed required exceeds the hardware limitations, direct form implementation of the Fractional RCF, as discussed above, is not a viable solution.

Therefore parallel branching of the data paths may be used to reduce the required internal processing speed of the hardware, but at the expense of resources. In this invention of a Fractional Rate Change Filter with an— ratio of less than one, the

D

signal processing functions must be modified at the algorithm level to implement parallel branching. An output rate of a polyphase Finite Impulse Response (FIR) Rate Change Filter is limited by the operating speed of the hardware. Further, control and coordination of the branches of the hardware resources requires specialized handling.

SUMMARY

The present invention relates to using a multi-branch finite impulse response filter to convert the sampling rate of a digital signal from a higher to a lower sampling rate. In accordance with one embodiment, a method of filtering an input sample stream having a downsampling rate to generate an output sample stream having an upsampling rate less than the downsampling rate includes inputting the input sample stream to a rate change filter that has multiple filter branches. The input sample stream is filtered at each of the multiple filter branches to output filtered sample substreams, wherein each of the multiple filter branches have filter coefficients that correspond to a different phase of the filter response. The filtered sample substreams are stored in a memory. The stored output sample substreams are combined to generate the output sample stream.

In accordance with an aspect of this embodiment, filtering the input sample stream at each of the multiple filter branches includes multiplying, during successive taps of a clock cycle, the input sample stream input of each filter branch by a set of filter coefficients to generate a set of products. The set of products is combined to generate a filter output signal for a respective filter branch. In accordance with another aspect of this embodiment, filtering the input sample stream in each of the multiple filter branches includes delaying the successive taps of each filter branch. The filter output signals from each respective branch are interleaved. In accordance with yet another aspect of this embodiment, the multiple filter branches include a finite impulse response filter. Delaying the successive taps includes including a first delay in an output of successive taps of each branch of the multiple branches to account for filter pipelining delays. Second delays are included in successive taps of each branch to account for a phase delay between taps of each branch of the multiple filter branches.

In accordance with still another aspect of this embodiment, storing the filtered sample substreams in memory includes determining whether an output sample of a filtered sample substream is valid based on an index of the input sample stream. The filter coefficients correspond to taps of each branch of the multiple filter branches. An index of the output sample stream is incremented if the output sample of the filter branch is valid. In accordance with an aspect of this embodiment, determining whether an output sample is valid is based on an index of the input sample stream, the upsampling rate and the downsampling rate. In accordance with another aspect of this embodiment, determining whether the output sample is valid is determined by

(k + l)U W_

valid (k)

D D

, wherein k is the index of the input sample stream; U is the upsampling rate; D is the downsampling rate; y is the output stream; and [x] is a ceiling function on x.

In accordance with yet another aspect of this embodiment, storing the generated output sample substreams in the memory includes storing the generated sample substreams in multiple output buffers. The multiple output buffers correspond to the multiple filter branches. Storing the generated output sample substreams include determining an index of the output sample substream. The determined index is used as a memory address of the multiple output buffers. The stored output sample substream is output from the memory address of the determined index as an output value. In accordance with still another aspect of this embodiment, the generated output sample substreams are stored in multiple output buffers. The multiple output buffers correspond to the multiple filter branches. The determination that the output sample of the input sample stream is valid is used as write control logic to determine which buffer address to write the filter branch outputs.

In accordance with another embodiment, a rate change filter for filtering an input sample stream having a first sample rate to generate an output stream having a second sample rate less than the first sample rate includes multiple branches of a rate change filter. Each of the multiple branches has an offset state to filter the input sample stream using filter coefficients in each branch corresponding to different phases and to generate multiple output substreams. An input control circuit is configured to control input of the input sample stream to each of the multiple branches of the rate change filter. A filter control circuit is configured to control filter coefficients of the rate change filter to output filtered sample substreams. An output control circuit is configured to control output of sample substreams generated at each of the multiple branches of the rate change filter. In accordance with an aspect of this embodiment, each branch of the multiple filter branches is configured to multiply, during successive taps of a clock cycle, the input sample stream fed to each filter branch by a set of filter coefficients to generate a set of products and combine the set of products to generate a filtered output substream for a respective branch. In accordance with another aspect of this embodiment, each branch of the multiple filter branches is further configured to delay successive taps of each branch. First delays are included in an output of each of the successive taps of each branch to account for filter pipelining delays. Second delays are included in an input of each of the successive taps of each branch to account for a phase delay between respective branches of the multiple filter branches. The output signals from each respective branch are interleaved. In accordance with yet another aspect of this embodiment, the output control circuit is further configured to determine whether an output sample is valid. The coefficient index of each branch of the multiple branches is updated. An index of the output sample stream is incremented if the output sample is valid.

In accordance with still another aspect of this embodiment, the output control circuit is further configured to determine whether an output sample is valid based on an index of the input sample stream, the first sample rate and the second sample rate. In accordance with an aspect of this embodiment, the output control circuit is further configured to store the generated output sample substreams in multiple output buffers, the multiple output buffers corresponding to the multiple filter branches of the rate change filter. In accordance with another aspect of this embodiment, the output control circuit is further configured to store the generated output sample substreams by determining an index of the output sample substream. The determined index is used as a memory address of the multiple output buffers. The stored output sample substream is output from the memory address of the determined index as an output value. In accordance with yet another aspect of this embodiment, the output control circuit is further configured to store the generated output sample substreams in multiple output buffers, the multiple output buffers corresponding to the multiple filter branches. The determination that the output sample is valid is used in determining when and to which buffer to write the filter branch outputs. A method of filtering an input sample stream having a first sample rate to generate an output sample stream having a second sample rate less than the first sample rate includes inputting the input sample stream to a rate change filter having multiple filter branches. The input sample stream is filtered at each of the multiple filter branches to output filtered sample substreams. Each of the multiple filter branches has filter coefficients corresponding to a different phase of the filter response. The filtering includes multiplying, during successive taps of a clock cycle, the input sample stream input to each filter branch by a set of filter coefficient to generate a set of products. The set of products are combined to generate a filter output signal for a respective filter branch. The successive taps of each filter branch is delayed by including first delays in an output of successive taps of each branch of the plurality of branches to account for filter pipelining delays. Second delays are included in successive taps of each branch to account for a phase delay between respective branches of the plurality of filter branches. The filtered sample substreams are stored in a plurality of output buffers. The plurality of output buffers correspond to the plurality of filter branches. Storing the generated output sample substreams includes determining an index of the output sample substream. The determined index is used as a memory address of the plurality of output buffers. The stored output sample substream is output from the memory address of the determined index as an output value. The stored output sample substreams are combined to generate the output sample stream.

In accordance with an aspect of this embodiment, determining an index of the output sample substream includes determining whether the output sample of the input

(k + W_ kU

valid (k)■

D D

sample stream is valid by , where k is the index of the input sample stream; U is the upsampling rate; D is the downsampling rate; y is the output stream; and [x] is a ceiling function on x.

In accordance with another aspect of this embodiment, determining an index of the output sample substreams include determining whether an output sample of the input sample stream is valid. The set of filter coefficients correspond to the taps of each branch of the plurality of filter branches. An index of the output sample stream is incremented if the output sample is valid.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an exemplary rate change filter system constructed in accordance with principles of the present invention;

FIG. 2 is a detailed block diagram view of an exemplary rate change filter constructed in accordance with principles of the present invention, shown as a two branch system;

FIG. 3 is a block diagram of a multi-branch systolic filter in accordance with principles of the present invention, shown as a two branch system;

FIG. 4 is a block diagram of FIR tap delays for a multi-branch rate change filter in accordance with principles of the present invention, shown as a two branch system;

FIG. 5 is a block diagram of coefficient memory addressing in accordance with principles of the present invention;

FIG. 6 is flow chart of an exemplary process of filtering an input stream to produce an output stream in accordance with principles of the present invention;

FIG. 7 is a flow chart of an exemplary process of filtering the input signal using a finite impulse response filter in accordance with principles of the present invention;

FIG. 8 is a flow chart of an exemplary process of accounting for pipelining delays and for the phase of the input signal in accordance with principles of the present invention;

FIG. 9 is a flow chart of an exemplary process of storing the filtered output sample substreams in the output data buffers in accordance with principles of the present invention; and

FIG. 10 is a flow chart of an exemplary process of determining an index of the output sample stream in accordance with principles of the present invention. DETAILED DESCRIPTION

It will be appreciated by persons skilled in the art that the present invention is not limited to what has been particularly shown and described herein above. In addition, unless mention was made above to the contrary, it should be noted that all of the accompanying drawings are not to scale. A variety of modifications and variations are possible in light of the above teachings without departing from the scope and spirit of the invention, which is limited only by the following claims.

As used herein, relational terms, such as "first" and "second," "top" and "bottom," and the like, may be used solely to distinguish one entity or element from another entity or element without necessarily requiring or implying any physical or logical relationship or order between such entities or elements.

In embodiments described herein, the joining term, "in communication with" and "connected to," and the like, may be used to indicate electrical or data communication, which may be accomplished by physical contact, induction, electromagnetic radiation, radio signaling, infrared signaling or optical signaling, for example. The above methods of achieving electrical or data communication are non- limiting and mentioned only for illustration. One having ordinary skill in the art will appreciate that multiple components may interoperate and modifications and variations are possible of achieving the electrical and data communication.

Referring to the drawing figures in which like reference designators refer to like elements, FIG. 1 shows a block diagram of an exemplary rate change filter system 10 according to an exemplary embodiment of the present invention. A filter 12 of the rate change filter system 10 receives an input signal having a frequency Fs and outputs a signal having a frequency Fs*U/D. According to some exemplary embodiments, the filter 12 may be implemented by a processor 14, which may include, for example, an Application Specific Integrated Circuit (ASIC) and a Field Programmable Gate Array (FPGA). The filter and/or processor may also include memory, such as non-transitory memory, for storing programmatic code and/or data associated with the implementation of the functions described herein.

A detailed exemplary block diagram of the filter 12 is described with reference to FIG. 2. An input signal x(k) having a frequency Fs is delayed by a delay element 16 and input to an input data buffer 18. A number of delay elements 16 may delay the input signal x(k), to correspond to a number of taps or coefficients corresponding to phases of the filter 12 and are stored as input samples in the input data buffer 18. An input data control logic module 20 controls storing the input samples in the input data buffer 18. Each of the input sample streams of the input data buffer 18 are output to a Rate Change Filter (RCF) 22. The rate change filter 22 is controlled by a filter coefficient control module 24. A filter output data valid control module 26 is connected to the filter coefficient control 24 and is configured to determine valid filter coefficients of RCF 22.

The output of RCF 22 is transmitted to a Finite Impulse Response (FIR ) output data selection module 30. The FIR output data selection module 30 is controlled by an output buffer pointer control 28, which includes input from the filter output data valid control 26. The output buffer pointer control 28 determines an address of the N Output Data Buffers 32 to save the selection of FIR output data 30, which are combined to output an output signal y(m) having a output frequency Fs*U/D. In accordance with principles of the present invention, U/D is less than 1.

L x U

From Eq. 1 , the length of m is calculated as , where L _x is the length

D

of the input stream x. Where k is the input stream index:

(Eq. 3): kU

, fc e [0 : L, - l].

D

An output of the FIR Rate Change Filter shown in Eq. 1 with respect to the stream index can then be rewritten as:

Because the targeted ratio for the RCF rate requires that _ is less than one,

D

the U factor is always smaller than the D factor. If U = D, Eq. 3 reduces to m = k, which bounds the increment step of the m index to no more than one for each k index. One having ordinary skill will recognize that as the k index increments from one cycle to another, the output stream index m increments or remains the same value at a rate dependent on the ratio of— .

D

A block diagram of a multi-branch systolic filter 34 having two branches 36 and 38 is shown according to an exemplary embodiment with reference to FIG. 3. The first branch 36 includes n tap inputs FIR0_tap[n-l] through FIR0_tap[0] sampled at a first time to. Each input FIR0_tap is delayed by delay element 16 and convolved with N impulse coefficients ko(0) through ko(N-l). A result of each convolution is delayed, at each stage, by a delay element 16 and summed in a first pipeline 40. The output of the first pipeline 40 is a first sample output series for the first branch 36. The second branch 38 includes n tap inputs FIRl_tap[n-l] through FIRl_tap[0] sampled at a second time ti. Each input FIRl_tap is delayed by delay element 16 and convolved with N impulse coefficients ki(0) through ki(N-l). A result of each convolution is delayed by a delay element 16 and summed in a second pipeline 42. The output of the second pipeline 42 is a second sample output series for the second branch 38. Delay elements 16 for tap inputs FIR0_tap and FIRl_tap ensure that the tap coefficients are properly sampled for the corresponding samples for phases of a branch cycle.

It will be appreciated that although the exemplary embodiment of systolic filter 34 shows a two-branch systolic filter, more than two branches may be implemented.

A block diagram of the FIR tap delays for the multi-branch rate change filter is shown according to an exemplary embodiment with reference to FIG. 4. According to an exemplary embodiment, the FIR RCF 22 has, for example, 12 taps (Ntap=12), and, for example, two branches. The appropriate input samples are aligned to the input filter branches to take into account a systolic pipelining delay and phase delay of the branch cycle. It can be shown, in this exemplary embodiment, that data input to the systolic filter pipeline, Din_0[j], is delayed for FIR0_tap[l l:0][j] by [S((n-1)*3), S((n-2*3), ...S(3), S(0)], for the first branch where the number of taps is 0:NTaps-l, and j is the tap index. The delay structure for FIRl_tap[l l :0] j] is [S((n-1)*3 + 1), S((n-2)*3 + 1), ... S(4), S(l)], for the second branch where the number of taps is 0:NTaps-l , and j is the tap index. According to a generic exemplary embodiment having NTaps taps and N branches, it can be shown that for FIRi_tap[Ntaps-l :0], the delay structure is [S((n- l)*3+i), ... S(0)] for i=0:N-l and n=0:Ntaps-l.

For k+1 indices where m does not increment compared to the k index, the summation of the filter in Eq. 4 is not valid. It is therefore, necessary to determine a valid index for k. If (k + i)U kU 1 , y(k) is valid, otherwise y(k) is not valid:

D D

(k + l)U kU

(Eq. 5): valid _y (k) -- D D

The ceiling function may be converted to floor functions and modulo functions using the following properties:

mod y

xmod y = x— y ; or, conversely x— x

y

Eq. 5 then may reduce to:

(k + l)U

valid _y (k) ^■ ■

D D

(k + 1)U - 1 kU - 1

D

[((k + l)U - 1) - ((k + l)U - 1) mod D]- [(kU - 1) - (kU - 1) mod D] .

D

and finally,

U - ((k + l)U - 1) mod D + (kU - 1) mod D

(Eq. 6): valid (k) - D

For valid _y (k)=l, Eq. 6 reduces to:

(Eq. 7): D - U = (kU - 1) mod D - ((k + 1)U - 1) mod D) .

A modified modulo-D counter may be used to indicate whether the output index m of the filter is valid or not for the particular input index k. The modified modulo-D counter is equivalent to (kU-1 )mod D, and increments by U each k" ¹ sample. One having ordinary skill will recognize that when k is equal to or greater than the difference of D and U, the modified modulo-D counter will roll over for the k+1 sample, and (k + l)U - l would increment. Another way of describing whether

D

y(k) is valid is by determining when the modified modulo-D counter will rollover:

(Eq. 8): If (kU -l)mod(D) >= D - U , valid _y (k) = 1 else valid _y (k) = 0.

The validy(k) determines when to increment the coefficient index m and may also be used to determine when the filter output sample is written to the output data buffer 32. In the exemplary embodiment where N = 2, the data valid signal has to be calculated for two samples within the same clock period, therefore two branches of modulo counters are used in determining a buffer control:

(Eq. 9): ^{CtrBr 0( j) = (( 2 j)U ~ 1} mod( D = (k} ° ^{U ~ 1} mod( D )} '

CtrBr 1( ) = ((2 j + \)U - 1) mod( D) = (k^U - 1) mod( D ). for ^° ^{= 2j} '

° ^r ^ ₁ = 27 + l ₎ e j = [0 : l : (L _x -l)/2l

(Eq. 10): If CtrBrO(j) >= D - U , valid _y0 (j) = 1 , else valid _y0 (j) = 0 ; and

(Eq. 11): If CtrBrl(j) >= D - U, valid _yl (j) = 1 , else valid _yl (j) = 0.

For a generic N-branch design, N branches of modulo counters may be used that will increment N*U. The equations for the generic N-branch design can be written as:

(Eq. 12) : CtrBr _n ( j) = ((2 j + n)U - 1) mod(D) = ((fe„ )U - 1) mod(D),e n = 0 : 1 : N - 1 ; for k _n - Nj + n,e j - [θ : 1 : (L -1) / N] .

(Eq. 13): If CtrBr _n {j)) >=D-U, valid _y(n) ( j) = 1 , else valid _y(n) (j) = 0 , where η=0:Ν-1.

According to another exemplary embodiment, a modified modulo-D counter could directly implement a ceiling function as shown in Eq. 5. Such an

implementation would require more complex hardware than a modulo counter and may require careful handling of the k index counter to ensure correct calculation of valid _y (k) when the k index overflows the counter depth.

According to some exemplary embodiments, reloadable and time-varying coefficients are used to implement efficient rate change filters. The phase of the coefficients is dependent on the input sample index as described herein: (Eq. 14): nU + = nU + coeffPtr ;

kU

(Eq. 15): where coeffPtr = DmodU .

D

Because coeffPtr(k+l) only increments if {k + \)U increments or when

D

valid (k) as shown in Eq. 5, the valid _y (k) is used to determine when to increment the coefficient index.

For an exemplary embodiment of N=2, the two branches of coefficient index coeffPtrBrO and coeffPtrBrl can be rewritten as:

= 2_7,

(Eq. 16):

^ = 27 + l e 7 = [0 : l : (L _x -l) / 2], coeffPtrBrO(j) D modU , and

coeffPtrBrl(j) D modU.

For a generic N-branch design, the equations can be written as:

(Eq. 17): k _n = Nj + n,<E j = [θ : 1 : {L -\)I N\ n - 0 : 1 : N -l ; coeffPtrBr _n {j) DmodU .

The coefficient index increments only when the filter output is valid since the output m index increments only when the filter output is valid. Thus, the coeffPtrBrO modulo counter is incremented by 2*D if both validyo(j) and valid _y i(j-l) are equal to 1. The coeffPtrBrO modulo is incremented by D if one of valid _y o(j) and valid _y i(j-l) is equal to 1, and by 0 if neither validyo(j) nor valid _y i(j-l) is valid. For a two-branch embodiment, this can be described by:

(Eq. 18):

coeffPtrBr _Q (j) = (coeffPtrBr _Q ( j - 1) + (valid _yQ (j) + valid _≠ (j - 1)) * D) mod U , coeffPtrBr, (j) = (coeffPtrBr, ( j - 1) + (valid _yl (j) + valid _yQ (j)) * D) modU. Written generically for a N-branch design, the coefficient pointers can be calculated as:

(Eq. 19): coeffPtrBr _n (j) = {coeffPtrBr _n ( j - 1) + (∑ valid _y(l) (j) +∑ valid _y(p) (j - 1)) * D) modU, e /i = 0 : l : H -l

The coeffPtrBr _n coefficient index is used as an address to read the appropriate value from the coefficient stored in memory with reference to FIG. 5. FIG. 5 shows the coeffPtrBr _n indices stored in memories for a branch n of a multiple branch RCF. The coefficients for the branch are saved in memory 46, for taps 0 to NTaps-1, in memory TapO to NTap-1 respectively, and include delays 16 to account for the pipelining within the RCF Systolic FIR Filter stages shown in FIG. 3. Coefficients for TapO are provided with a delay of zero; coefficients for Tapl are provided with a delay of one sample; coefficients for Tap2 (not pictured) are provided with a delay of two samples; and so on until the coefficients for NTap-1, which are provided with a delay of NTap-1 samples.

An alternative method to using a modified modulo counter in Eq. 19, would be to directly implement a ceiling function as shown in Eq. 16. Such a method would require more complex hardware than a modulo counter and would require careful handling of the j" ¹ index counter for when it overflows the counter depth to ensure coeffPtrBr _n is calculated correctly. In exemplary embodiments, the increment is bounded and appropriate counter depths may be chosen to ensure that no overflow conditions occur.

According to some exemplary embodiments, the majority of the RCF 22 is implemented at a higher clock rate than the input data buffers 18 to simplify input data design and allow for flexible— ratios. An output buffer is used for clock

D

domain transfer to the lower rate. According to exemplary embodiments, there are as many output buffers as FIR branches, each output buffer having separate write control logic. The output write control logic uses the valid signals from Filter Output Data Valid Control 26 for the FIR outputs to determine when and which buffer of the N Output Data Buffers 32 to write the filter branch outputs. According to an exemplary embodiment having a two-branch RCF (N=2), a write pointer for FIR BrO writePtrBrO in Output Buffer Pointer Control 28 is incremented by:

0 if both validyo(j) or valid _y i(j-l) are not valid (0);

+1 if only one of validyo(j) or valid _y i(j-l) is valid (1); and

+2 if both validyo(j) and valid _y i(j-l) are valid.

A write pointer for FIR Brl writePtrBrl in Output Buffer Pointer Control 28 is incremented by:

0 if both validyi(j) or valid _y o(j) are not valid (0);

+1 if only one of valid _y i(j) or validyo(j) is valid (1); and

+2 if both validyi(j) and valid _y o(j) are valid.

For a generic N-branch implementation, a write pointer writePtrBr _n in Output Buffer Pointer Control 28 can be written as:

(Eq. 20):

n N-l

writePtrBr _n (j) = (writePtrBr _n ( j - 1) + (∑ valid _y(i) (j) +∑ valid _y(p) (j - 1)),

i=0 p=n+l

e ra = 0 : l : N - l

In an exemplary embodiment having a two-branch RCF, where N=2, there are two output buffers BufferO and Bufferl in Output Data Buffers 32. A LSB (Least Significant Bit) of write pointer writePtrBrO selects which buffer phase the FIR output will be written to. If the LSB equals 0, then BufferO is selected; otherwise Bufferl is selected:

(Eq. 21): bufferSelBrO(j) = writePtrBrO(j) mod 2 ; and

bufferSelBrl(j) = writePtrBrl(j) mod 2.

BufferO data is then selected from the appropriate FIR branch and writing is enabled to BufferO if:

validyo(j) and bufferSelBrO(j) = 0, or

valid _y i(j) and bufferSelBrl(j) = 0.

If Bufferl data is selected from the appropriate FIR branch and writing is enabled to Bufferl if:

validyo(j) and bufferSelBrO(j) = 1, or

validyi(j) and bufferSelBrl(j) = 1. For a generic N-branch embodiment, the buffer select for the FIR output branch can be described as:

(Eq. 22): bufferSelBr _n (j) = writePtrBr _n (j)modN,e n = 0 : l : N-l .

The Buffer _n write enable is active if:

validyo(j) and bufferSelBrO(j) = n; or

validyi(j) and bufferSelBrl(j) = n; or

validy(N-i)(j) and bufferSelBr(N-l)(j) = n.

Output Buffer Pointer Control 28 increments the buffer write address when the write enable is active. If there is no valid data for a particular j" ¹ sample, the Buffer _n write address is not incremented. The Buffer _n input data is determined by the FIR Output Data Selection 30 based on branch x where bufferSelBr _x (j) = n and valid _y (k)(l) = 1. Because valid output data is written sequentially to the N Output Data Buffers 32, the read control logic may be based on the Nth buffer write pointer writePtrBrN- i(j), and may be common for all of the output branches if the clock rate is— *— .

N D

One method of incrementing a read output readPtr(j) is to wait until a difference between the writePtrBrN-i(j) and readPtr(j) is greater than an allowable fill level. When the difference is greater than the allowable fill level, the data is read out of all N buffers at readPtr(j) simultaneously, and readDataValid(j) = 1, otherwise readDataValid(j) = 0. It will be appreciated that if the output clock rate is— *— ,

N D

readDataValid(j) will always be 1 once the buffer has reached the desired fill level.

According to another exemplary embodiment, a single output buffer may be used instead of N output buffers 32. The single output buffer may have N*output data width instead of N buffers at a single data output width. The FIR Output Data Selection 30 would need to pre-buffer N valid output data samples before writing to the final output data buffer. Therefore, N valid output data samples are written at the same time. This would add more latency to the data path through the filter 12, however, and may be more efficient for address and write control logic as N increases.

An exemplary flow chart of a process of down converting an input signal, x(k), using a multi-branch rate change filter 22 is described with reference to FIG. 6. The input signal, x(k), is input (block 100) to the rate change filter 22. The rate change filter 22 includes multiple filter branches, i.e., two or more branches, each branch having a finite impulse response filter. The input signal, x(k), is filtered at each branch of the rate change filter 22 (block 102). The filtered output values are stored in the output data buffers 32 as output sample substreams (block 104). The stored output sample substreams may be combined to generate an output signal, y(m) (block 106). According to some exemplary embodiments, the output signal is not required to be re-serialized to the full rate of Fs*U/D depending on the hardware constraints.

An exemplary detailed flow chart of filtering the input signal using a finite impulse response filter of the rate change filter 22 (block 102) is described with reference to FIG. 7. The input sample stream is filtered (block 108) at each branch of a multi-branch RCF 22. More specifically, for example, a first sample of the input sample stream is filtered at each tap of a first branch of the multi-branch RCF 22. And a second sample of the input sample stream is filtered at each tap of a second branch of the multi-branch RCF 22. The filtered output of each tap is combined (block 110) in the RCF 22 to generate a filtered output signal. An output of each tap of each branch of the multi-branch RCF 22 is delayed (block 112) in the RCF 22 to account for filtering pipeline delays. The output buffer pointer control 28 of each tap of each branch is combines or interleaves (block 114) the filtered output of each tap of each branch with the filtered outputs of the taps of at least one other branch of the multi-branch RCF 22. In this way, a finite impulse response of the input signal, x(k), is produced.

An exemplary detailed flow chart of delaying the output of each tap of each branch (block 112) to account for pipelining delays and for the phase delays of the filter coefficients applied to the input signal is described with reference to FIG. 8. To account for phase delays of the input signal and pipelining delays of a systolic filter, the RCF 22 inserts delays in the input signal and filtered outputs of each tap. A first delay is included in an output (block 116) of each filtered tap coefficient to account for phase delays of the tap coefficients used in filtering the input signal. The pipeline signal, which is a combined output signal from taps of a filter branch, includes a second delay (block 118) between successive taps of a filter branch to account for delays caused by pipelining.

An exemplary detailed flow chart of storing the output sample substreams (block 104) in the output data buffers 32 is described with reference to FIG. 9. The output sample substreams, which include a series of filtered coefficients, are stored (block 120) in multiple output buffers 32 by the FIR output data selection 30 of the filter 12. Based on the output buffer pointer control 28, the output data selection 30 determines the index of the output buffer 32 for the output sample substream (block 122) from the multi-branch RCF 22. The FIR output data selection 30 uses the determined index when saving the output sample substream to the output buffer 32 (block 124). The stored output sample substream is then output (block 126) from the output buffer 32 to produce the output signal, y(m).

An exemplary detailed flow chart of determining an index of the output sample stream (block 122) for the output data buffers 32 is described with reference to FIG. 10. The filter output data valid control 26 determines whether an output of the input coefficient is valid (block 128). In other words, a determination is made whether the output index of the filter is valid or not. If the output index of the filter is valid (block 130), an index of the output sample stream corresponding to a branch of the multi-branch RCF 22 is incremented (block 132).

In one exemplary embodiment, the system 10 can be implemented in ASICs, FPGAs or any sort of digital signal processor that can convert the sample rate of a signal by a fractional ratio, as for example, between a modem and a radio in a wireless telecommunication system. These two sub-systems may operate at two different sampling rates, where the receiving sub-system has a maximum internal operating frequency less than Fs*U/D. Either sub-system could be implemented in an ASIC, FPGA, or other digital signal processor, along with suitable memory, where maximum operating frequencies are highly dependent on the device technology. For example, there may be a system that has a transmitting sub-system operating at a sampling rate of Fs= lGsps, and a receiver sub-system that is required to process the sampled data at Fs*U/D = 1G *40/50 = 800Msps. The receiving sub-system is implemented in an FPGA with a maximum internal operating frequency of Fp= 200MHz. To process the sampled RF data as required, and still achieve timing in the FPGA, the minimum number of branches required would be Fs/Fp = 5.

The present invention can be realized in hardware, or a combination of hardware and software. Any kind of computing system, or other apparatus adapted for carrying out the methods described herein, is suited to perform the functions described herein. A typical combination of hardware and software could be a specialized computer system, having one or more processing elements and a computer program stored on a storage medium that, when loaded and executed, controls the computer system such that it carries out the methods described herein. The present invention can also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which, when loaded in a computing system is able to carry out these methods. Storage medium refers to any volatile or non-volatile storage device.

Computer program or application in the present context means any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following a) conversion to another language, code or notation; b) reproduction in a different material form.

It will be appreciated by persons skilled in the art that the present invention is not limited to what has been particularly shown and described herein above. In addition, unless mention was made above to the contrary, it should be noted that all of the accompanying drawings are not to scale. A variety of modifications and variations are possible in light of the above teachings, which is limited only by the following claims.