PRIORITY CLAIM

[0001] The present application claims priority to U.S. Patent Application Serial No. 14/541,577, filed on November 14, 2014, and entitled "MULTI- CHANNEL AUDIO ALIGNMENT SCHEMES," which is incorporated herein by reference in its entirety.

BACKGROUND

I. Field of the Disclosure

[0002] The technology of the disclosure relates generally to the Serial Low-power Inter-chip Media Bus (SLIMbus) specification announced by MIPI® and particularly for managing multiple related audio channels using a SLIMbus.

II. Background

[0003] Electronic devices, such as mobile phones and computer tablets, have become common in contemporary society for supporting various everyday uses. These electronic devices each commonly include a microphone and speakers. Typical microphones and speakers used in electronic devices have analog interfaces, requiring dedicated two (2) port wiring to connect each device. However, electronic devices may include multiple audio devices, such as multiple microphones and/or speakers. Thus, it may be desired to allow for a microprocessor or other control device in such electronic devices to be able to communicate audio data to multiple audio devices over a common communications bus. Further, it may also be desired to provide a defined communications protocol for transporting digital data relating to audio channels to different audio devices in an electronic device over a common communications bus.

[0004] The MIPI ^® Alliance has set forth the Serial Low -power Inter-chip Media Bus (SLIMbus™) standard, version 1.01 of which was released to adopters on December 3, 2008. Copies of this standard can be found to members of the MIPI ^® Alliance at www.mipi.org/specifications/serial-low-power-inter-chip-medi a-bus- slimbussm-specification. SLIMbus is designed as an interface for audio data in the mobile terminal industry, allowing communication between modems, application processors, and standalone codec chips. SLIMbus is a time division multiplexed (TDM) bus with contiguous time slots carrying samples of a given audio channel. More than one channel can be defined on the bus at the same time as bandwidth permits. SLIMbus has been generally adopted by many within the mobile terminal industry.

[0005] When more than one channel is provided in a computing device that uses a SLIMbus, the SLIMbus standard does not address how these data channels can be aligned at the destination side so as to provide optimal audio fidelity. Accordingly, the SLIMbus standard may be improved by providing related channel alignment with corresponding increases in audio fidelity.

SUMMARY OF THE DISCLOSURE

[0006] Aspects disclosed in the detailed description include multi-audio channel alignment schemes. In particular, aspects of the present disclosure provide for accumulation of audio samples across multiple related audio channels at an audio source. Related audio channels indicate their interrelatedness, and when all the related audio channels have data to transmit, the source releases the data onto the time slots of the Serial Low-power Inter-chip Media Bus (SLIMbus), such that the related audio channels are within a given segment window of the time slot. This accumulation is repeated at the boundary of every segment window. Similarly, accumulation may be performed at the audio sink. Components within the audio sink may only read received data if status signals from all related sinks indicate that predefined thresholds have been reached. By providing such accumulation options, audio fidelity is maintained across multiple audio data channels.

[0007] In this regard in one aspect, a method of controlling an audio stream is defined. The method comprises providing first data associated with a first audio channel from an audio stream to a first port in an audio service. The method also comprises providing second data associated with a second audio channel from the audio stream to a second port in the audio source. The method further comprises, at the first port, accumulating the first data in a first first in, first out (FIFO) register. The method also comprises, at the second port, accumulating the second data in a second FIFO register and programming the first and second ports to operate at identical channel rates. The method further comprises, at a segment window boundary, draining the first and second FIFO registers, such that equivalent audio samples in the first audio channel and the second audio channel are able to be grouped and placed into a segment window corresponding to the segment window boundary in a time division format.

[0008] In another aspect, a method of controlling an audio stream is defined. The method comprises providing first data associated with a first audio channel from an audio stream to a first port in a slave audio source. The method also comprises providing second data associated with a second audio channel from the audio stream to a second port in the slave audio source. The method further comprises, at the first port, accumulating the first data in a first FIFO register and at the second port, accumulating the second data in a second FIFO register. The method further comprises programming the first and second ports to operate at identical channel rates. The method also comprises a segment window boundary, draining the first and second FIFO registers, such that equivalent audio samples in the first audio channel and the second audio channel are able to be grouped and placed into a segment window corresponding to the segment window boundary in a time division format.

[0009] In another aspect, a method of controlling an audio stream is defined. The method comprises receiving first data associated with a first audio channel from an audio bus at a first port in a master audio sink. The method also comprises receiving second data associated with a second audio channel from the audio bus at a second port in the master audio sink. The method further comprises at the first port, accumulating the first data in a first FIFO register. The method also comprises at the second port, accumulating the second data in a second FIFO register. The method also comprises programming the first and second ports to operate at identical channel rates. The method further comprises comparing a first count at the first FIFO register to a first predefined threshold. The method comprises setting a first ready signal if the first count exceeds the first predefined threshold. The method also comprises comparing a second count at the second FIFO register to a second predefined threshold. The method further comprises setting a second ready signal if the second count exceeds the second predefined threshold. The method also comprises allowing contents of the first and second FIFO registers to be read if the first ready signal and the second ready signal are set.

[0010] In another aspect, a method of controlling an audio stream is disclosed. The method comprises receiving first data associated with a first audio channel from an audio bus at a first port in a slave audio sink. The method also comprises receiving second data associated with a second audio channel from the audio bus at a second port in the slave audio sink. The method further comprises at the first port, accumulating the first data in a first FIFO register. The method also comprises at the second port, accumulating the second data in a second FIFO register. The method also comprises programming the first and second ports to operate at identical channel rates. The method further comprises comparing a first count at the first FIFO register to a first predefined threshold. The method comprises setting a first ready signal if the first count exceeds the first predefined threshold. The method also comprises comparing a second count at the second FIFO register to a second predefined threshold. The method further comprises setting a second ready signal if the second count exceeds the second predefined threshold. The method also comprises allowing contents of the first and second FIFO registers to be read if the first ready signal and the second ready signal are set.

BRIEF DESCRIPTION OF THE FIGURES

[0011] Figure 1 is a block diagram of an exemplary mobile terminal with audio elements;

[0012] Figure 2 is a block diagram of an exemplary mobile terminal driving an external audio system;

[0013] Figure 3 is a simplified diagram of a SLIMbus with associated components;

[0014] Figure 4 is a simplified block diagram of ports within SLIMbus components and a SLIMbus extending between two components;

[0015] Figure 5 is a simplified timing diagram of how related audio channels are provided within a single segment window on the SLIMbus;

[0016] Figure 6 is a simplified block diagram of the elements within an audio source component according to an exemplary aspect of the present disclosure;

[0017] Figure 7 is a simplified block diagram of the elements within an audio sink component according to an exemplary aspect of the present disclosure;

[0018] Figure 8 is a flow chart of the process for the source accumulating and transmitting related channels; [0019] Figure 9 is a flow chart of the process for the sink receiving and accumulating related channels;

[0020] Figure 10 is a flow chart of an exemplary process associated with a master sink pulling data from a slave source;

[0021] Figure 11 is a flow chart of an exemplary process associated with a slave sink pulling data from a master source;

[0022] Figure 12 is a flow chart of an exemplary process associated with a slave source pushing data to a master sink; and

[0023] Figure 13 is a flow chart of an exemplary process associated with a master source pushing data to a slave sink.

DETAILED DESCRIPTION

[0024] With reference now to the drawing figures, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0025] Aspects disclosed in the detailed description include multi-channel audio alignment schemes. In particular, aspects of the present disclosure provide for accumulation of audio samples across multiple related audio channels at an audio source. Related audio channels indicate their interrelatedness, and when all the related audio channels have data to transmit, the source releases the data onto the time slots of the SLIMbus, such that the related audio channels are within a given segment window of the time slot. This accumulation is repeated at the boundary of every segment window. Similarly, accumulation may be performed at the audio sink. Components within the audio sink may only read received data if status signals from all related sinks indicate that predefined thresholds have been reached. By providing such accumulation options, audio fidelity is maintained across multiple audio data channels.

[0026] Before addressing exemplary methods and processes associated with the present disclosure, an overview of the hardware elements in which such methods and processes may be implemented are provided with reference to Figures 1-7. Exemplary processes are provided with reference to Figures 8 and 9. [0027] In this regard, Figure 1 illustrates an example of a mobile terminal 10. While a mobile terminal 10 is specifically illustrated, other processor-based systems that employ a time division multiplexed bus for multi-channel audio may also benefit from aspects of the present disclosure. In this example, the mobile terminal 10 includes one or more central processing units (CPUs) 12, each including one or more processors 14. The processors 14 may include one or more applications processors that handle audio processing. The CPU(s) 12 may have cache memory 16 coupled to the processor(s) 14 for rapid access to temporarily stored data. The CPU(s) 12 is coupled to a system bus 18 and can intercouple devices included in the mobile terminal 10. As is well known, the CPU(s) 12 communicates with these other devices by exchanging address, control, and data information over the system bus 18. For example, the CPU(s) 12 can communicate bus transaction requests to a memory controller 20 to access memory units 22(0)-22(N). Although not illustrated in Figure 1, multiple system buses 18 could be provided, wherein each system bus 18 constitutes a different fabric. Likewise, in an exemplary aspect, one of the system buses 18 may be a Serial Low-power Inter-chip Media Bus (SLIMbus) for audio. In another exemplary aspect, a SLIMbus may be present for one or more input devices (e.g., a microphone) and for one or more output devices (e.g., a speaker).

[0028] Other devices can be connected to the system bus 18. As illustrated in Figure 1, these devices can include a memory system that includes memory controller 20 and memory units 22(0)-22(N), one or more input devices 24, one or more output devices 26, one or more network interface devices 28, and one or more display controllers 30, as examples. The input device(s) 24 can include any type of input device, including but not limited to input keys, switches, microphones, voice processors, etc. In the event that an input device 24 is a microphone, it may be connected to a SLIMbus. The output device(s) 26 can include any type of output device, including but not limited to audio, such as speakers, video, other visual indicators, etc. In the event that an output device 26 is a speaker, it may be connected to a SLIMbus. The network interface device(s) 28 can be any devices configured to allow exchange of data to and from a network 32. The network 32 can be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wide area network (WAN), a wireless local area network (WLAN), and the Internet. The network interface device(s) 28 can be configured to support any type of communications protocol desired.

[0029] The CPU(s) 12 may also be configured to access the display controller(s) 30 over the system bus 18 to control information sent to one or more displays 34. The display controller(s) 30 sends information to the display(s) 34 to be displayed via one or more video processors 36, which process the information to be displayed into a format suitable for the display(s) 34. The display(s) 34 can include any type of display, including but not limited to a cathode ray tube (CRT), a light emitting diode (LED) display, a liquid crystal display (LCD), a plasma display, etc.

[0030] While the mobile terminal 10 may include plural speakers and/or plural microphones coupled by a SLIMbus, the mobile terminal 10 may be coupled to an external sound system such as through a docking station (or wirelessly). In this regard, Figure 2 illustrates a 5.1 channel surround sound system 40 with mobile terminal 10 associated with a docking station 42. The docking station 42 may include a center speaker 44 and couple to front speakers 46(L) and 46(R) as well as rear speakers 48(L) and 48(R) and a sub-woofer 50. As is well understood, each speaker 44, 46(L), 46(R), 48(L), and 48(R), and sub-woofer 50 may have a separate audio channel. When the output of the speakers 44, 46(L), 46(R), 48(L), and 48(R) and sub-woofer 50 is properly aligned, a listener 52 may experience high audio fidelity.

[0031] Regardless of whether the audio components are internal to the mobile terminal 10 (or other processor based device) or an external system, the mobile terminal 10 (or other processor based device) may include a SLIMbus to move audio data between audio components such as modems, codecs, and/or applications processors. In this regard, a simplified audio system 60 is illustrated in Figure 3. Simplified audio system 60 may include a master 62 (sometimes referred to as a master device, but because "device" sometimes has additional connotations, referred to simply as "master" hereinafter) and slave devices 64(l)-64(4) communicatively coupled to a SLIMbus communications bus 66 as components. In an exemplary aspect, the slave devices 64(l)-64(4) may be microphones, speakers, or other audio devices. The master 62 may be an application processor, a codec, or a modem, and communicates with the slave devices 64(l)-64(4) using two signals: a clock signal 68 communicated over a common clock wire 70, and a data signal 72 communicated on a common data wire 74. While only four slave devices 64(l)-64(4) are illustrated in Figure 3, it should be appreciated that more or fewer components may be coupled to the SLIMbus communications bus 66. It should be appreciated that the master 62 may have a control system (CS) 76 associated therewith, which may be a hardware implemented processor with associated software stored in memory associated with the processor. In an exemplary aspect, the control system 76 is part of the system on a chip (SoC) of the master 62. In an alternate exemplary aspect, the control system 76 may be associated with the CPU 12 of the mobile terminal 10. In further exemplary aspects, the slave devices 64(l)-64(4) each have a respective slave control system 78(l)-78(4).

[0032] It should be appreciated that each component within the simplified audio system 60 may include multiple ports, each of which may be assigned to different audio channels. Exemplary aspects of this arrangement are illustrated in Figure 4. In particular, an audio system 80 may include a first component 82(1) and a second component 82(2). First component 82(1) may include plural ports 84, of which 84(m) and 84(n) are illustrated. Similarly, second component 82(2) may include plural ports 84, of which 84(x) and 84(y) are illustrated. Ports 84 receive audio channels 86. In particular, port 84(m) receives first audio channel 86(1) and port 84(n) receives second audio channel 86(2). A serializer (not illustrated) assembles the audio data and places the audio data on the data wire 74. The second component 82(2) uses a deserializer (not illustrated) to extract the data and pass the data to an appropriate port 84. In this example, the data for first audio channel 86(1) is passed to port 84(x) and the data for second audio channel 86(2) is passed to port 84(y). The ports 84 pass the separated audio channels 86(1) and 86(2) to appropriate signal processing blocks 88(1) and 88(2).

[0033] Exemplary aspects of the present disclosure provide for accumulating audio data for related audio channels 86 and placing the corresponding samples for the respective related audio channels 86 into a segment window within the TDM signal on the common data wire 74. In this regard, Figure 5 provides an illustration of a signal flow 90 where channel samples sl l and sl2 are sampled out of the first audio channel 86(1) and channel samples s21 and s22 are sampled out of the second audio channel 86(2). The samples from the same general sampling point are accumulated and placed onto the common data wire 74 in the same segment window 92. The accumulation is done at every segment window boundary. The second component 82(2) serializes the data on the common data wire 74 and reassembles the samples. The reassembled samples 94 are aligned at the receiver.

[0034] To get the samples aligned at the source, first in, first out (FIFO) registers may be used at each port. Figure 6 provides a block diagram of the FIFO registers within a source. In this example, the source is first component 82(1) (and may also be the master 62). The first component 82(1) includes a control system, which may be CS 76. While illustrated as a processor in Figure 6, it should be appreciated that the processor may be replaced with some other signal processing entity and still be the CS 76. The CS 76 communicates with a direct memory access (DMA) module 100. While illustrated as a DMA, it should be appreciated that some other data fetch entity may be used. The DMA module 100 generates the first audio channel 86(1) and second audio channel 86(2). The first audio channel 86(1) is provided to a FIFO 102 at port 84(m). A serializer (Parallel to Serial (P2S)) 104 takes the output of the FIFO 102 and passes the serialized signal to a multiplexer (MUX) 106. Similarly, the second audio channel 86(2) is provided to a FIFO 108 at port 84(n). A serializer 110 takes the output of the FIFO 108 and passes the serialized signal to the MUX 106. Clock signals from the clock wire 70 are provided as needed, or desired, to the ports 84. A TDM control signal controls the MUX 106 to put the respective sample onto the data wire 74. Signals are passed from the ports 84 to the MUX 106 through switches 112, 114 controlled by segment window logic 116. In use, the FIFOs 102, 108 collect (or accumulate) data for the respective audio channels 86 and set a flag or status indicator when a predetermined amount of data has been accumulated. Based on when all the related channels have indicated sufficient data accumulation, the segment window logic 116 releases the data to the MUX 106. In this fashion, data for related samples of the audio channels 86 end up in the same segment window on the data wire 74. Thus, the accumulation provides sample alignment at each segment window after initialization. This alignment helps improve audio fidelity.

[0035] On the receive side, both sample and phase alignment may be desirable to help improve audio fidelity. The structure of such receive side components is provided with reference to Figure 7. Audio data is received from the data wire 74 at a demultiplexer (DEMUX) 120, which splits the received signal and provides the split signals 122(x) and 122(y) to respective ports 84(x), 84(y). The ports 84 also receive a clock signal 68 from the clock wire 70. The port 84(x) receives the split signal 122(x) at a deserializer (serial to parallel (S2P)) 124(x) associated with a FIFO 126(x). The FIFO 126(x) provides a status message to error generation logic 128(x) and a count to a comparator 130(x). The comparator 130(x) compares the count to a watermark (or other predefined threshold) 132(x) and outputs a ready signal 134(x) based on the comparison (i.e., if the count exceeds the watermark 132(x), then the ready signal 134 is enabled). The error generation logic 128(x) selectively provides an error signal to an error bus 136. The ready signal 134(x) is provided to a ready bus 138.

[0036] With continued reference to Figure 7, exemplary aspects of the present disclosure perform error handling by evaluating the information on the error bus 136 to see if any of the channels of the multi-channel group has an error condition, such as an underflow or overflow condition. If there is an error condition, an exemplary aspect of the present disclosure halts the channel and substitutes null data until the stream is recovered or other corrective action is taken. When corrective action is taken, the stream is restored or recovered as a group.

[0037] With continued reference to Figure 7, the port 84(x) also includes a grouping register 140(x) that sets a status for first comparator 142(x) and second comparator 144(x). The first comparator 142(x) receives signals from the ready bus 138. The second comparator 144(x) receives signals from the error bus 136. Based the comparison of the comparators 142(x), 144(x), switches 146(x), 148(x) are opened or closed to provide a clock signal from a clock 150 to the FIFO 126(x). Based on whether the clock signal is provided to the FIFO 126(x), data is pulled from the FIFO 126(x) to a signal processing block 152(x) for further processing (e.g., passing to a speaker). Clock signals from the clock 150 are also passed to signal processing blocks 152(x) and 152(y). By clocking the signal processing blocks 152(x) and 152(y) with the same clock signal used with the FIFO 126(x) and FIFO 126(y), sample alignment is preserved and audio fidelity is improved.

[0038] With continued reference to Figure 7, port 84(y) has similar elements performing similar functions, albeit designated with a (y). It should be appreciated that the values of the watermark 132 and the information in the grouping register 140 may be programmed by message control or a programming entity as needed or desired. [0039] Against this backdrop of structure, an exemplary process 160 is provided illustrating how related ports at the first component 82(1) are linked. As illustrated, first component 82(1) is a source component. The process 160 begins with the control system 76 gathering audio data to be sent out through the two (or more) audio channels (block 162). The control system 76 and the DMA 100 prefill the FIFO 102 of port(m) with first channel audio data (block 164). The control system 76 and the DMA 100 then prefill the FIFO 108 of port(n) with second channel audio data (block 166). A manager device (not shown) programs the ports 84 to be of the same channel rate (e.g., 48 kHz) (block 168).

[0040] With continued reference to Figure 8, the manager device activates the channel on both ports 84 at the same time (block 170). A given numbered sample of the two audio channels from the two ports 84 get populated in the same segment window (block 172). The manager determines if this is the end of the data (block 174), with the process repeating as noted or ending and resetting the ports (block 176) if block 174 is answered affirmatively.

[0041] Figure 9 illustrates a process 180 that illustrates an exemplary technique to link the channels on the receive side. That is second component 82(2) is a sink component. In this regard, the process 180 begins with the processor programming the watermark 132(x) and the grouping register 140(x) for the port(x) (block 182). The processor programs with watermark 132(y) and the grouping register 140(y) for the port(y) (block 184). Note that the processor may be in the second component 82(2) or may be in the first component 82(1) and the programming may be effectuated by messages sent across the data wire 74.

[0042] With continues reference to Figure 9, a manager device (not shown) may programs the ports 84(x) and 84(y) with the same channel rate (block 186). The manager device activates the channel on both ports at the same time (block 188). A variety of things may happen. In a first instance, the FIFO 126(x) starts to fill and the ready signal 134(x) is constantly updated as well (block 190). The ready signal 134(x) is passed through the ready bus 138 to the port 84(y). In a second instance, the FIFO 126(y) starts to fill and the ready signal 134(y) is constantly updated as well (block 192). The ready signal 134(y) is passed through the ready bus 138 to the port 84(x). At the same time, the clock 150 is turned on and provided to the ports 84(x) and 84(y) and other signal processing blocks 152(x) and 152(y) (block 194). Once all involved ports signal ready (block 196), the read clock goes through the FIFO 126(x) and 126(y) when both ports 84(x) and 84(y) signal ready (block 198).

[0043] With continued reference to Figure 9, the ports 84(x) and 84(y) continue to get filled with data from the data wire 74 (block 200) and the same numbered sample of both audio channels is pulled from the FIFO 126(x) and 126(y) to the respective signal processing blocks 152(x) and 152(y) at the same time (block 202). The controller checks to see if there is an error signal from any port (block 204). If there is an error, the controller disables the read of both FIFO 126(x) and 126(y) and waits for processor intervention (block 206). If there is no error at block 204, then the controller checks to see if there is an end of the audio data (block 208). If there is an end, the process 180 ends (block 210). Otherwise, the process 180 repeats as indicated.

[0044] While the above discussion contemplates the general concepts behind accumulating data to promote channel alignment of multi-channel audio streams, there are several possible ways that this may be implemented depending on the master/slave nature of the source and sinks. That is, the source may be a master or slave, and the sinks may likewise be masters or slaves. Further, the source may push data or the sink may pull data. Exemplary aspects of these different variations are provided in Figures 10-13.

[0045] In this regard, Figure 10 illustrates an exemplary process 220 where the source is a slave and the master sink pulls data from the slave source. In process 220, the flow rate of the data is determined by the master sink and passed to the transmitting source FIFO register. Thus, after a reset (block 222) where the bus ports are placed in an idle state (block 224), the components monitor whether a bus channel has been enabled (block 226). While this answer is negative, the process 220 repeats as noted. Once the bus channel has been enabled, the process 220 bifurcates.

[0046] With continued reference to Figure 10, initially the bus port is placed in an active state (block 228). The control system 78 determines if the channel is at a segment window boundary (block 230). If the answer to block 230 is no, the process 220 realizes that the bus port is active before port data is ready (block 232). If, however, the answer to block 230 is yes, the control system 78 checks to see if all related channels are at the watermark level (block 234). If the answer to block 234 is no, the process realizes that the bus port is active before port data is ready (block 232). If, however, the answer to block 234 is yes, then the bus port starts up and indicates a data ready state (block 236).

[0047] With continued reference to Figure 10, after realizing that the bus port is active before port data is available (block 232), the control system 78 determines if the transmitter has reached a transmitted time slot (block 238). If the answer to block 238 is no, the process 220 returns to block 230. If, however, the answer to block 238 is yes, the transmitter outputs null data with no presence (block 240) and this null data is provided to the external bus (block 242). Null data is continued while the control system 78 determines if the channel has been disabled (block 244). If the answer to block 244 is no, the process returns to block 230 with any appropriate error handling if the bus starts before the internal data sink (block 246). If however, the answer to block 244 is yes, the port enters a shutdown state (block 248) and the process returns to block 224.

[0048] With continued reference to Figure 10, and returning to block 236, the control system 78 determines if a transmitted timeslot has been reached (block 250). If the answer to block 250 is no, the determination repeats. If there is an error, the error signal is provided to the error bus and an error state is indicated (block 252). From the error state of block 252, the port enters a shutdown state (block 248) and the process returns to block 224. If there is no error at block 250 and the timeslot has been reached, the source outputs the first valid data with presence status set (block 254) and data is sent to the external bus (block 242). The process 220 continues with the determination of whether a transmit timeslot has been reached (block 256). If the answer to block 256 is no, the process 220 repeats, as noted. If the answer to block 256 is that an error has occurred, the process 220 enters an error state (block 252), as previously described. If the answer to block 256 is yes, a transmit timeslot has been reached, the control system 78 determines if there is a master sink data-pull indication on the bus - i.e. a sample request "SRQ" tag set by the sink to complement the data-present "P" bus tag set by the source to indicate valid data for this transmit timeslot (block 258). While SRQ gets set in a pull-protocol by a sink that wants to pull data, in a push protocol, a data strobe ("STR") tag may be set. If there is an error, the error state is asserted (block 252), the port enters a shutdown state (block 248), and the process returns to block 224, as previously described. If the answer to block 258 is no, the source defers or skips data output (block 260). If the answer to block 258 is yes, then valid data is output (block 262). The control system 78 determines if the channel has been disabled (block 264). If the answer to block 264 is no, the process 220 returns to block 256, as noted. If the answer to block 264 is yes, the port enters a shutdown state (block 248), and the process returns to block 224, as previously described.

[0049] With continued reference to Figure 10, and returning to block 226, the source also determines if the internal data source has been enabled (block 266). If the answer to block 266 is no, the process 220 loops, as illustrated. Once the answer to block 266 is yes, the internal source enters a data start-up state (block 268). The source determines if there is an internal data source request to send (block 270). If there is an error at block 270, an error state is asserted (block 252), the port enters a shutdown state (block 248), and the process returns to block 224. If the answer to block 270 is no, the process 220 loops, as illustrated. Once the answer to block 270 is yes, the source determines if all the related channels in the multi-channel group are at, or above, the watermark level (block 272). If an error is detected, an error state is asserted (block 252), the port enters a shutdown state (block 248), and the process returns to block 224. If the answer to block 272 is no, then the data is ignored (block 274). If, however, the answer to block 272 is yes, then the valid data is input and an acknowledgment (ACK) response is generated (block 276). The data is then pulled from the external source (block 278). The control system 78 determines if the channel has been disabled (block 280). If the answer to block 280 is no, then the process loops back to block 270, as noted. If the answer to block 280 is yes, then the port enters a shutdown state (block 248) and the process returns to block 224.

[0050] Figure 11 shows a flow chart of process 290 associated with an exemplary aspect where the slave sink pulls data from the master source. In this regard, the process 290 starts with a reset (block 292) and the bus port entering an idle state (block 294). The process 290 determines if the bus channel has been enabled (block 296). As long as block 296 is negative, the process 290 loops, as indicated. Once the bus channel has been enabled, the bus port enters an active state (block 298). The process determines if the internal data sink has been enabled (block 300). As long as block 300 is negative, the process 290 loops, as indicated. Once the internal data sink has been enabled, the process 290 bifurcates.

[0051] With continued reference to Figure 11, the process 290 continues with the internal sink entering a data start-up state (block 302). The control system 78 determines if all the related channels are at the designated watermark level (block 304). If the answer to block 304 is negative, the internal data sink enters a null data state (block 306). The control system 78 determines if there is an internal data sink request (block 308). If the answer to block 308 is no, the process 290 loops back, as indicated. If the answer to block 308 is yes, there iS an internal data sink request, then null data is output (block 310). This data is provided to the internal sink (312). The control system 78 determines if the channel has been disabled (block 314). If the answer to block 314 is negative, the process loops back, as indicated. If the answer to block 314 is positive, the process 290 continues to a port shutdown state (block 316) and the process 290 returns to the bus port in the idle state (block 294), as indicated. Error handling may occur if the bus starts before the internal data sink starts.

[0052] With continued reference to Figure 11, if the answer to block 304 is yes, the channels are at the watermark level or above, then the data sink enters a start-up state (block 318). The control system 78 determines if there is an internal data sink request (block 320). As long as there is not an internal data sink request, the process 290 loops back, as indicated. If there is an internal data sink request at block 320, the source outputs valid data (block 322). This data is provided to the internal sink (block 324). The control system 78 determines if the channel has been disabled (block 326). If the answer to block 326 is negative, the process 290 loops back to block 320, as indicated. If the answer to block 326 is yes, the channel has been disabled, the port enters a shutdown state (block 316) and loops back to the bus port being in an idle state (block 294), as previously described. If there is an error associated with the internal data sink request at block 320, then the sink enters an error state (block 328) and the port enters a shutdown state (block 316), as previously described.

[0053] With continued reference to Figure 11 and block 300, concurrently with the internal sink entering a data start-up state, the bus port starts up and indicates the bus port is in a data ready state (block 330). The control system 78 determines if the data is at a segment window boundary (block 332). As long as the answer to block 332 is negative (and there is no error), the process 290 loops back, as indicated. If there is an error, the process 290 enters an error state (block 328), as previously discussed. If the answer to block 332 is yes, the data is at a segment window boundary, then the control system 78 determines if all the related channels are at or above the watermark level (block 334). Again, if there is an error, the process 290 enters an error state (block 328), as previously discussed. If the answer to block 334 is negative, the control system 78 determines if a transmit timeslot has been reached (block 336). If there is an error, the process 290 enters an error state (block 328), as previously discussed. If there is no error, then as along as the transmit timeslot has not been reached, the process 290 loops, as indicated. Once the transmit timeslot has been reached, the data is ignored and the bus sample request bus tag bit (SRQ) is not asserted by the sink (block 338). If, however, block 334 is answered affirmatively (i.e., the related channels are at or above the watermark level), then the control system 78 determines if the transmit timeslot has been reached (block 340). If there is an error, the process 290 enters an error state (block 328), as previously discussed. As long as there is no error and the transmit timeslot has not been reached, the process 290 loops, as indicated. Once the transmit timeslot has been reached, the valid data is inputted and the SRQ tag bit is asserted by the sink to acknowledge the data presence from the source (block 342). The data is pulled from the bus (block 344). The control system 78 determines if the channel has been disabled (block 346). If the answer to block 346 is negative, the process 290 returns to block 332 as indicated, otherwise, the port enters a shutdown state (block 316), as previously discussed.

[0054] Figure 12 shows a flow chart of process 350 associated with an exemplary aspect where the slave source pushes data to the master sink. The process 350 begins with a reset (block 352) and the bus port entering an idle state (block 354). The control system 78 determines if the bus channel has been enabled (block 356). As long as the bus channel has not been enabled, the process 350 loops, as indicated. Once the bus channel has been enabled, the process 350 bifurcates. Following one path, the bus port enters an active state (block 358). The control system 78 determines if the data is at a segment boundary window (block 360). If the answer to block 360 is no, then the bus port is active before the port data is available (block 362). The control system 78 determines if a transmit timeslot has been reached (block 364). If the answer to block 364 is no, then the process 350 loops back to block 360, as indicated. If the answer to block 364 is yes, then null data is output with no presence indication (block 366) sent with the data provided to the external bus (block 368). The control system 78 determines if the channel has been disabled (block 370). If the channel has not been disabled, the process 350 returns to block 360, as indicated. If the channel has been disabled, the port enters a shutdown state (block 372) and then returns to block 354, as indicated.

[0055] With continued reference to Figure 12, and returning to block 360, if block 360 is answered affirmatively, the control system 78 determines if all the related channels are at the watermark level (block 374). If the answer to block 374 is negative, then the process 350 goes to block 362, as indicated. If the answer to block 374 is affirmative, the bus port enters a start-up state with data ready (block 376). The control system 78 determines if a transmit timeslot has been reached (block 378). If there is an error, the process 350 enters an error state (block 380) and then the port enters a shutdown state (block 372), as previously discussed. As long as the transmit timeslot has not been reached, the process 350 loops, as indicated. Once the transmit timeslot has been reached, the valid data is output with the presence status set, i.e. bus presence ("P") tag and STR tag set (block 382). The data is sent to the external bus (block 368). The control system 78 determines if the data is at a segment window boundary (block 384). If there is an error, the process 350 enters an error state (block 380) and then the port enters a shutdown state (block 372), as previously discussed. If there is no error, and as long as the segment window boundary has not been reached, the process 350 loops, as indicated. Once the segment window boundary is reached, the control system 78 determines if all the related channels are at, or above, the watermark level (block 386). Again, if there is an error, the process 350 enters an error state (block 380) and then the port enters a shutdown state (block 372), as previously discussed. If there is no error, and the channels are not all above the watermark level, the control system 78 determines if the transmit timeslot has been reached (block 388). If there is an error, the process 350 enters an error state (block 380) and then the port enters a shutdown state (block 372), as previously discussed. If there is no error and the transmit timeslot has not been reached, the process 350 loops, as indicated. Once the transmit timeslot has been reached, the source outputs null data with no presence set, i.e. no bus P tag or STR tag set (block 390). The null data is output to the external bus (block 392). If there is no error and all the related channels are above the watermark threshold, the control system 78 determines if a transmit timeslot has been reached (block 394). If there is an error, the process 350 enters an error state (block 380) and then the port enters a shutdown state (block 372) as previously discussed. If there is no error and the transmit timeslot has been reached, the source outputs valid data with the presence status set, i.e. bus P tag and STR tag set (block 396). The data is output to the external bus (block 392). The control system 78 determines if the channel has been disabled (block 398). If the answer to block 398 is negative, the process 350 returns to block 384, as indicated. If the channel has been disabled, the port enters a shutdown state (block 372), as previously indicated.

[0056] With continued reference to Figure 12, and returning to block 356, concurrently, the control system 78 determines if the internal data source is enabled (block 400). If the answer to block 400 is negative, the process 350 loops as indicated. Once the internal data source is enabled, the internal source enters a data start-up state (block 402). The control system 78 determines if the internal data source has a request to send (block 404). If there is an error, the process 350 enters an error state (block 380) and then the port enters a shutdown state (block 372), as previously discussed. If there is no error and the answer to block 404 is negative, the process 350 loops, as indicated. Once there is a request to send, the internal data source inputs valid data (block 406). The data comes from the internal data source 408. The control system 78 determines if the channel has been disabled (block 410). If the answer to block 410 is negative, the process 350 returns to block 404. If the answer to block 410 is positive, the port enters a shutdown state (block 372), as previously discussed.

[0057] Figure 13 shows a flow chart of process 420 associated with an exemplary aspect where the master source pushes data to the slave sink. The process 420 begins with a reset (block 422) and the bus port entering an idle state (block 424). The control system 78 determines if the bus channel has been enabled (block 426). As long as the bus channel has not been enabled, the process 420 loops, as indicated. Once the bus channel has been enabled, the bus port enters an active state (block 428). The control system 78 determines if the internal data sink has been enabled (block 430). As long as the answer to block 430 is negative, the process 420 loops, as indicated. Once the answer to block 430 is affirmative, the process 420 bifurcates.

[0058] With continued reference to Figure 13, the process 420 continues with the internal sink entering a data start-up state (block 432). The control system 78 determines if all the related channels are at the watermark level (block 434). If the answer to block 434 is negative, the data sink enters a null data state (block 436). The control system 78 determines if there is an internal data sink request (block 438). If the answer to block 438 is negative, the process 420 loops back to block 434, as indicated. If the answer to block 438 is affirmative, null data is output (block 440) to the internal sink (block 442). The control system 78 determines if the channel is disabled (block 444). If the answer to block 444 is no, the process 420 loops back to block 434, as indicated. If the answer to block 444 is yes, then the port enters a shutdown state (block 446) and returns to block 424, as indicated.

[0059] With continued reference to Figure 13, if the answer to block 434 is yes, the data sink enters a start-up state (block 448). The control system 78 determines if there is an internal data sink request (block 450). If there is an error, the process 420 enters an error state (block 452) and then the port enters a shutdown state (block 446), as previously discussed. If there is no error and the answer to block 450 is negative, the process 420 loops back to block 450, as indicated. If there is no error, and the answer to block 450 is affirmative, the control system 78 determines if all the related channels are at, or exceed, the watermark level (block 454). If there is an error, the process 420 enters an error state (block 452) and then the port enters a shutdown state (block 446), as previously discussed. If there is no error and the answer to block 454 is negative, the process 420 skips the output (block 456). If the answer to block 454 is affirmative, then valid data is sent and an ACK response is provided (block 458). The data is sent to the internal sink (block 460). The control system 78 determines if the channel has been disabled (block 462). If the answer to block 462 is negative, the process 420 loops back to block 450, as indicated. If the answer to block 462 is affirmative, the port enters a shutdown state (block 446), as previously indicated.

[0060] With continued reference to Figure 13, after block 430, the process 420 also causes the bus port to start-up and enter a data ready state (block 464). The control system 78 determines if a transmit timeslot has been reached (block 466). If there is an error, the process 420 enters an error state (block 452) and then the port enters a shutdown state (block 446), as previously discussed. If there is no error and the answer to block 466 is negative, the process 420 loops, as indicated. If the answer to block 466 is affirmative, a transmit timeslot has been reached, and the data source then will assert a valid sample request strobe STR tag and associated data-present P tag to indicate there is valid data for this transmit timeslot (block 468). If there is an error, the process 420 enters an error state (block 452) and then the port enters a shutdown state (block 446), as previously discussed. If there is no error and the answer to block 468 is negative, the data input slot is skipped (block 470). If the answer to block 468 is affirmative, then valid data is inputted (block 472). The data is received from the bus source data (block 474). The control system 78 determines if the channel has been disabled (block 476). If the channel has not been disabled, the process 420 loops back to block 466, as indicated. If the channel has been disabled, the port enters a shut down state (block 446), as previously discussed.

[0061] Note that while Figures 10-13 are presented from what the slave control system 78 does, it should be appreciated that exemplary aspects of the present disclosure extend these concepts to the master control system 76. Further, the concept of using the watermark to define when to start-up is present on both the slave and the master. The concept of using a watermark to assert presence or SRQ/STR on a sample by sample basis assumes proximity to an audio time-reference, which is common on the slave side, but can also be found on the master side.

[0062] As alluded to above, the multi-channel audio alignment schemes according to aspects disclosed herein may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a computer, a portable computer, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, and a portable digital video player. While any such device may benefit from aspects of the present disclosure, the present disclosure is particularly well suited for use with devices that operate according to the SLIMbus protocol. [0063] Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium and executed by a processor or other processing device, or combinations of both. The devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0064] The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0065] The aspects disclosed herein may be embodied in hardware and in instructions that are stored in hardware, and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

[0066] It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flow chart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0067] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.