Title:
MULTI-CHANNEL CLOCK GENERATOR
Document Type and Number:
WIPO Patent Application WO/2022/215503
Kind Code:
A1
Abstract:
A clock generator 100 is provided with a plurality, N, of PLL circuits 200. A phase comparison circuit 210 generates a control signal S1 corresponding to a phase difference between a first clock CLKa input to a first terminal T1, and a second clock CLKb input to a second terminal T2. A loop filter 220 receives a control signal S1 and allows a predetermined frequency band to pass therethrough. An oscillator 230 oscillates at a frequency corresponding to a control signal S2 that has passed through the loop filter 220. A frequency divider 240 divides an output clock of the oscillator 230, and outputs a clock signal CLKc obtained by the dividing, from a third terminal T3. A common reference clock is input to the first terminals T1 of the N PLL circuits 200. The third terminal T3 of an i-th (1≦i≦N) PLL circuit 200_i is connected to the second terminal T2 of an (i+1)th PLL circuit 200_(i+1).
Inventors:
ASAMI KOJI (JP)
Application Number:
PCT/JP2022/012881
Publication Date:
October 13, 2022
Filing Date:
March 18, 2022
Export Citation:
Assignee:
ADVANTEST CORP (JP)
International Classes:
H03L7/07; H03L7/22
Foreign References:
| JP2001036404A | 2001-02-09 | |||
| JP2015046799A | 2015-03-12 | |||
| JP2004072714A | 2004-03-04 | |||
| JP2011061573A | 2011-03-24 | |||
| JPS63281520A | 1988-11-18 |
Attorney, Agent or Firm:
MORISHITA Sakaki (JP)
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