MULTI-CORE PROCESSOR SYSTEM, CONTROL PROGRAM AND CONTROL METHOD

Title:

MULTI-CORE PROCESSOR SYSTEM, CONTROL PROGRAM AND CONTROL METHOD

Document Type and Number:

WIPO Patent Application WO/2012/014287

Kind Code:

A1

Abstract:

Another CPU detects a match between an instruction address for a task (B) held in a table to access a shared memory and the program counter for another CPU, as a preprocessing of the access. Another CPU determines whether or not the value of an access flag is 1 by checking the access flag. Given that the value of the access flag is 0, another CPU determines that one CPU is accessing the shared memory and another CPU switches from the task B to the task C in a ready queue (121).

Inventors:

KURIHARA, Koji (1-1 Kamikodanaka 4-chome, Nakahara-ku, Kawasaki-sh, Kanagawa 88, 〒2118588, JP)
栗原　康志 (〒88 神奈川県川崎市中原区上小田中４丁目１番１号　富士通株式会社内 Kanagawa, 〒2118588, JP)
YAMASHITA, Koichiro (1-1 Kamikodanaka 4-chome, Nakahara-ku, Kawasaki-sh, Kanagawa 88, 〒2118588, JP)
山下　浩一郎 (〒88 神奈川県川崎市中原区上小田中４丁目１番１号　富士通株式会社内 Kanagawa, 〒2118588, JP)

Application Number:

JP2010/062629

Publication Date:

February 02, 2012

Filing Date:

July 27, 2010

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Assignee:

FUJITSU LIMITED (1-1 Kamikodanaka 4-chome, Nakahara-ku Kawasaki-sh, Kanagawa 88, 〒2118588, JP)
富士通株式会社 (〒88 神奈川県川崎市中原区上小田中４丁目１番１号 Kanagawa, 〒2118588, JP)
KURIHARA, Koji (1-1 Kamikodanaka 4-chome, Nakahara-ku, Kawasaki-sh, Kanagawa 88, 〒2118588, JP)
栗原　康志 (〒88 神奈川県川崎市中原区上小田中４丁目１番１号　富士通株式会社内 Kanagawa, 〒2118588, JP)
YAMASHITA, Koichiro (1-1 Kamikodanaka 4-chome, Nakahara-ku, Kawasaki-sh, Kanagawa 88, 〒2118588, JP)

International Classes:

G06F9/52; G06F9/50

Attorney, Agent or Firm:

SAKAI, Akinori (A. SAKAI & ASSOCIATES, 20F Kasumigaseki Building, 2-5, Kasumigaseki 3-chome, Chiyoda-k, Tokyo 20, 〒1006020, JP)

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Claims:

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