Technical Field

[0001] This disclosure relates generally to the field of semiconductor devices, and more specifically, to transistor devices/arrangements having multiple diffusion regions electrically connected to a single drain terminal.

Background

[0002] Electrostatic discharge (ESD) refers to a phenomenon of a sudden flow of electricity between two electrically charged objects. ESD presents a challenge in integrated circuits because solid state electronics components, e.g. transistors, used in such circuits can suffer permanent damage when subjected to high voltages. ESD can affect transistors during manufacturing/testing, transit (e.g. shipping, handling, and storage), as well as during normal operation and, therefore, measures for protecting transistors from ESD in all of these stages are needed.

Brief Description of the Drawings

[0003] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

[0004] FIGS. 1A-1B are cross-sectional views of an exemplary conventional transistor arrangement with multiple FinFETs on a single fin.

[0005] FIG. 2 is a cross-sectional side view of an exemplary multi-drain transistor arrangement, in accordance with various embodiments of the present disclosure.

[0006] FIG. 3 is a schematic illustration of an exemplary driver circuit with an exemplary multi-drain transistor arrangement, in accordance with various embodiments of the present disclosure.

[0007] FIGS. 4A-4C are top views of exemplary conventional transistor arrangements and multi- drain transistor arrangements in accordance with various embodiments of the present disclosure.

[0008] FIG. 5 is a perspective view of an exemplary FinFET to be used as a building block in providing a multi-drain transistor arrangement, in accordance with various embodiments of the present disclosure.

[0009] FIG. 6 is a perspective view of an exemplary all-around gate transistor to be used as a building block in providing a multi-drain transistor arrangement, in accordance with various embodiments of the present disclosure.

[0010] FIG. 7 is a flow diagram of an exemplary method of manufacturing a multi-drain transistor arrangement, in accordance with various embodiments of the present disclosure. [0011] FIGS. 8A and 8B are top views of a wafer and dies that may include one or more multi-drain transistor arrangements in accordance with any of the embodiments disclosed herein.

[0012] FIG. 9 is a cross-sectional side view of an integrated circuit (IC) device that may include one or more multi-drain transistor arrangements in accordance with any of the embodiments disclosed herein.

[0013] FIG. 10 is a cross-sectional side view of an IC device assembly that may include one or more multi-drain transistor arrangements in accordance with any of the embodiments disclosed herein.

[0014] FIG. 11 is a block diagram of an example computing device that may include one or more multi-drain transistor arrangements in accordance with any of the embodiments disclosed herein.

Detailed Description

[0015] Disclosed herein are transistor arrangements having multiple diffusion regions electrically connected to a single drain terminal, referred to as "multi-drain transistor" arrangements, and related methods and devices. For example, in some embodiments, a multi-drain transistor arrangement may include one or more semiconductor materials in which a channel of a transistor will be formed during operation (these one or more semiconductor materials referred to in the following as a "channel material"), a first gate electrode and a second gate electrode provided over different portions of the channel material, and a first drain electrode and a second drain electrode provided over different diffusion regions but connected to a single drain terminal. As used herein, the term "diffusion region" (also commonly referred to as "source/drain (S/D) region") refers to a region of a semiconductor material having a dopant concentration that is higher than that in the channel of a transistor. As described in greater detail below, providing multiple diffusion regions connected to a single drain terminal advantageously allows improving ESD robustness of the transistor arrangements.

[0016] Multi-drain transistor arrangements as described herein may be implemented in one or more components associated with an integrated circuit (IC) or/and between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on an IC, provided as an integral part of an IC, or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a computer.

[0017] For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details or/and that the present disclosure may be practiced with only some of the described aspects. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

[0018] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which are shown, by way of illustration, embodiments that may be practiced. The accompanying drawings are not necessarily drawn to scale. For example, to clarify various layers, structures, and regions, the thickness of some layers may be enlarged. Furthermore, while drawings illustrating various structures/assemblies of exemplary devices may be drawn with precise right angles and straight lines, real world process limitations may prevent implementations of devices exactly as shown. Therefore, it is understood that such drawings revised to reflect example real world process limitations, in that the features may not have precise right angles and straight lines, are within the scope of the present disclosure. Drawings revised in this manner may be more representative of real world structure/assemblies as may be seen on images using various characterization tools, such as e.g. scanning electron microscopy (SEM) or transmission electron microscopy (TEM). In addition, the various structures/assemblies of the present drawings may further include possible processing defects, such as e.g. the rounding of corners, the drooping of the layers/lines, unintentional gaps and/or discontinuities, unintentionally uneven surfaces and volumes, etc., although these possible processing defects may not be specifically shown in the drawings. It is to be understood that other embodiments may be utilized and structural or logical changes to the drawings and descriptions may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0019] Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment.

Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

[0020] For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on." [0021] The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. Furthermore, stating in the present disclosure that any part (e.g. a layer, film, area, or plate) is in any way positioned on or over (e.g. positioned on/over, provided on/over, located on/over, disposed on/over, formed on/over, etc.) another part means that the referenced part is either in contact with the other part, or that the referenced part is above the other part with one or more intermediate part(s) located

therebetween. On the other hand, stating that any part is in contact with another part means that there is no intermediate part between the two parts.

[0022] The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 20% of a target value. Unless otherwise specified, the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0023] In the following detailed description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. In some examples, as used herein, a "high-k dielectric" refers to a material having a higher dielectric constant than silicon oxide, while the terms "oxide," "carbide," "nitride," etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc. In another example, the term "connected" means a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term "coupled" means either a direct electrical or magnetic connection between the things that are connected or an indirect connection through one or more passive or active intermediary devices. The term "circuit" means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function.

[0024] For purposes of illustrating multi-drain transistor arrangements as proposed herein, it is important to understand the phenomena that may come into play in a typical transistor. The following foundational information may be viewed as a basis from which the present disclosure may be properly explained. Such information is offered for purposes of explanation only and, accordingly, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications.

[0025] The performance of electronic components may depend on a number of factors. One factor is how protected a component is from the undesirable effects of electrostatic discharge. For example, ESD can be responsible for providing the voltage high enough to trigger Gate Induced Drain Leakage (GIDL) and cause Zener breakdown of a transistor device. This problem is particularly prominent for otherwise promising high-voltage metal-oxide-semiconductor field-effect transistors (MOSFETs) with non-planar architecture, such as e.g. tri-gate/FinFETs, where, despite years of intensive investigations and design optimizations, conventional ESD protection concepts still have room for improvement due to weak ESD robustness of the transistors both on the single-fin and on the multi-fin/array levels, hindering scaling of these devices.

[0026] As is well-known, transistors can have planar or non-planar architecture. MOSFETs with non-planar architecture, such as e.g. tri-gate/FinFET and all-around gate transistors, have recently been extensively explored as more advantageous alternatives to transistors with planar architecture.

[0027] FinFETs refer to transistors having a non-planar architecture where a fin, formed of one or more semiconductor materials, extends away from a base. FinFETs are sometimes referred to as "tri-gate transistors," where the name "tri-gate" originates from the fact that, in use, such a transistor may form conducting channels on three "sides" of the fin. FinFETs potentially improve performance relative to single-gate transistors and double-gate transistors.

[0028] One type of ESD protection concept typically employed with FinFETs includes using bipolar functionality, e.g. allowing high ESD currents to flow in the substrate region. While this can be an efficient ESD protection concept, current crowding effect can compromise this functionality.

Ballasting resistors may be used to essentially balance the ESD currents in the bipolar function. One problem with such use of ballasting resistors is that the resistors have to be quite large to be effective, leading to costly layout consumption and to increased power consumption due to the additional resistance in the signal path. Another problem is that, in contrast to self-protecting ESD concepts in planar CMOS technologies, the use of ballasting resistors formed by extended drain regions is not compatible with FinFETs.

[0029] Thick-oxide transistors, ubiquitously used to implement I/O connections for voltages of about 1.8 Volts (V) and higher, feature gate lengths much longer than those used for logic devices. The name "thick-oxide" refers to the fact that, typically, a thickness of a gate dielectric (typically an oxide) in a gate stack of such a transistor is large compared to that used in a transistor that may implement a logic device. For example, a typical gate dielectric thickness of a thick-oxide transistor is above 2 nanometers (nm), e.g. between 3 and 10 nm, while a typical gate dielectric thickness of a logic device transistor is between 0.4 and 5 nm, e.g. between 0.4 and 3 nm. Thicker gate dielectrics and longer gate lengths of thick-oxide transistors have negative effects on the ESD performance of such devices due to the poorer properties of the inherent parasitic bipolar transistors having lower current gain, higher clamping voltage, and lower secondary breakdown currents.

[0030] While multi-drain transistor arrangement concepts proposed herein may be implemented in both planar and non-planar transistor architectures, they may be particularly advantageous for transistors having non-planar architectures, such as e.g. tri-gate and all-around gate transistors, because providing self-protection from ESD in such devices is not an easy task due to their small dimensions and complicated architecture. Furthermore, the concepts proposed herein are particularly advantageous for thick-oxide non-planar FET transistors, such as e.g. thick-oxide FinFET transistors typically used in I/O drivers.

[0031] In the following, multi-drain transistor arrangement concepts proposed herein are explained by comparing an exemplary conventional transistor arrangement with multiple FinFETs on a single fin, shown in FIG. 1A, with an exemplary multi-drain transistor arrangement where diffusion regions of multiple FinFETs provided on a single fin are electrically connected to a single drain terminal, shown in FIG. 2.

[0032] An example of a FinFET is shown in FIGs. 1A and IB, illustrating two different cross-sectional views of an exemplary conventional transistor arrangement 100 with multiple FinFETs on a single fin.

[0033] FIG. 1A illustrates a side view of the transistor arrangement 100, with a cross-section taken along the length of the fin, while FIG. IB illustrates a front view of the transistor arrangement 100 with a cross-section taken across one of the gates of the transistor arrangement 100 - i.e. FIG. IB illustrates a cross-sectional view with a cross-section taken along a plane AA shown in FIG. 1A, while FIG. 1A illustrates a cross-sectional view with a cross-section taken along a plane BB shown in FIG. IB (FIG. 1A is also a cross-sectional view with a cross-section taken along a plane CC shown in FIG. 5 that illustrates an exemplary perspective view of one FinFET, while FIG. IB is a cross-sectional view with a cross-section taken along a plane DD shown in FIG. 5).

[0034] As shown in FIGS. 1A and IB, the transistor arrangement 100 includes a substrate 102 over which a channel material 104 is provided. The channel material 104 is formed as a fin 120 extending away from the substrate (the fin 120 is not specifically shown in FIG. 1A because FIG. 1 illustrates a cross-sectional view with a cross-section taken along the length of the fin 120, but can be better seen in FIG. IB). A first gate stack 112-1 including a gate electrode material 106 and a gate dielectric 108, typically a high-k dielectric material, wraps around the upper portion of the fin 120, as can be seen in FIG. IB, with the active region of the channel material 104 (i.e. the region where the transistor channel is formed during operation) corresponding to the portion of the fin 120 wrapped by the gate stack. In particular, as shown in FIG. IB, the high-k dielectric 108 may wrap around the upper portion of the fin 120 and the gate electrode 106 may wrap around the high-k dielectric 108. As also shown in FIG. IB, sides of a lower portion of the fin 120, i.e. a portion that is closest to the substrate 102, are enclosed by a dielectric material 110, typically an oxide, commonly referred to as a "shallow trench isolation" (STI). A portion of a fin, e.g. the fin 120, that is enclosed by an STI is typically referred to as a "sub-fin" while a portion of a fin over which a gate stack wraps around is typically referred to as a "channel" or a "channel portion." In general, a gate stack includes a stack of one or more gate electrode metals and a stack of one or more gate dielectrics and is provided over the top and sides of the upper portion of the fin (i.e. the portion above the STI), thus wrapping around the upper portion of the fin and forming a three-sided gate of a tri-gate transistor.

[0035] FIG. 1A further illustrates a drain electrode 114-1 and a source electrode 116-1 formed of one or more electrically conductive materials 110. The drain electrode 114-1 provides electrical connectivity between a drain region 124-1 and a drain terminal/contact Dl, while the source electrode 116-1 provides electrical connectivity between a source region 126-1 and a source terminal/contact SI, as shown in FIG. 1A. Thus, the drain electrode 114-1 is electrically connected to the drain region 124-1 on one side and to the drain terminal Dl on the other. Similarly, the source electrode 116-1 is electrically connected to the source region 126-1 on one side and to the source terminal SI on the other. As is well-known, source/drain (S/D) regions of a transistor (also sometimes interchangeably referred to as "diffusion regions") are regions of doped semiconductors, e.g. regions of doped channel material, so as to supply charge carriers for the transistor channel. Often, the S/D regions are highly doped, e.g. with dopant concentrations of about 1-10 ²¹ dopants per cubic centimeter (cm ³ ), in order to advantageously form Ohmic contacts with the respective S/D electrodes, although these regions may also have lower dopant concentrations and may form Schottky contacts in some implementations. Irrespective of the exact doping levels, the S/D regions 126-1 and 124-1 are the regions having dopant concentration higher than in other regions, e.g. higher than a dopant concentration in a region between the source region 126-1 and the drain region 124-1, and, therefore, may be referred to as "highly doped" (HD) regions. Reference numeral 122 shown in FIG. 1A illustrates a channel region of the transistor arrangement 100, while reference numeral 132 shown in FIG. 1A illustrates a subfin region.

[0036] The S/D regions 126-1 and 124-1, the S/D electrodes 116-1 and 114-1, and the gate stack 112-1 may be viewed to form a first FinFET provided over a first portion of the fin 120. A substantially identical FinFET may be provided over a second portion of the fin 120 - as shown in FIG. 1A with a second FinFET on the left side of the illustration of FIG. 1A, including S/D regions 126-2 and 124-2, S/D electrodes 116-2 and 114-2, and a gate stack 112-2. The S/D regions 126-2 and 124- 2, the S/D electrodes 116-2 and 114-2, and the gate stack 112-2 of the second FinFET shown in FIG. 1A are substantially analogous to the S/D regions 126-1 and 124-1, the S/D electrodes 116-1 and 114-1, and the gate stack 112-1 of the first FinFET shown in FIG. 1A, and, therefore, in the interests of brevity, their description is not repeated. The drain electrode 114-2 provides electrical connectivity between a drain region 124-2 and a drain terminal D2, while the source electrode 116-2 provides electrical connectivity between a source region 126-2 and a source terminal S2, as shown in FIG. 1A for the second FinFET.

[0037] Implementations when multiple transistors are provided along a single fin as shown in FIG. 1A are common. Depending on a particular design, additional components may be present in a multi-FinFET implementation such as the one shown in FIG. 1A, such as e.g. various means for providing electrical separation between the adjacent S/D regions or the adjacent S/D electrodes of the different transistors on a single fin, such additional components not shown in FIG. 1A. However, for all of such implementations, what is desirable, from the manufacturing perspective, is to keep the same the gate pitch between the gates of different transistors, shown in FIG. 1A as a distance dgg, which is indicative of a center-to-center distance between the immediately adjacent gates and of a poly-pitch distance, which are critical design parameters. Transistor arrangements proposed herein allow providing ESD self-protection while, at the same time, respecting this condition. In particular, transistor arrangements described herein may be implemented with multiple gate electrodes on a continuous channel material as implemented conventionally, including maintaining the gate pitch, but connecting multiple diffusion (drain) regions to a single drain terminal.

Connecting multiple diffusion regions to a single drain terminal effectively extends the drain region for a transistor, improving the ESD robustness of the transistor. Namely, such multiple diffusion regions allow the ESD current to enter through various drain electrodes connected to the ESD exposed drain terminal, which may be connected to a pad or any other type of electrical connection, thereby distributing the ESD current and mitigating the problems of current crowding and local overheating. An example of a transistor arrangement having multiple diffusion regions connected to a single drain terminal is shown in FIG. 2.

[0038] FIG. 2 is a cross-sectional side view of an exemplary FinFET multi-drain transistor arrangement 200, in accordance with various embodiments of the present disclosure. The view of FIG. 2 is similar to the view of FIG. 1A. For example, similar to the transistor arrangement 100, the transistor arrangement 200 includes a substrate 202 over which a channel material 204 is provided.

[0039] The substrate 202 may be any structure on which one or more multi-drain transistor arrangements as described herein can be disposed. In some embodiments, the substrate 202 may include a semiconductor, such as silicon. In some embodiments, the substrate 202 may include an insulating layer, such as an oxide isolation layer, e.g. to electrically isolate the semiconductor material of the substrate 202 from the S/D regions and the channel material 204, and thereby mitigate the likelihood that conductive pathways will form between the source region and the drain region through the substrate 202. Examples of ILDs that may be included in/on a substrate 202 in some embodiments may include silicon oxide, silicon nitride, aluminum oxide, and/or silicon oxynitride.

[0040] The channel material 204 may be composed of semiconductor material systems including, for example, N-type or P-type materials systems. In some embodiments, the channel material 204 may be formed of a monocrystalline semiconductor. In some embodiments, the channel material 204 may be formed of a compound semiconductor with a first sub-lattice of at least one element from group III of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of at least one element of group V of the periodic table (e.g., P, As, Sb). In some embodiments, the channel material 204 may be a binary, ternary, or quaternary lll-V compound semiconductor that is an alloy of two, three, or even four elements from groups III and V of the periodic table, including boron, aluminum, indium, gallium, nitrogen, arsenic, phosphorus, antimony, and bismuth.

[0041] For exemplary P-type transistor embodiments, the channel material 204 may

advantageously be a group IV material having a high hole mobility, such as, but not limited to, Ge or a Ge-rich SiGe alloy. For some exemplary embodiments, the channel material 204 may have a Ge content between 0.6 and 0.9, and advantageously is at least 0.7.

[0042] For exemplary N-type transistor embodiments, the channel material 204 may

advantageously be a lll-V material having a high electron mobility, such as, but not limited to InGaAs, InP, InSb, and InAs. For some such embodiments, the channel material 204 may be a ternary lll-V alloy, such as InGaAs or GaAsSb. For some ln _x Gai- _x As fin embodiments, In content in the channel material 204 may be between 0.6 and 0.9, and advantageously at least 0.7 (e.g., lno.7Gao.3As).

[0043] In some embodiments, the channel material 204 may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide.

[0044] In some embodiments, the channel material 204 may have a thickness e.g. between about 5 and 10000 nanometers, including all values and ranges therein. In some implementations, the channel material 204 may be viewed as a part of the substrate 202, or as a part of the crystalline semiconductor upper part of the substrate 202.

[0045] In some embodiments, the channel material 204 is an intrinsic lll-V or IV semiconductor material or alloy, not intentionally doped with any electrically active impurity. In alternate embodiments, nominal impurity dopant levels may be present within the channel material 204, for example to set a threshold voltage Vt, or to provide HALO pocket implants, etc. In such impurity- doped embodiments however, impurity dopant level within the channel material 204 may be relatively low, for example below about 10 ¹⁵ cm ³ , and advantageously below 10 ¹³ cm ³ .

[0046] In the exemplary device shown in FIG. 2, the channel material 204 is formed as a fin 220 extending away from the substrate (a view of the transistor arrangement 200 with the fin 220 in a cross-section across the fin in the right FinFET shown in FIG. 2 would be similar to that shown in FIG. IB, not specifically shown in FIG. 2). Some further considerations with respect to the fin are described below, with reference to FIG. 5.

[0047] As further shown in FIG. 2, the upper portion of the fin is wrapped by a first gate stack 212-1 and a second gate stack 212-2, the two gate stacks provided over different regions of the channel material 204. Each of the gate stacks 212 includes a gate electrode material 206 and a gate dielectric 208, with the active region of the channel material 204 corresponding to the portion of the fin wrapped by the respective gate stack. In particular, in each of the gate stacks 212, the gate dielectric 208 may wrap around the upper portion of the fin and the gate electrode material 206 may wrap around the gate dielectric 208.

[0048] The gate electrode material 206 may include at least one P-type work function metal or N- type work function metal, depending on whether the transistor arrangement 200 is a P-type metal oxide semiconductor (PMOS) transistor or an N-type metal oxide semiconductor (NMOS) transistor (P-type work function metal used as the gate electrode material 206 when the transistor arrangement 200 includes PMOS transistors and N-type work function metal used as the gate electrode material 206 when the transistor arrangement 200 includes NMOS transistors). For PMOS transistors, metals that may be used for the gate electrode material 206 may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For NMOS transistors, metals that may be used for the gate electrode material 206 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode material 206 may include of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further layers may be included next to the gate electrode material 206 for other purposes, such as to act as a diffusion barrier layer or/and an adhesion layer, not specifically shown in FIG. 2.

[0049] In some embodiments, the gate dielectric 208 may be a high-k dielectric (i.e. a dielectric material that has a higher dielectric constant (k) than silicon dioxide) including elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric 208 may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0050] In some embodiments, an annealing process may be carried out on the gate dielectric 208 during manufacture of the transistor arrangement 200 to improve the quality of the gate dielectric 208. The gate dielectric 208 may have a thickness, a dimension measured in the vertical direction in the view of FIG. 2, that may, in some embodiments, be between about 0.4 and 5 nm, including all values and ranges therein (e.g., between about 0.5 and 3 nm, or between 1 and 2 nm), or between about 2 and 10 nm, including all values and ranges therein (e.g., between about 2 and 7 nm, or between 3 and 5 nm).

[0051] In some embodiments, each of the gate stacks 212 may be surrounded by a gate spacer, not shown in FIG. 2, configured to provide separation between the gates of different transistors. Such a gate spacer is typically made of a low-k dielectric material (i.e. a dielectric material that has a lower dielectric constant (k) than silicon dioxide). Examples of low-k materials that may be used in such a dielectric spacer may include, but are not limited to, fluorine-doped silicon dioxide, carbon-doped silicon dioxide, spin-on organic polymeric dielectrics such as e.g.

polyimide, polynorbornenes, benzocyclobutene, and polytetrafluoroethylene (PTFE), or spin-on silicon based polymeric dielectric such as e.g. hydrogen silsesquioxane (HSQ) and

methylsilsesquioxane (MSQ)). Other examples of low-k materials that may be used in a dielectric spacer include various porous dielectric materials, such as for example porous silicon dioxide or porous carbon-doped silicon dioxide, where large voids or pores are created in a dielectric in order to reduce the overall dielectric constant of the layer, since voids can have a dielectric constant of nearly 1.

[0052] Similar to the transistor arrangement 100 shown in FIGS. 1A and IB described above, the lower portion of the fin in the transistor arrangement 200, i.e. sub-fin portion 232, is surrounded by a dielectric material, typically an oxide, referred to as STI (not specifically shown in the cross- sectional side view of FIG. 2). The dielectric material of the STI layer may e.g. include any of the high-k dielectric materials described herein.

[0053] The fin of the transistor arrangement 200 further includes S/D diffusion regions on either side of each of the gate stacks 212-1 and 212-2. However, the two diffusion regions of the different gate stacks which are closest to one another are merged into a continuous diffusion region 228. This is illustrated in FIG. 2 by: 1) showing individual S/D diffusion regions of the first transistor as a source region 226-1 and a drain region 224-1, similar to the source region 126-1 and the drain region 124-1 shown in FIG. 1A; 2) showing individual S/D diffusion regions of the second transistor as a source region 226-2 and a drain region 224-2, similar to the source region 126-2 and the drain region 124-2 shown in FIG. 1A; and 3) showing that the source region 226-2 of the second FinFET is merged with the drain region 224-1 of the first FinFET into a single common diffusion region 228. A common electrode 214-1 is provided over the common diffusion region 228, providing electrical connectivity between the common diffusion region 228 and a first drain terminal/contact Dl. An electrode 214-2 provided on the opposite side of the gate stack 212-2 provides electrical connectivity between the diffusion region 224-2 of the second transistor and the first drain terminal/contact Dl, thus both the diffusion region 224-2 and the common diffusion region 228 are electrically connected to a single drain terminal Dl. An electrode 216-2 provided on the opposite side of the gate stack 212-1 provides electrical connectivity between the diffusion region 226-1 of the first transistor and the first source terminal/contact SI.

[0054] It should be noted that while references may be made to the first and second transistors in the transistor arrangement 200 or other embodiments described herein, what is referred to as the "second transistor" is not a fully functioning transistor in a conventional meaning of the term because its' diffusion regions on either side of its' gate stack 212-2 are not connected to the source and drain terminals, respectively, and no bias needs to be applied to its' gate during operation. Instead, the diffusion regions on either side of the gate stack 212-2 are connected to the single drain terminal Dl, effectively making the "second transistor" short circuited, and the gate 212-2 may be left electrically floating (i.e. not connected to any bias). Similarly, reference to the diffusion region 226-2 as the "source region" and to the diffusion region 224-2 as the "drain region" is only to draw parallels with the arrangement shown in FIG. 1A where two separate FinFETs are provided along a single fin, but, in context of the multi-drain transistor arrangements described herein the source region 226-2 and the drain region 224-2 are actually both drain regions because they are both connected to the drain terminal Dl. Thus, in general, the "source region" 226-2 and the "drain region" 224-2 may be referred to as "diffusion regions" or "drain regions" of the first transistor, while the "second transistor" may be referred to as a "dummy transistor."

[0055] Merging multiple diffusion regions together (e.g. merging the diffusion region 226-2 and the diffusion region 224-1 into a single diffusion region 228) and connecting such a common diffusion region to a drain terminal together with a diffusion region on the other side of the gate stack 212-2 (i.e. the diffusion region 224-2) increases the effective drain region for the first transistor (i.e. the transistor having the gate stack 212-1 and the source electrode 216-1 connected to the source terminal SI). In other words, the transistor arrangement 200 includes a hard electrical connection of multiple diffusion regions configured as one common drain terminal Dl. In this manner, the transistor arrangement 200 has improved ESD protection, while being fully compliant to industrywide technologies and related design rules.

[0056] While an improvement in the ESD protection for the transistor arrangement 200 has been shown from simulations, such an improvement is unexpected because it is not apparent from regular MOS transistor properties (MOS channel in active fin region) and also not expected from conventional bipolar junction understanding. At the moment, the improved ESD protection of the transistor arrangement 200 may be explained by stimulating vertical bipolar junction transistor (BJT) action from the drain region into the sub-fin region beneath caused by connecting multiple diffusion regions to a single drain terminal, as described above. The improvement is particularly prominent for thick-oxide (i.e. long gate) transistor devices.

[0057] Each of the common diffusion region 228, the "drain" diffusion region 224-2 and the source diffusion region 226-1 are formed within the channel material 204 and, in some embodiments, may include one or more highly doped crystalline semiconductor materials, compared to the channel material 204. For example, in various embodiments, dopant levels within these diffusion regions may be at least 1-10 ¹⁹ cm ³ , e.g. between about 1-10 ¹⁹ and 10-10 ²¹ cm ³ . While diffusion regions having doping concentrations varying from about 1-10 ¹⁹ cm ^"3 to solid solubility values, i.e. above 1-10 ²¹ cm ^"3 would typically advantageously form Ohmic contacts with their respective source/drain electrode metals, embodiments of the present disclosure may also be implemented for at least some of the diffusion regions having lower doping concentrations, i.e. when these diffusion regions form Schottky contacts with their respective electrode(s), e.g. doping concentrations between about 5-10 ¹⁶ and 1-10 ¹⁹ cm ³ . Irrespective of the exact dopant levels, the diffusion regions 228, 224-2 and 226-1 all have the same type of dopants - e.g. N-type dopants for NMOS transistor applications or P- type dopants for PMOS transistor applications, while the channel material 204 is a semiconductor material of an opposite type - e.g., for NMOS transistor applications, the channel material is a P-type semiconductor, while, for PMOS transistor applications, the channel material is an N-type semiconductor.

[0058] Manufacturing the common diffusion region 228 and the first and second diffusion regions 224-2 and 226-1 may be achieved by e.g. using an appropriate mask or/and an appropriate spacer.

[0059] In various embodiments, the diffusion regions 228, 224-2 and 226-1 may be formed within the channel material 204 using either an implantation/diffusion process or a deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the channel material 204 to form the highly doped regions. An annealing process that activates the dopants and causes them to diffuse farther into the channel material 204 may follow the ion implantation process. In the latter process, an epitaxial deposition process may provide material that is used to fabricate the highly doped regions. In some implementations, the highly doped regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the highly doped regions may be formed using one or more alternate semiconductor materials such as germanium or a group ll l-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the highly doped regions. In some embodiments, an etch process may be performed before the epitaxial deposition to create recesses in the channel material 204 in which the material for the highly doped regions is deposited.

[0060] A length of the common diffusion region 228, indicated in FIG. 2 as a dimension d _C d (where "cd" stands for common drain), would depend on the gate pitch d _gg and on the gate length L _g of the first and second gates. In some embodiments, the length d _C d may be between about 2 and 50 nm, including all values and ranges therein, e.g. between 4 and 20 nm or between 5 and 15 nm.

[0061] While the embodiments described above are described with reference to the distances d _C d being between about 2 and 50 nm, this distance may be in different smaller ranges depending e.g. on whether a device in which such multi-drain transistor arrangements are implemented is intended for high-voltage applications such as e.g. I/O devices/drivers or low-voltage applications such as e.g. logic gates. As is known, gate lengths and, correspondingly, poly pitch distances used in the low- voltage applications are smaller than those used in high-voltage applications. For example, in some embodiments, e.g. those suitable for low-voltage applications, a gate length L _g may be between about 3 and 50 nm, including all values and ranges therein, e.g. between 5 and 20 nm, or between 7 and 10 nm. In other embodiments, e.g. those suitable for low-voltage applications, a gate length L _g may be above 50 nm, e.g. between about 50 and 1000 nm (or even higher), including all values and ranges therein, e.g. between 75 and 200 nm, or between 50 and 100 nm. Thus, in some

embodiments, ranges for the distance d _C d according to various embodiments of the present disclosure may be expressed in terms of poly-pitch distance (i.e. a dimension indicative of the distance between the outer edges of two adjacent poly gates) or in terms of gate pitch - e.g. the distances d _C d may be between about 0.1* L _g and 10*L _g , including all values and ranges therein. For example, for a gate length of about 160 nm (i.e. an exemplary high voltage application), d _C d may be about 20 nm. Of course, different values of d _C d are also possible, for various design requirements, all of which are within the scope of the present disclosure. [0062] FIG. 2 further illustrates a source electrode 216-1 and first and second drain electrodes 214- 1 and 214-2 formed of one or more electrically conductive materials 210. The source electrode 216- 1 is electrically connected to the source region 226-1, while the first and second drain electrodes 214-1 and 214-2 are electrically connected to, respectively, the common drain region 228 and the additional drain region 224-2. The S/D electrode material 210 may include any suitable electrically conductive material, alloy, or a stack of multiple electrically conductive materials. In some embodiments, the S/D electrode material 210 may include one or more metals or metal alloys, with metals such as e.g. ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, and aluminum. In some embodiments, the S/D electrode material 210 may include one or more electrically conductive alloys oxides or carbides of one or more metals. In various

embodiments, the S/D conductive material 210 could be the same or different materials for the source electrode 216-1, the first drain electrode 214-1, and the second drain electrode 214-2, and could be the same or different materials as the gate electrode material 206. In various

embodiments, the S/D electrode material 210 may have a thickness between about 5 and 500 nm, including all values and ranges therein, e.g. between 5 and 100 nm.

[0063] Although the transistor arrangement shown in FIG. 2 only illustrates two transistors - the first transistor Tl and one dummy transistor, T2, in various embodiments, any number of 1 or more such dummy transistors could be implemented. Additional dummy transistors would be implemented to the left of the dummy transistor T2, for the view of FIG. 2, with their diffusion regions all connected to the first drain terminal Dl. An example of this is illustrated in FIG. 3 where an exemplary multi-drain transistor arrangement 301 includes the active transistor Tl and three dummy transistors - shown as T2, T3, and T4 - the dummy transistors having their diffusion regions connected to a single drain terminal Dl, along with the drain region of the active transistor Tl, and having their gates electrically floating. As shown in FIG. 3, the nearest diffusion regions of the adjacent dummy transistors are implemented as a continuous common diffusion region (similar to the common diffusion region 228 between transistors Tl and T2 shown in FIG. 2), with a single electrode providing electrical connectivity from the common diffusion region to the drain terminal Dl: e.g. the diffusion region of the dummy transistor T2 nearest to the diffusion region of the dummy transistor T3 may be combined into a single diffusion region with a single drain electrode, etc.

[0064] FIG. 3 is a schematic illustration of an exemplary driver circuit 300 with an exemplary multi- drain transistor arrangement 301, in accordance with various embodiments of the present disclosure. The multi-drain transistor arrangement 301 may be implemented as an example of the transistor arrangement 200, described above, with any number of one or more dummy transistors (three of which are shown for the particular example of FIG. 3, but any other number could also be used). As shown in FIG. 3, the gates of the dummy transistors, shown as the gates G2, G3, and G4 for the dummy transistors T2, T3, and T4, respectively, are not connected to any signal, i.e. gates G2- G4 are floating. The gate of the active transistor Tl is connected to a pre-driver 350 which is switching the driver stage 301. In operation, the pre-driver 350 is configured to apply a signal (e.g. voltage bias) to the gate Gl, switching the transistor arrangement 301 between high and low impedance states, which varies the signal at the drain terminal Dl. The drain terminal Dl may e.g. be connected to an I/O connector, e.g. an I/O pad, or any other component of a given device. In this manner, the driver circuit 300 can drive further components - e.g. in case of a digital circuit, the driver circuit 300 can drive 0s and Is, while in case of an analog circuit - drive the targeted voltage and/or current levels.

[0065] Although the transistor arrangement shown in FIG. 2 only illustrates one active transistor - the first transistor Tl, the multi-drain transistor arrangements as described herein may be implemented in other, multi-finger, transistor arrangements where more than one active transistor is used, some examples of which are shown in FIGS. 4B and 4C, described below. Again, any number of one or more dummy transistors may be used here as well, in accordance with various

embodiments disclosed herein.

[0066] FIGS. 4A-4C are top views of exemplary conventional transistor arrangements and multi- drain transistor arrangements in accordance with various embodiments of the present disclosure. The exemplary conventional transistor arrangements are shown on the left sides of FIGS. 4A-4C as transistor arrangements 402A, 402B, and 402C, while the exemplary multi-drain transistor arrangements in accordance with various embodiments of the present disclosure are shown on the right sides of FIGS. 4A-4C as transistor arrangements 404A, 404B, and 404C.

[0067] FIG. 4A illustrates single-sided transistor arrangements, while each of FIGS. 4B and 4C illustrate double-sided, or multi-finger, transistor arrangements. The layouts shown in FIGS. 4A-4C illustrate that all embodiments of the new multi-drain transistor arrangements as proposed herein can be made compliant to typical industry-wide design requirements strictly following a poly-gate pattern being implemented, with the main modification being in the configuration of the different diffusion regions so that multiple diffusion regions are connected to a single drain terminal, thus being configured effectively as an enlarged drain region.

[0068] In FIGS. 4A-4C, each element 406 illustrates to a gate of an active transistor (i.e. a gate to which a bias is applied), each element 408 illustrates a diffusion region connected to a drain terminal, each element 410 illustrates a diffusion region connected to a source terminal, and each element 412 illustrates to a gate of a dummy transistor (i.e. a floating gate). In accordance with the multi-drain principles described herein, all of the diffusion regions 408 shown in each of the multi- drain transistor arrangements 404A and 404B are connected to a single drain terminal, e.g. the drain terminal similar to Dl shown in FIG. 1. For the multi-drain transistor arrangement 404C, the two diffusion regions 408 shown on the left side of the active transistors are connected to a first single drain terminal, while the two diffusion regions 408 shown on the right side of the active transistors are connected to a second single drain terminal, thus provided a respective extended drain region instead of a conventional drain region provided on each side of two active transistors sharing a common source region, as shown with the conventional transistor arrangement 402C. The layout variants shown in FIGS. 4A-4C represent solutions for an area efficient design for drivers with a large number of FinFETs.

[0069] While multi-drain transistor arrangements in accordance with various embodiments of the present disclosure have been described above with reference to FinFETs, in various embodiments such transistors may be implemented using any suitable transistor structure, two examples of which are shown in FIGS. 5 and 6, both illustrating different non-planar architectures. In other embodiments, teachings of the present disclosure may also be implemented with transistors having planar architectures.

[0070] FIGS. 5 and 6 provide perspective illustrations of exemplary transistors to be used as building blocks in providing multi-drain transistor arrangements described herein, i.e. each illustrating only a single transistor, in order to not clutter the drawings. While only a single transistor is shown in each of FIGS. 5 and 6, and references are made to an active transistor, the FinFET 500 or the all-around gate transistor 600 shown in these FIGS, may be seen as illustrating a perspective drawing for each of the transistors shown in FIGS. 2, 3, or 4A-4C, or any other FinFET arrangement where multiple diffusion regions are connected to a single drain terminal in accordance with various embodiments described herein, where additional transistors, including dummy transistors, would be implemented along the fin shown in FIG. 5 or along the wire shown in FIG. 6.

[0071] FIG. 5 is a perspective view of an example FinFET 500 that could be used as a building block in providing a multi-drain transistor arrangement, in accordance with various embodiments.

[0072] Reference numerals used to label elements of FIG. 5 which are the same as reference numerals used to label elements of FIG. 2 are intended to illustrate similar/analogous or same elements and, therefore, discussions of these elements provided with respect to FIG. 2 are applicable to FIG. 5 and, in the interests of brevity, are not repeated for FIG. 5. In particular, FIG. 5 illustrates the substrate 202, the channel material 204, the gate electrode 210, the gate dielectric 208, the fin 220, the gate stack 212-1, the source region 226-1, and the drain region 224-1. In addition, FIG. 5 illustrates STI 509, similar to the STI 110 described above. [0073] The composition of the channel material 204, the source region 226-1, and the drain region 224-1 of the FinFET 500 may take the form of any of the embodiments disclosed herein, or known in the art. In particular, the source region 226-1 and the drain region 224-1 may be implemented as described above for any of the multi-drain transistor arrangements proposed herein, where the drain region 224-1 shown in FIG. 5 is a part of a common drain region, such as e.g. the region 228 of FIG. 2, with one or more dummy transistors as described herein implemented along the fin 220 shown in FIG. 5, after the region 228.

[0074] Although the fin 220 illustrated in FIG. 5 is shown as having a rectangular cross section, the fin 220 may instead have a cross section that is rounded or sloped at the "top" of the fin 220, and the gate stacks 212 may conform to this rounded or sloped fin 220. In use, the FinFET 500 may form conducting channels on three "sides" of the fin 220 wrapped around by the gate stack 212-1, potentially improving performance relative to single-gate transistors (which may form conducting channels on one "side" of a channel material or substrate) and double-gate transistors (which may form conducting channels on two "sides" of a channel material or substrate).

[0075] In some embodiments, multiple transistor arrangements such as the transistor arrangement 200 shown in FIG. 2, including FinFETs similar to that shown in FIG. 5, may be provided along a single fin such as the fin 220, with considerations relevant to providing multiple devices on a single fin being known in the art and, therefore, in the interests of brevity, not specifically described here.

[0076] FIG. 6 is a perspective view of an example all-around gate transistor 600 that could be used as a building block in providing a multi-drain transistor arrangement, in accordance with various embodiments. The transistor 600 of FIG. 6 may include one or more semiconductor materials, including a channel material 204, as described above, the one or more semiconductor materials formed as a wire 620 provided over a substrate, e.g. the substrate 202 as described above. The wire 620 may take the form of a nanowire or nanoribbon, for example. A gate stack, e.g. gate stack 212- 1, including a gate electrode material 210 and a high-k dielectric 208 may wrap entirely or almost entirely around the wire 620 as shown in FIG. 6, with the active region of the channel material 204 corresponding to the portion of the wire 620 wrapped by the gate stack. In particular, the high-k dielectric 208 may wrap around the wire 620 and the gate electrode material 210 may wrap around the high-k dielectric 208. In some embodiments, the gate stack may fully encircle the wire 620. In some embodiments, a layer of oxide material (not specifically shown in FIG. 6) may be provided between the substrate 202 and the gate electrode 210.

[0077] The wire 620 may include a source region 226-1 and a drain region 224-1 on either side of the gate stack, as shown. The composition of the channel material 204, the source region 226-1, and the drain region 224-1 of the all-around gate transistor 600 may take the form of any of the embodiments disclosed herein, or known in the art. In particular, the source region 226-1 and the drain region 224-1 may be implemented as described above for any of the multi-drain transistor arrangements proposed herein, where the drain region 224-1 shown in FIG. 6 is a part of a common drain region, such as e.g. the region 228 of FIG. 2, with one or more dummy transistors as described herein implemented along the wire 620 after the region 228.

[0078] Although not specifically illustrated in FIG. 6, a dielectric spacer may be provided between the source electrode and the gate stack as well as between the transistor drain electrode and the gate stack of the all-around-gate transistor 600 in order to provide electrical isolation between the source, gate, drain electrodes, similar to a dielectric spacer described above for the transistor arrangement 200.

[0079] Furthermore, although the wire 620 illustrated in FIG. 6 is shown as having a rectangular cross section, the wire 620 may instead have a cross section that is rounded or otherwise irregularly shaped, and the gate stacks may conform to the shape of the wire 620. In use, the all-around-gate transistor 600 may form conducting channels on more than three "sides" of the wire 620, potentially improving performance relative to FinFETs. Although FIG. 6 depicts an embodiment in which the longitudinal axis of the wire 620 runs substantially parallel to a plane of the substrate 202, this need not be the case; in other embodiments, for example, the wire 620 may be oriented "vertically" so as to be perpendicular to a plane of the substrate 202.

[0080] In some embodiments, multiple transistor arrangements such as the transistor arrangement 200 shown in FIG. 2, including all-around-gate transistors similar to that shown in FIG. 6, may be provided along a single wire such as the wire 620, with considerations relevant to providing multiple devices on a single wire being known in the art and, therefore, in the interests of brevity, not specifically described here.

[0081] The transistor arrangements illustrated in FIGS. 2-6 do not represent an exhaustive set of transistor arrangements in which multiple diffusion regions electrically connected to a single drain terminal may be included, but merely provide examples of such structures. Although particular arrangements of materials are discussed with reference to FIGS. 2-6, intermediate materials may be included in the transistor devices of these FIGS. Note that FIGS. 2-6 are intended to show relative arrangements of the components therein, and that transistor arrangements of these FIGS may include other components that are not illustrated (e.g., gate spacers or various interfacial layers). Additionally, although various components of the transistor arrangements are illustrated in FIGS. 2-6 as being planar rectangles or formed of rectangular solids, this is simply for ease of illustration, and embodiments of these transistors may be curved, rounded, or otherwise irregularly shaped as dictated by, and sometimes inevitable due to, the manufacturing processes used to fabricate various components.

[0082] Transistor arrangements with multiple diffusion regions electrically connected to a single drain terminal as disclosed herein may be manufactured using any suitable techniques. For example, FIG. 7 is a flow diagram of an example method 700 of manufacturing a multi-drain transistor arrangement having multiple diffusion regions electrically connected to a single drain terminal, in accordance with various embodiments. Although the operations of the method 700 are illustrated once each and in a particular order, the operations may be performed in any suitable order and repeated as desired. For example, one or more operations may be performed in parallel to manufacture multiple multi-drain transistor arrangements substantially simultaneously. In another example, the operations may be performed in a different order to reflect the structure of a particular device in which a multi-drain transistor arrangement having multiple diffusion regions electrically connected to a single drain terminal will be included.

[0083] At 702, one or more semiconductor materials for forming a channel of the future transistor arrangement may be provided. The one or more semiconductor materials provided at 702 may take the form of any of the embodiments of the channel material 204 disclosed herein, for example (e.g., any of the embodiments discussed herein with reference to the multi-drain transistor arrangements shown in FIGS. 2-6). The one or more semiconductor materials may be provided at 702 using any suitable deposition and patterning techniques known in the art.

[0084] At 704, future diffusion regions may be provided within the one or more semiconductor materials 204. The diffusion regions defined at 704 may take the form of any of the embodiments of the diffusion regions 228, 224-2 and 226-1, disclosed herein, for example (e.g., any of the embodiments discussed herein with reference to the multi-drain transistor arrangements shown in FIGS. 2-6). The diffusion regions provided at 704 may be manufactured using any suitable techniques known in the art, such as e.g. using an implantation/diffusion process or a deposition process, possibly using a suitable mask for implementing the diffusion regions, including common diffusion region(s), at desired locations within a transistor arrangement, as described above.

[0085] At 706, the gate dielectric material may be provided. The gate dielectric material provided at 706 may take the form of any of the embodiments of the gate dielectric material 308 disclosed herein, for example (e.g., any of the embodiments discussed herein with reference to the multi-drain transistor arrangements shown in FIGS. 2-6). The gate dielectric material may be provided at 706 using any suitable deposition and patterning techniques known in the art.

[0086] At 708, the gate, source, and drain electrodes may be provided. The S/D electrode material provided at 708 may take the form of any of the embodiments of the S/D electrode material 210 disclosed herein while the gate electrode material provided at 708 may take the form of any of the embodiments of the gate electrode material 206 disclosed herein, for example (e.g., any of the embodiments discussed herein with reference to the multi-drain transistor arrangements shown in FIGS. 2-6). The gate, source, and drain electrodes may be provided at 708 using any suitable deposition and patterning techniques known in the art.

[0087] Multi-drain transistor arrangements having multiple diffusion regions connected to a single drain terminal as disclosed herein may be included in any suitable electronic device. FIGS. 8-11 illustrate various examples of apparatuses that may include one or more of such multi-drain transistor arrangements.

[0088] FIGS. 8A-B are top views of a wafer 2000 and dies 2002 that may include one or more multi- drain transistor arrangements in accordance with any of the embodiments disclosed herein. The wafer 2000 may be composed of semiconductor material and may include one or more dies 2002 having IC structures formed on a surface of the wafer 2000. Each of the dies 2002 may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., ICs including one or more transistor arrangements 200, or any other transistor arrangements having multiple diffusion regions connected to a single drain terminal as described herein). After the fabrication of the semiconductor product is complete (e.g., after manufacture of one or more transistor arrangements 200, or any other transistor arrangements having multiple diffusion regions connected to a single drain terminal as described herein), the wafer 2000 may undergo a singulation process in which each of the dies 2002 is separated from one another to provide discrete "chips" of the semiconductor product. In particular, devices that include one or more multi-drain transistor arrangements as disclosed herein may take the form of the wafer 2000 (e.g., not singulated) or the form of the die 2002 (e.g., singulated). The die 2002 may include one or more transistors (e.g., one or more of the transistors 2140 of FIG. 9, discussed below, at least some of which may take the form of any of the multi-drain transistor arrangements as described herein) and/or supporting circuitry to route electrical signals to the transistors, as well as any other IC components. In some embodiments, the wafer 2000 or the die 2002 may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 2002. For example, a memory array formed by multiple memory devices may be formed on a same die 2002 as a processing device (e.g., the processing device 2202 of FIG. 11) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

[0089] FIG. 9 is a cross-sectional side view of an IC device 2100 that may include one or more multi- drain transistor arrangements in accordance with any of the embodiments disclosed herein. The IC device 2100 may be formed on a substrate 2102 (e.g., the wafer 2000 of FIG. 8A) and may be included in a die (e.g., the die 2002 of FIG. 8B). The substrate 2102 may be a semiconductor substrate composed of semiconductor material systems including, for example, N-type or P-type materials systems. The substrate 2102 may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In some embodiments, the semiconductor substrate 2102 may be formed using alternative materials, which may or may not be combined with silicon, that include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group ll-VI, lll-V, or IV may also be used to form the substrate 2102. Although a few examples of materials from which the substrate 2102 may be formed are described here, any material that may serve as a foundation for an IC device 2100 may be used. The substrate 2102 may be part of a singulated die (e.g., the die 2002 of FIG. 8B) or a wafer (e.g., the wafer 2000 of FIG. 8A).

[0090] The IC device 2100 may include one or more device layers 2104 disposed on the substrate 2102. The device layer 2104 may include features of one or more transistors 2140 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the substrate 2102. The device layer 2104 may include, for example, one or more source and/or drain (S/D) regions 2120, a gate 2122 to control current flow in the transistors 2140 between the S/D regions 2120, and one or more S/D contacts 2124 to route electrical signals to/from the S/D regions 2120. Even though not specifically illustrated in FIG. 9, at least some of the one or more transistors 2140 may include any of the multi- drain transistor arrangements as described herein. Thus, at least some of the S/D regions 2120 may include the diffusion regions 228, 224-2 and 226-1 described above, or any other diffusion regions where multiple drain regions are form an extended diffusion region and are connected to a single drain terminal, as described herein. The transistors 2140 are not limited to the type and configuration depicted in FIG. 9 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both, each of which could be used to implement multi-drain transistor arrangements as described herein. Non- planar transistors may include FinFET transistors, such as double-gate transistors or FinFETs, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors. For example, a transistor 2140 may take the form of any of the transistor arrangements described with reference to FIGS. 2-6. The transistors 2140 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like.

[0091] Each transistor 2140 may include a gate 2122 formed of at least two layers, a gate dielectric layer and a gate electrode layer. Generally, the gate dielectric layer of a transistor 2140 may include one layer or a stack of layers, and the one or more layers may include silicon oxide, silicon dioxide, and/or a high-k dielectric material. The high-k dielectric material included in the gate dielectric layer of the transistor 2140 may take the form of any of the embodiments of the high-k dielectric 208 disclosed herein, for example.

[0092] In some embodiments, when viewed as a cross section of the transistor 2140 along the source-channel-drain direction, the gate electrode may include a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate (e.g., as illustrated for a FinFET of FIGS. 1A and IB). In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may include a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may include one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers. In some embodiments, the gate electrode may include a V-shaped structure (e.g., when the fin of a FinFET does not have a "flat" upper surface, but instead has a rounded peak).

[0093] In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0094] The S/D regions 2120 may be formed within the substrate 2102 and include multi-drain diffusion regions as described herein. For example, at least some of the S/D regions 2120 formed within the substrate 2102 may include the diffusion regions 228, 224-2 and 226-1 described above, or any other diffusion regions where multiple drain regions are form an extended diffusion region and are connected to a single drain terminal, as described herein. The S/D regions 2120 may be formed within the substrate 2102 using any suitable processes known in the art, some of which are described above.

[0095] Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the transistors 2140 of the device layer 2104 through one or more interconnect layers disposed on the device layer 2104 (illustrated in FIG. 9 as interconnect layers 2106-2110). For example, electrically conductive features of the device layer 2104 (e.g., the gate 2122 and the S/D contacts 2124) may be electrically coupled with the interconnect structures 2128 of the interconnect layers 2106-2110. The one or more interconnect layers 2106-2110 may form an interlayer dielectric (ILD) stack 2119 of the IC device 2100.

[0096] The interconnect structures 2128 may be arranged within the interconnect layers 2106-1210 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 2128 depicted in FIG. 9). Although a particular number of interconnect layers 2106-1210 is depicted in FIG. 9, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

[0097] In some embodiments, the interconnect structures 2128 may include trench structures 2128a (sometimes referred to as "lines") and/or via structures 2128b (sometimes referred to as "holes") filled with an electrically conductive material such as a metal. The trench structures 2128a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate 2102 upon which the device layer 2104 is formed. For example, the trench structures 2128a may route electrical signals in a direction in and out of the page from the perspective of FIG. 9. The via structures 2128b may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate 2102 upon which the device layer 2104 is formed. In some embodiments, the via structures 2128b may electrically couple trench structures 2128a of different interconnect layers 2106-2110 together.

[0098] The interconnect layers 2106-2110 may include a dielectric material 2126 disposed between the interconnect structures 2128, as shown in FIG. 9. In some embodiments, the dielectric material 2126 disposed between the interconnect structures 2128 in different ones of the interconnect layers 2106-2110 may have different compositions; in other embodiments, the composition of the dielectric material 2126 between different interconnect layers 2106-2110 may be the same.

[0099] A first interconnect layer 2106 (referred to as Metal 1 or "Ml") may be formed directly on the device layer 2104. In some embodiments, the first interconnect layer 2106 may include trench structures 2128a and/or via structures 2128b, as shown. The trench structures 2128a of the first interconnect layer 2106 may be coupled with contacts (e.g., the S/D contacts 2124) of the device layer 2104.

[0100] A second interconnect layer 2108 (referred to as Metal 2 or "M2") may be formed directly on the first interconnect layer 2106. In some embodiments, the second interconnect layer 2108 may include via structures 2128b to couple the trench structures 2128a of the second interconnect layer 2108 with the trench structures 2128a of the first interconnect layer 2106. Although the trench structures 2128a and the via structures 2128b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 2108) for the sake of clarity, the trench structures 2128a and the via structures 2128b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.

[0101] A third interconnect layer 2110 (referred to as Metal 3 or "M3") (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 2108 according to similar techniques and configurations described in connection with the second interconnect layer 2108 or the first interconnect layer 2106.

[0102] The IC device 2100 may include a solder resist material 2134 (e.g., polyimide or similar material) and one or more bond pads 2136 formed on the interconnect layers 2106-2110. The bond pads 2136 may be electrically coupled with the interconnect structures 2128 and configured to route the electrical signals of the transistor(s) 2140 to other external devices. For example, solder bonds may be formed on the one or more bond pads 2136 to mechanically and/or electrically couple a chip including the IC device 2100 with another component (e.g., a circuit board). The IC device 2100 may have other alternative configurations to route the electrical signals from the interconnect layers 2106-2110 than depicted in other embodiments. For example, the bond pads 2136 may be replaced by or may further include other analogous features (e.g., posts) that route the electrical signals to external components.

[0103] FIG. 10 is a cross-sectional side view of an IC device assembly 2200 that may include components having one or more multi-drain transistor arrangements in accordance with any of the embodiments disclosed herein. The IC device assembly 2200 includes a number of components disposed on a circuit board 2202 (which may be, e.g., a motherboard). The IC device assembly 2200 includes components disposed on a first face 2240 of the circuit board 2202 and an opposing second face 2242 of the circuit board 2202; generally, components may be disposed on one or both faces 2240 and 2242. In particular, any suitable ones of the components of the IC device assembly 2200 may include any of the transistor arrangements having multiple diffusion regions connected to a single drain terminal in accordance with any of the embodiments disclosed herein.

[0104] In some embodiments, the circuit board 2202 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 2202. In other embodiments, the circuit board 2202 may be a non-PCB substrate.

[0105] The IC device assembly 2200 illustrated in FIG. 10 includes a package-on-interposer structure 2236 coupled to the first face 2240 of the circuit board 2202 by coupling components 2216. The coupling components 2216 may electrically and mechanically couple the package-on-interposer structure 2236 to the circuit board 2202, and may include solder balls (as shown in FIG. 10), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

[0106] The package-on-interposer structure 2236 may include an IC package 2220 coupled to an interposer 2204 by coupling components 2218. The coupling components 2218 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 2216. Although a single IC package 2220 is shown in FIG. 10, multiple IC packages may be coupled to the interposer 2204; indeed, additional interposers may be coupled to the interposer 2204. The interposer 2204 may provide an intervening substrate used to bridge the circuit board 2202 and the IC package 2220. The IC package 2220 may be or include, for example, a die (the die 2002 of FIG. 8B), an IC device (e.g., the IC device 2100 of FIG. 9), or any other suitable component. Generally, the interposer 2204 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 2204 may couple the IC package 2220 (e.g., a die) to a ball grid array (BGA) of the coupling components 2216 for coupling to the circuit board 2202. In the embodiment illustrated in FIG. 10, the IC package 2220 and the circuit board 2202 are attached to opposing sides of the interposer 2204; in other embodiments, the IC package 2220 and the circuit board 2202 may be attached to a same side of the interposer 2204. In some

embodiments, three or more components may be interconnected by way of the interposer 2204.

[0107] The interposer 2204 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 2204 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials. The interposer 2204 may include metal interconnects 2208 and vias 2210, including but not limited to through-silicon vias (TSVs) 2206. The interposer 2204 may further include embedded devices 2214, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD devices, and memory devices. In particular, one or more multi-drain transistor arrangements may be included within at least some of the embedded devices 2214, e.g. as ESD devices. More complex devices such as radio-frequency ( F) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 2204. The package-on-interposer structure 2236 may take the form of any of the package-on-interposer structures known in the art.

[0108] The IC device assembly 2200 may include an IC package 2224 coupled to the first face 2240 of the circuit board 2202 by coupling components 2222. The coupling components 2222 may take the form of any of the embodiments discussed above with reference to the coupling components 2216, and the IC package 2224 may take the form of any of the embodiments discussed above with reference to the IC package 2220.

[0109] The IC device assembly 2200 illustrated in FIG. 10 includes a package-on-package structure 2234 coupled to the second face 2242 of the circuit board 2202 by coupling components 2228. The package-on-package structure 2234 may include an IC package 2226 and an IC package 2232 coupled together by coupling components 2230 such that the IC package 2226 is disposed between the circuit board 2202 and the IC package 2232. The coupling components 2228 and 2230 may take the form of any of the embodiments of the coupling components 2216 discussed above, and the IC packages 2226 and 2232 may take the form of any of the embodiments of the IC package 2220 discussed above. The package-on-package structure 2234 may be configured in accordance with any of the package-on-package structures known in the art.

[0110] FIG. 11 is a block diagram of an example computing device 2300 that may include one or more components with one or more multi-drain transistor arrangements in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the computing device 2300 may include a die (e.g., the die 2002 (FIG. 8B)) having one or more multi- drain transistor arrangements in accordance with any of the embodiments disclosed herein. Any one or more of the components of the computing device 2300 may include, or be included in, an IC device 2100 (FIG. 9). Any one or more of the components of the computing device 2300 may include, or be included in, an IC device assembly 2200 (FIG. 10).

[0111] A number of components are illustrated in FIG. 11 as included in the computing device 2300, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the computing device 2300 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.

[0112] Additionally, in various embodiments, the computing device 2300 may not include one or more of the components illustrated in FIG. 11, but the computing device 2300 may include interface circuitry for coupling to the one or more components. For example, the computing device 2300 may not include a display device 2306, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2306 may be coupled. In another set of examples, the computing device 2300 may not include an audio input device 2324 or an audio output device 2308, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2324 or audio output device 2308 may be coupled. [0113] The computing device 2300 may include a processing device 2202 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2202 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing device 2300 may include a memory 2204, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 2204 may include memory that shares a die with the processing device 2202. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-M RAM).

[0114] In some embodiments, the computing device 2300 may include a communication chip 2312 (e.g., one or more communication chips). For example, the communication chip 2312 may be configured for managing wireless communications for the transfer of data to and from the computing device 2300. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

[0115] The communication chip 2312 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and

interoperability tests for the IEEE 802.16 standards. The communication chip 2312 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2312 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2312 may operate in accordance with Code Division M ultiple Access (CDMA), Time Division M ultiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2312 may operate in accordance with other wireless protocols in other embodiments. The computing device 2300 may include an antenna 2322 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

[0116] In some embodiments, the communication chip 2312 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2312 may include multiple communication chips. For instance, a first communication chip 2312 may be dedicated to shorter-range wireless

communications such as Wi-Fi or Bluetooth, and a second communication chip 2312 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2312 may be dedicated to wireless communications, and a second communication chip 2312 may be dedicated to wired communications.

[0117] The computing device 2300 may include battery/power circuitry 2314. The battery/power circuitry 2314 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device 2300 to an energy source separate from the computing device 2300 (e.g., AC line power).

[0118] The computing device 2300 may include a display device 2306 (or corresponding interface circuitry, as discussed above). The display device 2306 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

[0119] The computing device 2300 may include an audio output device 2308 (or corresponding interface circuitry, as discussed above). The audio output device 2308 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

[0120] The computing device 2300 may include an audio input device 2324 (or corresponding interface circuitry, as discussed above). The audio input device 2324 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (M IDI) output). [0121] The computing device 2300 may include a global positioning system (GPS) device 2318 (or corresponding interface circuitry, as discussed above). The GPS device 2318 may be in

communication with a satellite-based system and may receive a location of the computing device 2300, as known in the art.

[0122] The computing device 2300 may include an other output device 2310 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2310 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0123] The computing device 2300 may include an other input device 2320 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2320 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0124] The computing device 2300 may have any desired form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2300 may be any other electronic device that processes data.

[0125] The following paragraphs provide various examples of the embodiments disclosed herein.

[0126] Example 1 provides a multi-drain transistor arrangement that includes a channel material, a first gate electrode (e.g. the gate electrode 206 of the gate stack 212-1) provided over a first portion of the channel material, a second gate electrode (e.g. the gate electrode 206 of the gate stack 212-2) provided over a second portion of the channel material, a first drain electrode (e.g. the drain electrode 214-1) provided between the first gate electrode and the second gate electrode and electrically connected to a first drain terminal (e.g. the drain contact Dl), and a second drain electrode (e.g. the drain electrode 214-2) electrically connected to the first drain terminal as well.

[0127] In all Examples described herein, each of the S/D, or diffusion, regions are regions of doped semiconductor materials, while the channel material may include one or more semiconductor materials with doping concentrations significantly smaller than those of the diffusion regions. For example, in some embodiments, the channel material may be an intrinsic (i.e. undoped) lll-V or IV semiconductor material or alloy, not intentionally doped with any electrically active impurity. In alternate embodiments, one or more a nominal impurity dopant level may be present within the channel material, for example to set a threshold voltage Vt, or to provide HALO pocket implants, etc. In such impurity-doped embodiments however, impurity dopant level within the channel material are still significantly lower than in the source and drain regions, for example below 10 ¹⁵ dopant elements per cubic centimeter (cm ³ ), and advantageously below 10 ¹³ cm ^"3 . Also in all Examples described herein, the gate electrode material, as well as each of the source electrode material and the drain electrode material, may include one or more of conductor materials, e.g. one or more metals.

[0128] Example 2 provides the transistor arrangement according to Example 1, where the second gate electrode is between the second drain electrode and the first drain electrode.

[0129] Example 3 provides the multi-drain transistor arrangement according to Examples 1 or 2, further including a common diffusion region, in the channel material, extending continuously between the first gate electrode and the second gate electrode, where the first drain electrode is electrically connected to the common diffusion region.

[0130] Example 4 provides the multi-drain transistor arrangement according to Example 3, further including a second diffusion region separated from the common diffusion region by the channel material, where the second drain electrode is electrically connected to the second diffusion region.

[0131] Example 5 provides the multi-drain transistor arrangement according to Example 4, where each of the common diffusion region and the second diffusion region has a dopant concentration of at least 5-10 ¹⁶ dopant elements per cubic centimeter. For example, the drain region may have a doping concentration between 1-10 ¹⁹ dopant elements per cubic centimeter and 10-10 ²¹ dopant elements per cubic centimeter.

[0132] Example 6 provides the multi-drain transistor arrangement according to Examples 4 or 5, further including a third gate electrode provided over the channel material, where the second diffusion region is a second common diffusion region, extending continuously between the second gate electrode and the third gate electrode.

[0133] Example 7 provides the multi-drain transistor arrangement according to Example 6, further including a third diffusion region and a third drain electrode, where the third diffusion region is separated from the second diffusion region by the channel material and where the third drain electrode is electrically connected to the third diffusion region and to the first drain terminal.

[0134] Example 8 provides the multi-drain transistor arrangement according to any one of

Examples 1-3, further including a third gate electrode provided over the channel material; and a third drain electrode electrically connected to the first drain terminal. [0135] Example 9 provides the multi-drain transistor arrangement according to any one of the preceding Examples, where the first drain electrode is a single electrode between the first gate electrode and the second gate electrode. In other words, the first drain electrode is a common electrode replacing the drain electrode associated with the first gate electrode and the source electrode associated with the second gate electrode.

[0136] Example 10 provides the multi-drain transistor arrangement according to any one of the preceding Examples, further including a first gate dielectric between the first gate electrode and the channel material.

[0137] Example 11 provides the multi-drain transistor arrangement according to Example 10, where the channel material is shaped as a fin, and the first gate dielectric wraps around the fin.

[0138] Example 12 provides the multi-drain transistor arrangement according to Example 10, where the channel material is shaped as a wire, and the first gate dielectric wraps around the wire.

[0139] Example 13 provides the multi-drain transistor arrangement according to Example 12, where the first gate dielectric wraps entirely around the wire.

[0140] Example 14 provides the multi-drain transistor arrangement according to any one of Examples 10-13, where a thickness of the first gate dielectric is above 2 nanometers.

[0141] Example 15 provides a driver assembly/device that includes a multi-drain transistor arrangement having a channel material, a first gate electrode provided over the channel material, a second gate electrode provided over the channel material, a first drain electrode provided between the first gate electrode and the second gate electrode and electrically connected to a first drain terminal, and a second drain electrode electrically connected to the first drain terminal. The driver assembly/device further includes a pre-driver device configured to control a signal applied to the first gate electrode.

[0142] Example 16 provides the driver assembly according to Example 15, further including a further device electrically connected to the first drain terminal.

[0143] Example 17 further includes the driver assembly according to Examples 15 or 16, where the driver assembly is an input/output (I/O) driver.

[0144] Example 18 provides a method of manufacturing a multi-drain transistor arrangement. The method includes providing a channel material; providing a plurality of diffusion regions in the channel material, the plurality of diffusion regions having a dopant concentration higher than a dopant concentration in the channel material; providing a first gate dielectric material over a first portion the channel material and a second gate dielectric material over a second portion the channel material, where the first portion of the channel material is between a first pair of diffusion regions of the plurality of diffusion regions, and the second portion of the channel material is between a second pair of diffusion regions of the plurality of diffusion regions (the first and second pairs being different in at least one diffusion region); and providing a first gate electrode material over the first gate dielectric material and a second gate electrode material over the second gate dielectric material, electrically connecting at least two of the plurality of diffusion regions to a single drain terminal.

[0145] Example 19 provides the method according to Example 18, where a first diffusion region of the plurality of diffusion regions is closest to an edge of the first gate dielectric material that is farthest from the second gate dielectric material, a second diffusion region of the plurality of diffusion regions is between the first and the second portions of the channel material (i.e. the second diffusion region continuously extends between the first and second portions of the channel material, separating the first and second portions of the channel material), and a third diffusion region of the plurality of diffusion regions is closest to an edge of the second gate dielectric material that is farthest from the first gate dielectric material.

[0146] Example 20 provides the method according to Example 19, further including providing a source electrode material to be in electrical contact with the first diffusion region; providing a first drain electrode material to be in electrical contact with the second diffusion region; and providing a second drain electrode material to be in electrical contact with the third diffusion region, where connecting at least two of the plurality of diffusion regions to the single drain terminal includes connecting the first and second drain electrodes to the single drain terminal.

[0147] In various Examples, providing transistor electrode materials (i.e. gate, source, and drain electrode materials) includes depositing titanium, aluminum, titanium nitride, erbium, gadolinium, or ytterbium, using any suitable deposition and patterning techniques.

[0148] Example 21 provides the method according to any one of Examples 18-20, where providing the plurality of diffusion regions includes doping the channel material to form the plurality of diffusion regions.

[0149] Example 22 provides the method according to Example 21, further including performing an anneal of the transistor arrangement to activate dopants of the plurality of diffusion regions.

[0150] Example 23 provides the method according to any one of Examples 18-20, where providing the plurality of diffusion regions includes forming a plurality of openings in the channel material and depositing the one or more doped semiconductor materials into the plurality of openings, e.g. using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

[0151] Example 24 provides a computing device that includes a substrate and an integrated circuit (IC) die coupled to the substrate. The IC die includes a transistor arrangement having a channel material, a plurality of diffusion regions in the channel material, the plurality of diffusion regions having a dopant concentration higher than a dopant concentration in the channel material, and a first gate dielectric material over a first portion the channel material and a second gate dielectric material over a second portion the channel material, where a first diffusion region of the plurality of diffusion regions is closest to an edge of the first gate dielectric material that is farthest from the second gate dielectric material and is electrically connected to a source terminal for the transistor arrangement, a second diffusion region of the plurality of diffusion regions is between the first and the second portions of the channel material (i.e. the second diffusion region continuously extends between the first and second portions of the channel material, separating the first and second portions of the channel material), a third diffusion region of the plurality of diffusion regions is closest to an edge of the second gate dielectric material that is farthest from the first gate dielectric material, and each of the second and the third diffusion regions are electrically connected to a single drain terminal for the transistor arrangement.

[0152] In further Examples, the transistor arrangement included within the computing device is a transistor arrangement according to any one of the preceding Examples.

[0153] Example 25 provides the computing device according to Example 24, where the computing device is a wearable or handheld computing device.

[0154] Example 26 provides the computing device according to Examples 24 or 25, where the computing device further includes one or more communication chips and an antenna.

[0155] Example 27 provides the computing device according to any one of Examples 24-26, where the substrate is a motherboard.

[0156] The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

[0157] These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.