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Title:
MULTI-FRAME CACHING DUAL-CAMERA TWIN-TEST TEST CARD
Document Type and Number:
WIPO Patent Application WO/2018/076402
Kind Code:
A1
Abstract:
A multi-frame caching dual-camera twin-test test card, which comprises: an FPGA (10), a detection module (20), a data interaction module (30), an interface module (40) and an open short circuit module (50); the FPGA (10) has four DDRs (11), and the FPGA (10) has a dual MIPI decoding unit (13), a DVP image acquisition unit (14), and an LVDS image decoding unit (15); the detection module (20) is connected with an I2C/GPIO control module (21) inside the FPGA (10); the data interaction module (30) is integrated in the FPGA (10), and performs data transmission with an upper computer (60); the interface module (40) is integrated in the FPGA (10), and performs the data transmission with the upper computer (60) through the data interaction module (30); and the open short circuit module (50) is connected with the FPGA (10). Two cameras can be activated at the same time by dual-camera or two camera full-speed (1.6 G/4 lane), transmitting to PC in real time through a USB 3.0 interface. At the same time, with 8 G of memory and with 64 Gbps of cache reading and writing capability, far beyond the output image rate of 12 Gbps of a camera, two cameras can simultaneously cache continuous frames at 15 fps.

Inventors:
ZHONG YUELIANG (CN)
LI CHANGSHUI (CN)
XIA YUANYANG (CN)
Application Number:
PCT/CN2016/105269
Publication Date:
May 03, 2018
Filing Date:
November 10, 2016
Export Citation:
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Assignee:
KUNSHAN ROLONGO AUTOMATION TECH CO LTD (CN)
International Classes:
H04N17/00
Foreign References:
CN206100337U2017-04-12
CN105866607A2016-08-17
CN201116967Y2008-09-17
CN201282538Y2009-07-29
Attorney, Agent or Firm:
BEIJING KEYI INTELLECTUAL PROPERTY FIRM (CN)
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