MULTI-LAYER PRINTED CIRCUIT BOARD

Title:

MULTI-LAYER PRINTED CIRCUIT BOARD

Document Type and Number:

WIPO Patent Application WO/2006/101134

Kind Code:

A1

Abstract:

[PROBLEMS] To provide a multi-layer printed circuit board capable of assuring via hole connection reliability. [MEANS FOR SOLVING PROBLEMS] At the connection portion between the bottom of the filled via (60) and the cover plated layer (36a), the connection boundary plane is shifted downward from the upper surface of the cover plated layer (36a) by depth d1. Thus, the connection boundary plane where a crack is caused most easily is at a lower position than the upper surface position of the cover plated layer (36a) where the stress upon heat shrinkage becomes maximum. Accordingly, a crack is not caused easily and resistance against thermal stress can be enhanced.

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Inventors:

YAMASHITA TAKAHIRO (JP)
ISHIHARA AKIHIDE (JP)
KUBOTA NAOKI (JP)

Application Number:

PCT/JP2006/305721

Publication Date:

September 28, 2006

Filing Date:

March 22, 2006

Export Citation:

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Assignee:

IBIDEN CO LTD (JP)
YAMASHITA TAKAHIRO (JP)
ISHIHARA AKIHIDE (JP)
KUBOTA NAOKI (JP)

International Classes:

H05K3/46

Foreign References:

JP2004158703A	2004-06-03
JP2003218531A	2003-07-31
JP2003069233A	2003-03-07
JP2003283135A	2003-10-03
JP2001156456A	2001-06-08

Attorney, Agent or Firm:

Tashita, Akihito (Sakae 1-chome Naka-k, Nagoya-shi Aichi 08, JP)

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