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Title:
MULTI-LEVEL INVERTER
Document Type and Number:
WIPO Patent Application WO/2024/053453
Kind Code:
A1
Abstract:
The present invention suppresses a voltage drop in a bootstrap circuit. A control unit (60) changes a first voltage vector, a second voltage vector, and a third voltage vector, which are adjacent to a command voltage vector in a first vector space, to a combination of a zero vector, and a fourth voltage vector and a fifth voltage vector that are adjacent to the command voltage vector, in a second vector space. The zero vector is a voltage vector resulting from a combination of potential levels at a third connection point (13) of a plurality of inverter circuits (1) becoming the potential of a negative electrode and a voltage vector resulting from a combination of the potential levels at the third connection point becoming the potential of a positive electrode. The control unit (60) controls a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), and a plurality of fourth gate drivers (64) within a prescribed control period so that the command voltage vector matches a synthesis vector of the zero vector, the fourth voltage vector, and the fifth voltage vector.

Inventors:
NAKAMURA HIROKAZU
HEGDE ANANTHA
SUZUKI ASAMIRA
ARAI YASUHIRO
Application Number:
PCT/JP2023/030965
Publication Date:
March 14, 2024
Filing Date:
August 28, 2023
Export Citation:
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Assignee:
PANASONIC IP MAN CO LTD (JP)
International Classes:
H02M7/487; H02M1/08; H02M7/48
Foreign References:
JPH11164567A1999-06-18
JPH05292755A1993-11-05
JP2012244796A2012-12-10
CN103076482A2013-05-01
US20150236618A12015-08-20
Attorney, Agent or Firm:
HOKUTO PATENT ATTORNEYS OFFICE (JP)
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