MULTI-LEVEL PULSING OF DC AND RF SIGNALS

Field

[0001] The present embodiments relate to systems and methods for multi-level pulsing of a direct current (DC) signal or a radio frequency (RF) signal to achieve a low angular spread.

Background

[0002] The background description provided herein is for the purposes of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

[0003] A plasma tool includes a radio frequency (RF) generator, and impedance matching circuit, and a plasma chamber. The RF generator generates a radio frequency waveform that is supplied to the impedance matching circuit. The impedance matching circuit receives the radio frequency waveform to output a radio frequency signal that is supplied to the plasma chamber. A wafer is processed within the plasma chamber by plasma generated when the radio frequency signal is supplied in conjunction with a process gas. For example, the wafer is etched within the plasma chamber pursuant to the radio frequency signal.

[0004] It is in this context that embodiments described in the present disclosure arise.

Summary

[0005] Embodiments of the disclosure provide systems, apparatus, methods and computer programs for multi-level parameter and multi-level frequency pulsing with a low angular spread. It should be appreciated that the present embodiments can be implemented in numerous ways, e.g., a process, an apparatus, a system, a device, or a method on a computer readable medium. Several embodiments are described below.

[0006] To generate ions, such as both high energy and low energy ions, a radio frequency (RF) bias is increased at low frequency, such as 1 megahertz (MHz). The RF bias has a continuous waveform. The low energy ions have a low voltage and therefore, have a high angular spread. The high angular spread reduces an etch rate of etching a wafer. Also, the low energy ions cross a voltage sheath of plasma and spread out to create the high angular spread. [0007] With an increase in an amount of the RF bias, high aspect ratio etching is achieved. However, the increase in the amount of power increases mask erosion. Also, increasing the amount of RF bias greater than a pre-set amount, such as greater than approximately 5 kilovolts, does not reduce the angular spread due to high plasma sheath thickness.

[0008] By using multiple voltage levels, such as a high bias voltage that is greater than 500 volts, the angular spread is reduced but the low energy ions may still have relatively high energy, which is approximately 200 electron volts (eV). Applying the multiple voltage levels with multiple frequency levels decreases the angular spread in addition to reducing energy of the low energy ions to less than 100 electron volts. The low energy ions with the angular spread that is reduced protect a mask layer and simultaneously etch a substrate layer. The substrate layer has a lower etching threshold compared to the mask layer.

[0009] If the multiple voltage levels and multiple frequency levels with the high bias voltage are applied, the reduction in the energy of the low energy ions and of the angular spread occurs. For example, a low frequency level is applied with a low voltage level and a high frequency level is applied with a high voltage level. After a transition from the low frequency level to the high frequency level and from the low voltage level to the high voltage level, a high electric field is applied to the low energy ions by the high frequency level and the high voltage level. The high electric field is applied to the low energy ions because it takes time to change a plasma sheath associated with the low energy ions. Voltage magnitudes of the low voltage level apply a voltage boost to the low energy ions during the high voltage level. Also, the low energy ions have a low temperature because of the low voltage level. The high electric field increases velocity and energy of the low energy ions without substantially increasing the high voltage level to increase directionality of the low energy ions or reducing the angular spread of the low energy ions. For example, the angular spread is reduced, such as to approximately 1 degree from approximately 2 degrees. The directionality is also increased by the low temperature of the low energy ions. The increase in directionality facilitates piercing of plasma sheath to increase an etch rate of etching a substrate. A number of the multiple voltage levels and a duty cycle of each of the voltage levels are optimized for reducing the angular spread of the low energy ions.

[0010] Also, the high voltage level and the high frequency level of an RF signal create high energy ions having a low angular spread. The low voltage level and the low frequency level create the low energy ions that have a high angular spread. The high energy ions etch a feature of the substrate faster and the low energy ions improve mask selectivity. [0011] The reduction in the angular spread increases the mask selectivity compared to that achieved by applying the continuous waveform, reduces critical dimension, such as a thickness, of a channel within the substrate compared to that achieved by applying the continuous waveform, and achieves better high aspect ratio etching of the substrate compared to that achieved by applying the continuous waveform. For example, the mask selectivity is improved by approximately 20% or more, the etch rate is increased by approximately 40% or more, and the critical dimension is reduced by approximately 12% or more compared to that achieved using the continuous waveform.

[0012] Moreover, if direct current (DC) voltage is applied in addition to application of the multiple voltage levels and multiple frequency levels, a DC positive voltage is used in the low voltage level. Similarly, if transformer coupled plasma (TCP) pulsing is applied in addition to application of the multiple voltage levels and multiple frequency levels, a small amount of TCP power is used in the low voltage level. The application of the DC voltage or the small amount of TCP power decelerates the high energy ions of plasma within the plasma chamber. The high energy ions that are decelerated maintain a relatively narrow angular spread compared to the low energy ions generated during the continuous waveform operation of the RF bias. When the small amount of TCP power is applied, temperature of ions of plasma cools down to provide increased directionality of the low energy ions to increase an etch rate of etching the substrate.

[0013] During a transition from the low voltage level to the high voltage level while applying the multiple voltage levels and multiple frequency levels, a high amount of electric field is created in plasma within the plasma chamber. As a result of the high amount of electric field, there is an increase in energy of ions of plasma within the plasma chamber and there is a decrease in the angular spread of the ions. For example, an application of the multiple voltage levels and multiple frequency levels increases an etch rate of etching the substrate by approximately 60% and decreases the critical dimension of the substrate, such as a thickness of a channel within the substrate layer, by about 7%. Moreover, when the DC voltage is applied in addition to the multiple voltage levels and multiple frequency levels, the high energy ions lose energy due to a decrease in an amount of an electric field of plasma within the plasma chamber. The loss of energy decelerates ions of plasma within the plasma chamber and the ions do not scatter like they do in case of a negative potential sheath of plasma. As an example, the ions that lose the energy maintain an approximately 50% narrower low energy angular spread compared to the low energy ions produced by applying the continuous waveform. The application of the DC voltage produces a large population of the low energy ions with a relatively narrow angular spread at lower energies and the low energy ions enhance an etch rate of etching the substrate by, for example, approximately 60% and reduces the critical dimension, for example, of the substrate by approximately 12%, compared to the continuous waveform.

[0014] Moreover, when the multiple voltage levels and multiple frequency levels are applied in conjunction with pulsing of the TCP power, temperature of ions within the plasma chamber is reduced to preserve directionality of the ions. When the directionality of ions is preserved, an etch rate of etching the substrate increases, for example, by about 50% compared to that achieved using the continuous waveform and the critical dimension of the substrate decreases by about 16% compared to the critical dimension achieved using the continuous waveform. When the multiple voltage levels and multiple frequency levels are applied, the mask layer is eroded by, for example, about 92%, compared to erosion of the mask layer when the continuous waveform is applied. If the DC voltage is applied during a low voltage level of the multiple voltage levels, the mask layer is eroded by approximately 85% compared to erosion of the mask layer when the continuous waveform is applied. Similarly, if the small amount of TCP power is applied during the low voltage level of the multiple voltage levels, the mask layer is eroded by approximately 95% compared to erosion of the mask layer when the continuous waveform is applied.

[0015] Application of the multiple voltage levels and multiple frequency levels to a substrate support generates low energy ions with a low angular spread. Moreover, an application of the DC voltage, such a positive DC voltage, to the substrate support decelerates ions immediately after application of a high voltage level from the multiple voltage levels to the substrate support. Also, an application of the small amount of TCP power immediately after application of the high voltage level from the multiple voltage levels produces ions with low energy and low angular spread. The ions with the low energy and the low angular spread increase an etch rate of etching the substrate. The increase in the etch rate decreases the critical dimension of the substrate and increases mask selectivity of the mask layer of the substrate.

[0016] In some embodiments, a method is described. The method includes controlling an RF generator to generate an RF signal that concurrently pulses between a plurality of parameter levels and between a plurality of frequency levels during a time period. The plurality of parameter levels include a first parameter level and a second parameter level and the plurality of frequency levels include a first frequency level and a second frequency level. During the time period, a transition from the first frequency level to the second frequency level occurs in substantial synchronization with a transition from the first parameter level to the second parameter level and a transition from the second frequency level to the first frequency level occurs in substantial synchronization with a transition from the second parameter level to the first parameter level. The method further includes controlling a DC power supply to generate a DC signal that pulses between a plurality of DC parameter levels in substantial synchronization with the plurality of parameter levels of the RF signal. The plurality of DC parameter levels include a first DC parameter level and a second DC parameter level. During the time period, a transition from the first DC parameter level to the second DC parameter level occurs in substantial synchronization with a transition from the first parameter level to the second parameter level of the RF signal and a transition from the second DC parameter level to the first DC parameter level occurs in substantial synchronization with a transition from the second parameter level to the first parameter level of the RF signal.

[0017] In various embodiments, a controller is described. The controller includes a processor. The processor is configured to control an RF generator to generate an RF signal that concurrently pulses between a plurality of parameter levels and between a plurality of frequency levels during a time period. The plurality of parameter levels include a first parameter level and a second parameter level and the plurality of frequency levels include a first frequency level and a second frequency level. During the time period, a transition from the first frequency level to the second frequency level occurs in substantial synchronization with a transition from the first parameter level to the second parameter level and a transition from the second frequency level to the first frequency level occurs in substantial synchronization with a transition from the second parameter level to the first parameter level. The processor is further configured to control a DC power supply to generate a DC signal that pulses between a plurality of DC parameter levels in substantial synchronization with the plurality of parameter levels of the RF signal. The plurality of DC parameter levels include a first DC parameter level and a second DC parameter level. During the time period, a transition from the first DC parameter level to the second DC parameter level occurs in substantial synchronization with a transition from the first parameter level to the second parameter level of the RF signal and a transition from the second DC parameter level to the first DC parameter level occurs in substantial synchronization with a transition from the second parameter level to the first parameter level of the RF signal. The controller further includes a memory device coupled to the processor. [0018] In several embodiments, a system is described. The system includes an RF generator, a DC power supply, and a controller coupled to the RF generator and the DC power supply. The controller is configured to control the RF generator to generate an RF signal that concurrently pulses between a plurality of parameter levels and between a plurality of frequency levels during a time period. The plurality of parameter levels include a first parameter level and a second parameter level and the plurality of frequency levels include a first frequency level and a second frequency level. During the time period, a transition from the first frequency level to the second frequency level occurs in substantial synchronization with a transition from the first parameter level to the second parameter level and a transition from the second frequency level to the first frequency level occurs in substantial synchronization with a transition from the second parameter level to the first parameter level. The controller is configured control the DC power supply to generate a DC signal that pulses between a plurality of DC parameter levels in substantial synchronization with the plurality of parameter levels of the RF signal. The plurality of DC parameter levels include a first DC parameter level and a second DC parameter level. During the time period, a transition from the first DC parameter level to the second DC parameter level occurs in substantial synchronization with a transition from the first parameter level to the second parameter level of the RF signal and a transition from the second DC parameter level to the first DC parameter level occurs in substantial synchronization with a transition from the second parameter level to the first parameter level of the RF signal.

[0019] In some embodiments, a method is described. The method includes controlling a first RF generator to generate a first RF signal that concurrently pulses between a plurality of parameter levels and between a plurality of frequency levels during a time period. The plurality of parameter levels include a first parameter level and a second parameter level. The plurality of frequency levels include a first frequency level and a second frequency level. During the time period, a transition from the first frequency level to the second frequency level occurs in substantial synchronization with a transition from the first parameter level to the second parameter level and a transition from the second frequency level to the first frequency level occurs in substantial synchronization with a transition from the second parameter level to the first parameter level. The method further includes controlling a second RF generator to generate a second RF signal that pulses between a plurality of parameter levels in substantial synchronization with the plurality of parameter levels of the first RF signal. The plurality of parameter levels of the second RF signal include a first parameter level and a second parameter level. During the time period, a transition from the first parameter level of the second RF signal to the second parameter level of the second RF signal occurs in substantial synchronization with a transition from the first parameter level of the first RF signal to the second parameter level of the first RF signal and a transition from the second parameter level of the second RF signal to the first parameter level of the second RF signal occurs in substantial synchronization with a transition from the second parameter level of the first RF signal to the first parameter level of the first RF signal.

[0020] In several embodiments, a controller is described. The controller includes a processor configured to control a first RF generator to generate a first RF signal that concurrently pulses between a plurality of parameter levels and between a plurality of frequency levels during a time period. The plurality of parameter levels include a first parameter level and a second parameter level and the plurality of frequency levels include a first frequency level and a second frequency level. During the time period, a transition from the first frequency level to the second frequency level occurs in substantial synchronization with a transition from the first parameter level to the second parameter level and a transition from the second frequency level to the first frequency level occurs in substantial synchronization with a transition from the second parameter level to the first parameter level. The processor is further configured to control a second RF generator to generate a second RF signal that pulses between a plurality of parameter levels in substantial synchronization with the plurality of parameter levels of the first RF signal. The plurality of parameter levels of the second RF signal include a first parameter level and a second parameter level. During the time period, a transition from the first parameter level of the second RF signal to the second parameter level of the second RF signal occurs in substantial synchronization with a transition from the first parameter level of the first RF signal to the second parameter level of the first RF signal and a transition from the second parameter level of the second RF signal to the first parameter level of the second RF signal occurs in substantial synchronization with a transition from the second parameter level of the first RF signal to the first parameter level of the first RF signal. The controller includes a memory device coupled to the processor.

[0021] In several embodiments, a system is described. The system includes a first RF generator, a second RF generator, and a controller coupled to the first RF generator and the second RF generator. The controller is configured to control the first RF generator to generate a first RF signal that concurrently pulses between a plurality of parameter levels and between a plurality of frequency levels during a time period. The plurality of parameter levels include a first parameter level and a second parameter level and the plurality of frequency levels include a first frequency level and a second frequency level. During the time period, a transition from the first frequency level to the second frequency level occurs in substantial synchronization with a transition from the first parameter level to the second parameter level and a transition from the second frequency level to the first frequency level occurs in substantial synchronization with a transition from the second parameter level to the first parameter level. The controller is further configured to control the second RF generator to generate a second RF signal that pulses between a plurality of parameter levels in substantial synchronization with the plurality of parameter levels of the first RF signal. The plurality of parameter levels of the second RF signal include a first parameter level and a second parameter level. During the time period, a transition from the first parameter level of the second RF signal to the second parameter level of the second RF signal occurs in substantial synchronization with a transition from the first parameter level of the first RF signal to the second parameter level of the first RF signal and a transition from the second parameter level of the second RF signal to the first parameter level of the second RF signal occurs in substantial synchronization with a transition from the second parameter level of the first RF signal to the first parameter level of the first RF signal.

[0022] Other aspects will become apparent from the following detailed description, taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The embodiments may best be understood by reference to the following description taken in conjunction with the accompanying drawings.

[0024] Figure 1 is a diagram of an embodiment of a system to illustrate an application of multi-level parameter pulsing and multi-level frequency pulsing.

[0025] Figure 2A shows embodiments of graphs to illustrate three-level pulsing of a parameter of a radio frequency (RF) signal generated by an RF generator and two-level pulsing of a frequency of the RF signal.

[0026] Figure 2B shows embodiments of graphs to illustrate reverse two-level pulsing of the frequency of the RF signal compared to the three-level pulsing of the parameter of the RF signal.

[0027] Figure 3A shows embodiments of graphs to illustrate four-level pulsing of the parameter of the RF signal and two-level pulsing of the frequency of the RF signal.

[0028] Figure 3B shows embodiments of the graphs to illustrate reverse two-level pulsing of the frequency of the RF signal compared to the four-level pulsing of the parameter of the RF signal. [0029] Figure 3C shows embodiments of graphs to illustrate two-level pulsing of the frequency of the RF signal and four-level pulsing of the parameter of the RF signal.

[0030] Figure 3D shows embodiments of graphs to illustrate reverse two-level pulsing of the frequency of the RF signal compared to four-level pulsing of the parameter of the RF signal.

[0031] Figure 4A shows embodiments of graphs to illustrate five-level pulsing of the parameter of the RF signal and two-level pulsing of the frequency of the RF signal.

[0032] Figure 4B shows embodiments of graphs to illustrate reverse two-level pulsing of the frequency of the RF signal compared to five-level pulsing of the parameter of the RF signal.

[0033] Figure 5A is an embodiment of a graph to illustrate an angular distribution of ions of plasma within a plasma reactor when a continuous wave voltage signal of 200 volts is applied as a bias voltage to a wafer support.

[0034] Figure 5B is an embodiment of a graph to illustrate the angular distribution of ions of plasma within the plasma reactor when a continuous wave voltage signal of 400 volts is applied as the bias voltage to the wafer support.

[0035] Figure 5C is an embodiment of a graph to illustrate the angular distribution of ions of plasma within the plasma reactor when a continuous wave voltage signal of 800 volts is applied as the bias voltage to the wafer support.

[0036] Figure 5D is an embodiment of a graph to illustrate the angular distribution of ions of plasma within the plasma reactor when a continuous wave voltage signal of 1600 volts is applied as the bias voltage to the wafer support.

[0037] Figure 5E is an embodiment of a graph to illustrate a decrease in the angular distribution with an increase in a voltage of a continuous wave signal.

[0038] Figure 5F is an embodiment of a graph to illustrate an energy of ions of plasma within the plasma reactor versus the angular distribution when a continuous wave voltage signal of 300 volts is applied to the wafer support.

[0039] Figure 5G is an embodiment of a graph to illustrate an energy of ions of plasma within a plasma chamber when two-level pulsing of the parameter of the RF signal is applied to a substrate support and the RF signal has a constant frequency level.

[0040] Figure 5H an embodiment of a graph to illustrate an energy of ions of plasma within the plasma chamber when three-level pulsing of the parameter of the RF signal is applied to the substrate support and the RF signal has the constant frequency level. [0041] Figure 51 is an embodiment of a graph to illustrate an energy of ions of plasma within the plasma chamber when three-level pulsing of the parameter of the RF signal is applied to the substrate support in addition to applying two-level pulsing of the frequency of the RF signal.

[0042] Figure 5J is an embodiment of a graph to illustrate an energy of ions of plasma within the plasma chamber when five-level pulsing of the parameter of the RF signal is applied to the substrate support and the RF signal has the constant frequency level.

[0043] Figure 5 K is an embodiment of a graph to illustrate a comparison between the angular distribution achieved using a continuous wave voltage signal and an angular spread achieved using multi-level pulsing of the parameter of the RF signal.

[0044] Figure 6A is an embodiment of a graph that is generated when a continuous wave voltage signal is applied to the wafer support of the plasma reactor.

[0045] Figure 6B is an embodiment of a graph that is generated when the five- level pulsing of the parameter of the RF signal and the constant frequency level of the RF signal are applied to the substrate support.

[0046] Figure 6C is an embodiment of a graph that is generated when the five- level pulsing of the parameter of the RF signal and the constant frequency level of the RF signal are applied to the substrate support.

[0047] Figure 6D is an embodiment of a graph that is generated when the three- level pulsing of the parameter of the RF signal and the two-level pulsing of the frequency of the RF signal are applied to the substrate support.

[0048] Figure 6E is an embodiment of a graph that is generated when the three- level pulsing of the parameter of the RF signal and the two-level pulsing of the frequency of the RF signal are applied to the substrate support.

[0049] Figure 6F is an embodiment of a graph that is generated when the five- level pulsing of the parameter of the RF signal and the two-level pulsing of the frequency of the RF signal are applied to the substrate support.

[0050] Figure 7 A is an embodiment of a graph that is generated when a continuous wave voltage signal is applied to the wafer support of the plasma reactor.

[0051] Figure 7B is an embodiment of a graph that is generated when the two- level pulsing of the parameter of the RF signal and the constant frequency level of the RF signal are applied to the substrate support. [0052] Figure 7C is an embodiment of a graph that is generated when the two- level pulsing of the parameter of the RF signal and the constant frequency level of the RF signal are applied to the substrate support.

[0053] Figure 7D is an embodiment of a graph that is generated when the three- level pulsing of the parameter of the RF signal and the two-level pulsing of the frequency of the RF signal are applied to the substrate support.

[0054] Figure 7E is an embodiment of a graph that is generated when the five- level pulsing of the parameter of the RF signal and the two-level pulsing of the frequency of the RF signal are applied to the substrate support.

[0055] Figure 8A is an embodiment of a graph that plots a direct current (DC) bias at the substrate support versus time t when the two-level pulsing of the parameter and the constant frequency level are applied to the substrate support.

[0056] Figure 8B is an embodiment of a graph that plots the DC bias at the substrate support versus the time t when the three-level pulsing of the parameter and the constant frequency level are applied to the substrate support.

[0057] Figure 8C is an embodiment of a graph that plots the DC bias at the substrate support versus the time t when the three-level pulsing of the parameter and the two- level pulsing of the frequency level are applied to the substrate support.

[0058] Figure 8D is an embodiment of a graph that plots the DC bias at the substrate support versus the time t when the five-level pulsing of the parameter and the constant frequency level are applied to the substrate support.

[0059] Figure 9A is an embodiment of a graph to illustrate a sheath voltage of plasma formed within the plasma reactor when a continuous wave voltage signal is applied to the wafer support.

[0060] Figure 9B is an embodiment of a graph to illustrate a sheath voltage of plasma formed within the plasma chamber when the two-level pulsing of the parameter and the constant frequency level are applied to the substrate support.

[0061] Figure 9C is an embodiment of a graph to illustrate a sheath voltage of plasma formed within the plasma chamber when the four-level pulsing of the parameter and the constant frequency level are applied to the substrate support.

[0062] Figure 10A is an embodiment of a graph that plots the DC bias at the substrate support by the RF signal versus the time t when multi-level pulsing of the parameter and the constant frequency level are applied to the substrate support. [0063] Figure 10B is an embodiment of a graph that plots the DC bias at the substrate support by the RF signal versus the time t when multi-level pulsing of the parameter and the two-level pulsing of the frequency are applied to the substrate support.

[0064] Figure 11A is an embodiment of a graph that plots a vertical distance across a wafer versus a horizontal distance across the wafer when a continuous wave voltage signal is applied to the wafer support of the plasma reactor.

[0065] Figure 11B is an embodiment of a graph that plots the vertical distance across a substrate versus the horizontal distance across the substrate when the two-level pulsing of the parameter of the RF signal and the constant frequency level are applied to the substrate support.

[0066] Figure 11C is an embodiment of a graph that plots the vertical distance across the substrate versus the horizontal distance across the substrate when the three-level pulsing of the parameter of the RF signal and the constant frequency level are applied to the substrate support.

[0067] Figure 11D is an embodiment of a graph that plots the vertical distance across the substrate versus the horizontal distance across the substrate when the three-level pulsing of the parameter of the RF signal and the two-level pulsing of the frequency of the RF signal are applied to the substrate support.

[0068] Figure 11E is an embodiment of a graph that plots the vertical distance across the substrate versus the horizontal distance across the substrate when the five-level pulsing of the parameter of the RF signal and the constant frequency level of the RF signal are applied to the substrate support.

[0069] Figure 11F is an embodiment of a graph that plots the vertical distance across a mask layer of the substrate versus the horizontal distance across the mask layer of the substrate when the mask layer is not processed.

[0070] Figure 11G is an embodiment of a graph that plots the vertical distance across the mask layer versus the horizontal distance across the mask layer when a continuous wave voltage signal is applied to the wafer support of the plasma reactor.

[0071] Figure 11H is an embodiment of a graph that plots the vertical distance across the mask layer versus the horizontal distance across the mask layer when the two-level pulsing of the parameter of the RF signal and the constant frequency level are applied to the substrate support.

[0072] Figure 111 is an embodiment of a graph that plots the vertical distance across the mask layer versus the horizontal distance across the mask layer when the three- level pulsing of the parameter of the RF signal and the constant frequency level are applied to the substrate support.

[0073] Figure 11J is an embodiment of a graph that plots the vertical distance across the mask layer versus the horizontal distance across the mask layer when the three- level pulsing of the parameter of the RF signal and the two-level pulsing of the frequency of the RF signal are applied to the substrate support.

[0074] Figure 11K is an embodiment of a graph that plots the vertical distance across the mask layer versus the horizontal distance across the mask layer when the five-level pulsing of the parameter of the RF signal and the constant frequency level of the RF signal are applied to the substrate support.

[0075] Figure 11L is an embodiment of a graph to illustrate a decrease in mask erosion when multi-level pulsing of the parameter of the RF signal is applied in conjunction with the constant frequency level or multi-level pulsing of the parameter is applied in conjunction with the two-level pulsing of the frequency of the RF signal.

[0076] Figure 12 is a diagram of an embodiment of a system to illustrate a supply of a DC signal to the substrate support while multi-level pulsing of the parameter of the RF signal is applied to the substrate support.

[0077] Figure 13A shows an embodiment of a graph to illustrate an example of a digital pulse signal of figure 12 and an embodiment of a graph to illustrate an example of the parameter of the DC signal of figure 12.

[0078] Figure 13B shows an embodiment of a graph to illustrate an example of the digital pulse signal of figure 12 and an embodiment of a graph to illustrate an example of the parameter of the DC signal of figure 12.

[0079] Figure 13C shows an embodiment of a graph to illustrate an example of the digital pulse signal of figure 12 and an embodiment of a graph to illustrate an example of the parameter of the DC signal of figure 12.

[0080] Figure 14A is a diagram of an embodiment of a system to illustrate multi level pulsing of the parameter of an RF signal that is generated by an RF generator coupled to a transformer coupled plasma (TCP) coil.

[0081] Figure 14B is a block diagram of an embodiment of the RF generator of figure 14A to illustrate components of the RF generator.

[0082] Figure 15 A shows an embodiment of a graph and an embodiment of another graph to illustrate pulsing of the parameter of the RF signal generated by the RF generator of figure 14A. [0083] Figure 15B shows an embodiment of a graph and an embodiment of another graph to illustrate pulsing of the parameter of the RF signal generated by the RF generator of figure 14A.

[0084] Figure 15C shows an embodiment of a graph and an embodiment of yet another graph to illustrate pulsing of the parameter of the RF signal generated by the RF generator of figure 14A.

[0085] Figure 16A is an embodiment of the graph of figure 5F.

[0086] Figure 16B is an embodiment of a graph to illustrate that the angular spread of ions of plasma within the plasma chamber decreases when the five-level pulsing of the parameter and the two-level pulsing of the frequency of the RF signal are applied to the substrate support.

[0087] Figure 16C is an embodiment of a graph to illustrate that the angular spread of ions of plasma within the plasma chamber decreases when the four-level pulsing of the parameter and the two-level pulsing of the frequency are applied to the substrate support, and the DC signal pulses between two DC parameter levels.

[0088] Figure 16D is an embodiment of a graph to illustrate that the angular spread of ions of plasma within the plasma chamber decreases when the four-level pulsing of the parameter and the two-level pulsing of the frequency are applied to the substrate support, and the RF signal applied to the TCP coil pulses between two parameter levels.

[0089] Figure 16E is an embodiment of the graph of figure 11 A.

[0090] Figure 16F is an embodiment of a graph that plots the vertical distance across the substrate versus the horizontal distance across the substrate when the five-level pulsing of the parameter and the two-level pulsing of the frequency are applied to the substrate support.

[0091] Figure 16G is an embodiment of a graph that plots the vertical distance across the substrate versus the horizontal distance across the substrate when the four-level pulsing of the parameter and the two-level pulsing of the frequency are applied to the substrate support and the DC signal pulses between the two DC parameter levels.

[0092] Figure 16H is an embodiment of a graph that plots the vertical distance across the substrate versus the horizontal distance across the substrate when the five-level pulsing of the parameter and the two-level pulsing of the frequency are applied to the substrate support in conjunction with the pulsing of the parameter of the RF signal generated by the RF generator of figure 14 A.

[0093] Figure 17A is an embodiment of the graph of figure 11F. [0094] Figure 17B is an embodiment of the graph of figure 11G.

[0095] Figure 17C is an embodiment of a graph that plots the vertical distance of a mask layer of the substrate versus the horizontal distance of the mask layer when the five- level pulsing of the parameter and the two-level pulsing of the frequency are applied to the substrate support.

[0096] Figure 17D is an embodiment of a graph that plots the vertical distance of a mask layer of the substrate versus the horizontal distance of the mask layer when the four- level pulsing of the parameter and the two-level pulsing of the frequency are applied to the substrate support in addition to applying the DC signal that pulses between the two DC parameter levels.

[0097] Figure 17E is an embodiment of a graph that plots the vertical distance of a mask layer of the substrate versus the horizontal distance of the mask layer when the five- level pulsing of the parameter and the two-level pulsing of the frequency are applied to the substrate support in addition to pulsing of the parameter of the RF signal generated by the RF generator of figure 14A.

DETAILED DESCRIPTION

[0098] The following embodiments describe systems and methods for multi-level parameter and multi-level frequency pulsing of a radio frequency (RF) signal that is applied to a substrate support in conjunction with multi-level pulsing of a direct current (DC) signal or a radio frequency (RF) signal to achieve a low angular spread. It will be apparent that the present embodiments may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present embodiments.

[0099] Figure 1 is a diagram of an embodiment of a system 100 to illustrate an application of multi-level parameter pulsing and multi-level frequency pulsing. The system 100 includes an RF generator RFGA, and impedance match 104, a plasma chamber 112, another impedance match 120, another RF generator RFGB, a host computer 106, an RF cable 128, an RF transmission line 126, another RF cable 130, and another RF transmission line 132. Examples of the host computer 106 include a desktop computer, laptop computer, a server, a controller, a tablet, and a smart phone.

[00100] An impedance match, as described herein, includes a network of one or more resistors, or one or more capacitors, or one or more inductors, or a combination thereof, to match an impedance of a load coupled to an output of the impedance match with an impedance of a source coupled to an input of the impedance match. Examples of the load coupled to an output of impedance match 104 include the plasma chamber 112 and the RF transmission line 126. Moreover, examples of the source coupled to an input of the impedance match 104 include the RF cable 128 and the RF generator RFGA.

[00101] The host computer 106 includes a processor 108 and a memory device 110. As used herein, a processor is an application specific integrated circuit (ASIC), or a programmable logic device (PLD), or a central processing unit (CPU), or a microprocessor, or a microcontroller. As used herein, a controller is ASIC, or a PLD, or a CPU, or a microprocessor, or a microcontroller, or a processor. Examples of a memory device include a random access memory (RAM) and a read-only memory (ROM). To illustrate, a memory device is a flash memory, a hard disk, or a storage device, etc. A memory device is an example of a computer-readable medium.

[00102] The plasma chamber 112 includes a substrate support 114 on which a substrate 118 is placed for processing. The plasma chamber 112 further includes a dielectric window 134. Examples of the substrate support 114 include an electrostatic chuck and a wafer platen. The substrate support 114 includes a lower electrode, which is made from a metal, such as aluminum or an alloy of aluminum. A transformer coupled plasma (TCP) coil is situated outside the plasma chamber 112 over the dielectric window 134.

[00103] The RF generator RFGA includes a digital signal processor DSPA and multiple parameter controllers PRAS(n-N), PRAS(n-l), and PRAS(n), where N is an integer greater than zero. Examples of a parameter, as used herein, include voltage and power. The RF generator RFGA further includes multiple frequency controllers FCS(m-M) and FCS(m), where M is an integer greater than zero, such as 2, 3, 4, or 5. The RF generator RFGA further includes a driver system DRVRA and an RF power supply 102. An example of a driver system, as used herein, include one or more transistors. Another example of the driver system, as used herein, include one or more transistors that are coupled to an amplifier. An example of an RF power supply, as used herein, include an RF oscillator that generates a sinusoidal signal at a radio frequency, such as ranging from and including 400 kilohertz (kHz) to 100 megahertz (100 MHz).

[00104] The digital signal processor DSPA is coupled to the parameter controllers PRAS(n-N) through PRAS(n) and to the frequency controllers FCS(m-M) through FCS(m). Each of the parameter controllers PRAS(n-N) through PRAS(n) and to the frequency controllers FCS(m-M) through FCS(m) is coupled to the driver system DRVRA and the driver system DRVRA is coupled to the RF power supply 102. The processor 108 is coupled to the memory device 110 and to the digital signal processor DSPA. [00105] The RF power supply 102 is coupled to the input of impedance match 104 via the RF cable 112. The output of the impedance match 102 is coupled to the substrate support 114. The RF generator RFGB includes an RF power supply that is coupled via the RF cable 132 the impedance match 120 and impedance match 120 is coupled via the RF transmission line 132 to a TCP coil 116.

[00106] The RF power supply of the RF generator RFGB generates an RF signal 144, such as a sinusoidal signal, and supplies the RF signal 144 via the RF cable 130 to the impedance match 120. For example, the processor 108 sends via a connection medium 148 a parameter level and a frequency level of the RF signal 144 to the RF generator RFGB. The connection medium 148 couples the processor 108 to the RF generator RFGB. Upon receiving the parameter level and the frequency level from the processor 108, the RF generator RFGB generates the RF signal 144 having the parameter level and the frequency level. An example of a connection medium, as used herein, is a conductor or a group of conductors. To illustrate, a connection medium is a serial transfer cable, a parallel transfer cable, or a Universal Serial Bus (USB) cable.

[00107] The RF signal 144 is a continuous wave signal. For example, the RF signal 144 is not pulsed from one state to another. As another example, all power magnitudes of the parameter level of the RF signal 144 are within a predefined range, such as 18%, 19%, or 20%. To illustrate, a lowest parameter magnitude of the parameter level of the RF signal 144 is 20% lower than a highest parameter magnitude of the parameter level of the RF signal 144. As yet another example, the RF signal 144 has a single parameter level.

[00108] The impedance match 120 matches an impedance of a load, such as the RF transmission line 132 and the plasma chamber 112, coupled to an output of impedance match 120 which an impedance of a source, such as the RF cable 130 and the RF generator RFGB, coupled to an input of the impedance match 120 to generate a modified RF signal 146. The modified RF signal 146 is generated from the RF signal 144 received via the RF cable 130. The modified RF signal output from the impedance match 120 is supplied via the RF transmission line 132 to the TCP coil 116.

[00109] Moreover, the processor 108 generates a digital pulse signal 136, such as a clock signal, and provides the digital pulse signal 136 to the digital signal processor DSPA. Moreover, the processor 108 generates another digital pulse signal 138 and provides the digital pulse signal 138 to the digital signal processor DSPA. The digital pulse signal 136 is supplied via a connection medium 142 the digital signal processor DSPA. Similarly, the digital pulse signal 138 is supplied via another connection medium 142 to the digital signal processor DSPA. The connection medium 140 couples the processor 108 to the digital signal processor DSPA and the connection medium 142 couples the processor 108 to the digital signal processor DSPA.

[00110] Upon receiving the digital pulse signal 136, the digital signal processor DSPA identifies an occurrence of a state of the digital pulse signal 136. For example, the digital signal processor DSPA determines whether a logic level of the digital pulse signal 136 is greater or lower than a predetermined threshold. Upon determining that the logic level of the digital pulse signal 136 is greater than the predetermined threshold, the digital signal processor DSPA identifies an occurrence of the state of the digital pulse signal 136 to be Sl. On the other hand, upon determining that the logic level of the digital pulse signal 136 is less than the predetermined threshold, the digital signal processor DSPA identifies an occurrence of the state of the digital pulse signal 136 to be SO. As another example, the digital signal processor DSPA determines whether the logic level of the digital pulse signal 136 is zero or one. Upon determining that the logic level of the digital pulse signal 136 is one, the digital signal processor DSPA identifies the occurrence of the state of the digital pulse signal 136 to be Sl. On the other hand, upon determining that the logic level of the digital pulse signal 136 is zero, the digital signal processor DSPA identifies the occurrence of the state of the digital pulse signal 136 to be SO.

[00111] Similarly, upon receiving the digital pulse signal 138, the digital signal processor DSPA identifies an occurrence of a state of the digital pulse signal 138. For example, when the digital pulse signal 138 has five states, the digital signal processor DSPA determines whether a logic level of the digital pulse signal 138 is within a first predetermined range, a second predetermined range, a third predetermined range, a fourth predetermined range, or a fifth predetermined range. Upon determining that the logic level of the digital pulse signal 138 is within the first predetermined range, the digital signal processor DSPA identifies an occurrence of the state of the digital pulse signal 138 to be Sl. Similarly, upon determining that the logic level of the digital pulse signal 138 is within the second predetermined range, the digital signal processor DSPA identifies an occurrence of the state of the digital pulse signal 138 to be S2. Moreover, upon determining that the logic level of the digital pulse signal 138 is within the third predetermined range, the digital signal processor DSPA identifies an occurrence of the state of the digital pulse signal 138 to be S3. Also, upon determining that the logic level of the digital pulse signal 138 is within the force predetermined range, the digital signal processor DSPA identifies an occurrence of the state of the digital pulse signal 138 to be S4. Upon determining that the logic level of the digital pulse signal 138 is within the fifth predetermined range, the digital signal processor DSPA identifies an occurrence of the state of the digital pulse signal 138 to be S5.

[00112] As another example, when the digital pulse signal 138 has five states, the digital signal processor DSPA determines whether the logic level of the digital pulse signal 138 is 1, 2, 3, 4, or 5. Upon determining that the logic level of the digital pulse signal 138 is one, the digital pulse signal DSPA identifies the occurrence of the state of the digital pulse signal 138 to be Sl. Similarly, upon determining that the logic level of the digital pulse signal 138 is two, the digital pulse signal DSPA identifies the occurrence of the state of the digital pulse signal 138 to be S2. Also, upon determining that the logic level of the digital pulse signal 138 is three, the digital signal processor DSPA identifies the occurrence of the state of the digital pulse signal 138 to be S3. Moreover, upon determining that the logic level of the digital pulse signal 138 is four, the digital signal processor DSPA identifies the occurrence of the state of the digital pulse signal 138 to be S4. Upon determining that the logic level of the digital pulse signal 138 is five, the digital signal processor DSPA identifies the occurrence of the state of the digital pulse signal 138 to be S5.

[00113] In response to identifying the occurrence of the state of the digital pulse signal 136 to be SO, the digital signal processor DSPA sends a signal to the frequency controller FCS(m-M). Upon receiving the signal during the occurrence of the state SO of the digital pulse signal 136, the frequency controller FCS(m-M) accesses a frequency level stored within the frequency controller FCS(m-M) and provides the frequency level to the driver system DRVRA. It should be noted that a frequency level is stored within a frequency controller, described herein, within a memory device of the frequency controller and the frequency level is accessed by a processor of the frequency controller from the memory device of the frequency controller. Examples of the frequency level stored within the frequency controller FCS(m-M) include a frequency level fl, which is further described below.

[00114] Similarly, in response to identifying the occurrence of the state of the digital pulse signal 136 to be Sl, the digital signal processor DSPA sends a signal to the frequency controller FCS(m). Upon receiving the signal during the occurrence of the state SO of the digital pulse signal 136, the frequency controller FCS(m) accesses a frequency level stored within the frequency controller FCS(m) and provides the frequency level to the driver system DRVRA. Examples of the frequency level stored within the frequency controller FCS(m) include a frequency level f2, which is further described below. [00115] Moreover, in response to identifying the occurrence of the state of the digital pulse signal 138 to be Sl, the digital signal processor DSPA sends a signal to the parameter controller PRAS(n-N). Upon receiving the signal during the occurrence of the state

51 of the digital pulse signal 138, the parameter controller PRAS(n-N) accesses a parameter level stored within the parameter controller PRAS(n-N) and provides the parameter level to the driver system DRVRA. Examples of the parameter level, for the state Sl of the digital pulse signal 138, stored within the parameter controller PRAS(n-N) include parameter levels PR1 (figures 2A and 2B), PR11 (figures 3A-3D), and PR111 (figures 4A and 4B), which are further described below.

[00116] Similarly, in response to identifying the occurrence of the state of the digital pulse signal 138 to be S2, the digital signal processor DSPA sends a signal to the parameter controller PRAS(n-3). Upon receiving the signal during the occurrence of the state

52 of the digital pulse signal 138, the parameter controller PRAS(n-3) accesses a parameter level stored within the parameter controller PRAS(n-3) and provides the parameter level to the driver system DRVRA. Examples of the parameter level, for the state S2 of the digital pulse signal 138, stored within the parameter controller PRAS(n-3) include parameter levels PR2 (figures 2A and 2B), PR21 (figures 3A-3D), and PR211 (figures 4A and 4B), which are further described below.

[00117] Also, in response to identifying the occurrence of the state of the digital pulse signal 138 to be S3, the digital signal processor DSPA sends a signal to the parameter controller PRAS(n-2). Upon receiving the signal during the occurrence of the state S3 of the digital pulse signal 138, the parameter controller PRAS(n-2) accesses a parameter level stored within the parameter controller PRAS(n-2) and provides the parameter level to the driver system DRVRA. Examples of the parameter level, for the state S3 of the digital pulse signal 138, stored within the parameter controller PRAS(n-2) include parameter levels PR3 (figures 2A and 2B), PR31 (figures 3A-3D), and PR311 (figures 4A and 4B), which are further described below.

[00118] Furthermore, in response to identifying the occurrence of the state of the digital pulse signal 138 to be S4, the digital signal processor DSPA sends a signal to the parameter controller PRAS(n-l). Upon receiving the signal during the occurrence of the state S4 of the digital pulse signal 138, the parameter controller PRAS(n-l) accesses a parameter level stored within the parameter controller PRAS(n-l) and provides the parameter level to the driver system DRVRA. Examples of the parameter level, for the state S4 of the digital pulse signal 138, stored within the parameter controller PRAS(n-l) include parameter levels PR41 (figures 3A-3D) and PR411 (figures 4A and 4B), which are further described below.

[00119] In response to identifying the occurrence of the state of the digital pulse signal 138 to be S5, the digital signal processor DSPA sends a signal to the parameter controller PRAS(n). Upon receiving the signal during the occurrence of the state S5 of the digital pulse signal 138, the parameter controller PRAS(n) accesses a parameter level stored within the parameter controller PRAS(n) and provides the parameter level to the driver system DRVRA. An example of the parameter level stored, for the state S5 of the digital pulse signal 138, within the parameter controller PRAS(n) includes a parameter level PR511 (figures 4 A and 4B), which is further described below.

[00120] During the occurrence of the state Sl of the digital pulse signal 138, the driver system DRVRA generates a current signal based on the parameter level PR1, PR11, or PR111, and provides the current signal to the RF power supply 102. Also, the RF power supply 102 generates an RF signal 122 upon receiving the current signal from the driver system DRVRA during the occurrence of the state Sl of the digital pulse signal 138. The RF signal 122 has the parameter level PR1, PR11, or PR111 during the occurrence of the state Sl of the digital pulse signal 138.

[00121] Similarly, during the occurrence of the state S2 of the digital pulse signal 138, the driver system DRVRA generates the current signal based on the parameter level PR2, PR21, or PR211, and provides the current signal to the RF power supply 102. Also, the RF power supply 102 generates the RF signal 122 upon receiving the current signal from the driver system DRVRA during the occurrence of the state S2 of the digital pulse signal 138. The RF signal 122 has the parameter level PR2, PR21, or PR211 during the occurrence of the state S2 of the digital pulse signal 138.

[00122] Moreover, during the occurrence of the state S3 of the digital pulse signal 138, the driver system DRVRA generates the current signal based on the parameter level PR3, PR31, or PR311, and provides the current signal to the RF power supply 102. Also, the RF power supply 102 generates the RF signal 122 upon receiving the current signal from the driver system DRVRA during the occurrence of the state S3 of the digital pulse signal 138. The RF signal 122 has the parameter level PR3, PR31, or PR311 during the occurrence of the state S3 of the digital pulse signal 138.

[00123] Furthermore, during the occurrence of the state S4 of the digital pulse signal 138, the driver system DRVRA generates the current signal based on the parameter level PR41 or PR411, and provides the current signal to the RF power supply 102. Also, the RF power supply 102 generates the RF signal 122 upon receiving the current signal from the driver system DRVRA during the occurrence of the state S4 of the digital pulse signal 138. The RF signal 122 has the parameter level PR41 or PR411 during the occurrence of the state S4 of the digital pulse signal 138.

[00124] Moreover, during the occurrence of the state S5 of the digital pulse signal 138, the driver system DRVRA generates the current signal based on the parameter level PR511, and provides the current signal to the RF power supply 102. Also, the RF power supply 102 generates the RF signal 122 upon receiving the current signal from the driver system DRVRA during the occurrence of the state S5 of the digital pulse signal 138. The RF signal 122 has the parameter level PR511 during the occurrence of the state S5 of the digital pulse signal 138.

[00125] During the occurrence of the state SO of the digital pulse signal 136, the driver system DRVRA generates the current signal based on the frequency level fO, and provides the current signal to the RF power supply 102. Also, the RF power supply 102 generates the RF signal 122 upon receiving the current signal from the driver system DRVRA during the occurrence of the state SO of the digital pulse signal 136. The RF signal 122 has the frequency level fO during the occurrence of the state SO of the digital pulse signal 136.

[00126] Similarly, during the occurrence of the state Sl of the digital pulse signal 136, the driver system DRVRA generates the current signal based on the frequency level fl, and provides the current signal to the RF power supply 102. Also, the RF power supply 102 generates the RF signal 122 upon receiving the current signal from the driver system DRVRA during the occurrence of the state Sl of the digital pulse signal 136. The RF signal 122 has the frequency level fl during the occurrence of the state Sl of the digital pulse signal 136.

[00127] The impedance match 104 receives the RF signal 122 via the RF cable 128 and matches an impedance of the load coupled to the output of the impedance match 104 with that of the source coupled to the input of the impedance match 104 to generate a modified RF signal 124. The modified RF signal 124 is supplied from the output of the impedance match 104 to the substrate support 114. For example, the modified RF signal 124 is supplied by the RF transmission line 126 to the lower electrode of the substrate support 114.

[00128] When one or more process gases are supplied to the plasma chamber 122 in addition to supplying the modified RF signal 146 and the modified RF signal 124, plasma is stricken or maintained within the plasma chamber 112 to process the substrate 118. Examples of the one or more process gases include an oxygen-containing gas, such as 0 ₂ . Other examples of the one or more process gases include a fluorine-containing gas, e.g., tetrafluoromethane (CF ₄ ), sulfur hexafluoride (SF ₆ ), hexafluoroethane (C ₂ F ₆ ), etc. Examples of processing the substrate 119 includes depositing a material on the substrate 118, etching the substrate 118, cleaning the substrate 118, and sputtering the substrate 118.

[00129] In some embodiments, an impedance match, as described herein is referred to as an impedance matching circuit or an impedance matching network.

[00130] In various embodiments, any number of TCP coils, such as two or three or four, located over the dielectric window 134. In some embodiments, one or more TCP coils are located next to a sidewall of the plasma chamber 112.

[00131] In several embodiments, instead of the plasma chamber 112 being a TCP plasma chamber, a capacitively coupled plasma (CCP) chamber is used. The CCP chamber includes an upper electrode, such as a capacitive plate, and the chuck. The chuck faces the upper electrode. The upper electrode is coupled to the RF transmission line 132. The upper electrode is made of a metal, such as aluminum or an alloy of aluminum.

[00132] In some embodiments, the parameter controllers PRAS(n-N) through PRAS(n), the frequency controllers FCS(m-M) through FCS(m), and the digital signal processor DSPA are parts of a controller of the RF generator RFGA. For example, functions, described herein, as performed by the parameter controllers PRAS(n-N) through PRAS(n), the frequency controllers FCS(m-M) through FCS(m), and the digital signal processor DSPA are performed by the controller of the RF generator RFGA.

[00133] In various embodiments, instead of the processor 108, a clock source, such as a clock oscillator or an electronic oscillator, generates the digital pulse signal 136.

[00134] In several embodiments, the TCP coil 116 is considered to be a part of the plasma chamber 112.

[00135] In some embodiments, when the digital pulse signal 138 has three states Sl through S3 without the states S4 and S5, the digital signal processor DSPA identifies the three states to be Sl, S2, and S3 in the same manner in which the digital pulse signal identifies the five states of the digital pulse signal 138 except that the digital signal processor DSPA does not identify the states S4 and S5. Moreover, in various embodiments, when the digital pulse signal 138 has four states Sl through S4 without the state S5, the digital signal processor DSPA identifies the four states to be Sl, S2, S3, and S4 in the same manner in which the digital pulse signal identifies the five states of the digital pulse signal 138 except that the digital signal processor DSPA does not identify the state S5.

[00136] In various embodiments, when the digital pulse signal 138 has three states Sl through S3 without the states S4 and S5, in response to identifying the occurrence of the state of the digital pulse signal 138 to be Sl, S2, or S3, the digital signal processor DSPA sends a signal to a corresponding one of the parameter controllers PRAS(n-N), PRAS(n-l), and PRAS(n). Upon receiving the signal during the occurrence of the state Sl, S2, or S3 of the digital pulse signal 138, the corresponding parameter controller PRAS(n-N), PRAS(n-l), or PRAS(n) accesses a parameter level stored within the parameter controller and provides the parameter level to the driver system DRVRA. In some embodiments, when the digital pulse signal 138 has four states Sl through S4 without the state S5, in response to identifying the occurrence of the state of the digital pulse signal 138 to be Sl, S2, S3, or S4, the digital signal processor DSPA sends a signal to a corresponding one of the parameter controllers PRAS(n-N), PRAS(n-2), PRAS(n-l), and PRAS(n). Upon receiving the signal during the occurrence of the state Sl, S2, S3, or S4 of the digital pulse signal 138, the corresponding parameter controller PRAS(n-N), PRAS(n-2), PRAS(n-l), and PRAS(n) accesses a parameter level stored within the parameter controller and provides the parameter level to the driver system DRVRA.

[00137] In various embodiments, when the digital pulse signal 138 has three states Sl through S3 without the states S4 and S5, during the occurrence of one of the three states Sl through S3 of the digital pulse signal 138, the driver system DRVRA generates a current signal based on a corresponding one of the parameter levels PR1, PR2, and PR3, and provides the current signal to the RF power supply 102. Also, during the occurrence of the one of the three states Sl through S3 of the digital pulse signal 138, the RF power supply 102 generates the RF signal 122 upon receiving the current signal from the driver system DRVRA during the occurrence of the one of the three states Sl through S3 of the digital pulse signal 138. The RF signal 122 has the corresponding one of the parameter levels PR1, PR2, and PR3 during the occurrence of the one of the three states Sl through S3 of the digital pulse signal 138.

[00138] In some embodiments, when the digital pulse signal 138 has four states Sl through S4 without the state S5, during the occurrence of one of the four states Sl through S4 of the digital pulse signal 138, the driver system DRVRA generates a current signal based on a corresponding one of the parameter levels PR11, PR21, PR31, and PR41, and provides the current signal to the RF power supply 102. Also, during the occurrence of the one of the four states Sl through S4 of the digital pulse signal 138, the RF power supply 102 generates the RF signal 122 upon receiving the current signal from the driver system DRVRA during the occurrence of the one of the four states Sl through S4 of the digital pulse signal 138. The RF signal 122 has the corresponding one of the parameter levels PR11, PR21, PR31, and PR41 during the occurrence of the one of the four states Sl through S4 of the digital pulse signal 138.

[00139] In some embodiments, the RF generator RFGA is coupled via the RF cable 128, the impedance match 104, and the RF transmission line 126 to the TCP coil 116 instead of to the substrate support 114. Moreover, the RF generator RFGB is coupled via the RF cable 148, the impedance match 120, and the RF transmission line 132 to the substrate support 114 instead of to the TCP coil 116. For example, the modified RF signal 124 is supplied to the TCP coil 116 instead of the substrate support 114. Moreover, the modified RF signal 146 is supplied to the substrate support 114 instead of the TCP coil 116.

[00140] In various embodiments, the TCP coil is coupled to a ground potential instead of to the RF generator RFGB.

[00141] In some embodiments, the RF generator RFGA is coupled to the TCP coil 116 and the substrate support 114 is coupled to the ground potential.

[00142] In several embodiments, a combination of the digital signal processor DSPA, the parameter controllers PRAS(n-N) through PRAS(n), and the frequency controllers FCS(n-N) through FCS(n) are sometimes referred to herein as a controller. For example, each of the digital signal processor DSPA, the parameter controller PRAS(n-N), the parameter controller PRAS(n-l), the parameter controller PRAS(n), the frequency controller FCS(n-N), and the frequency controller FCS(n) is a portion, such as a hardware circuit or a software module, of the controller.

[00143] In various embodiments, any parameter levels, described herein, of the RF signal 122 are provided from the processor 108 via the connection medium 142 or another connection medium to the digital signal processor DSPA. In some embodiments, any frequency levels, described herein, of the RF signal 122 are provided from the processor 108 via the connection medium 140 or another connection medium to the digital signal processor DSPA. The parameter levels and the frequency levels, described herein, of the RF signal 122 are stored in the memory device 110.

[00144] Figure 2A shows embodiments of graphs 202, 206, 210, and 214 to illustrate three-level pulsing of the parameter of the RF signal 122 (figure 1) generated by the RF generator RFGA (figure 1) and two-level pulsing of the frequency of the RF signal 122. The graph 202 plots a logic level of a digital pulse signal 204 versus time t. The digital pulse signal 204 is an example of the digital pulse signal 138 of figure 1.

[00145] During the state Sl, the graph 202 has the logic level of one. Also, during the state S2, the graph 202 has the logic level of two. Moreover, during the state S3, the graph 202 has the logic level of three. For example, during a time period between 0 and tl2, the logic level of the digital pulse signal 204 is one, during a time period between tl2 and t22, the logic level of the digital pulse signal 204 is two, and during the time period between t22 and t32, the logic level of the digital pulse signal 204 is three.

[00146] The states S 1 through S3 of the digital pulse signal 204 repeat periodically after the time t32. For example, during a time period between the times t32 and t42, the logic level of the digital pulse signal 204 is one, during a time period between the times t42 and t52, the logic level of the digital pulse signal 204 is two, and during the time period between the times t52 and t62, the logic level of the digital pulse signal 204 is three. As another example, during a time period between the times t62 and t72, the logic level of the digital pulse signal 204 is one, during a time period between the times t72 and t82, the logic level of the digital pulse signal 204 is two, and during the time period between the times t82 and t92, the logic level of the digital pulse signal 204 is three.

[00147] It should be noted that a duty cycle of the digital pulse signal 204 during the state Sl is p%, where p is a positive real number less than 100. For example, p% ranges from and including 20% to 40%. Moreover, a duty cycle of the digital pulse signal 204 during the state S2 is q%, where q is a positive real number less than 100%. For example, q% ranges from and including 20% to 40%. Also, a duty cycle of the digital pulse signal 204 during the state S3 is (l00-p-q)%. For example, the duty cycle of the digital pulse signal 204 during the state S3 ranges from and including 20% to 40%. It should be noted that the duty cycles for the states Sl through S3 of the digital pulse signal 204 add to 100%, which is one occurrence of a cycle of the digital pulse signal 204.

[00148] The graph 206 plots a logic level of a digital pulse signal 208, which is an example of the digital pulse signal 136 of figure 1, versus the time t. The digital pulse signal 208 has the logic level of zero during the state SO and the logic level of one during the state Sl. For example, the digital pulse signal 208 has the logic level of zero during a time period between zero and the time tl2 and has the logic level of one during a time period between the time tl2 and the time t32.

[00149] The digital pulse signal 208 repeats the states SO and Sl after the time t32. For example, the digital pulse signal 208 has the logic level of zero during a time period between t32 and the time t42, has the logic level of one during a time period between the time t42 and the time t62, has the logic level of zero during a time period between t62 and the time t72, and has the logic level of one during a time period between the time t72 and the time t92. [00150] The graph 210 plots the parameter levels PR1, PR2, and PR3 of a parameter 212 of the RF signal 122 of figure 1 versus the time t. The parameter 212 is concurrent with, such as substantially synchronized with, the digital pulse signal 204. For example, the parameter 212 has the state Sl during the time period between the times 0 and tl2, the state S2 during the time period between the times tl2 and t22, and the state S3 during the time period between the times t22 and t32. To illustrate, the parameter 212 has the parameter level PR1 during the time period between the times 0 and tl2, the parameter level PR2 during the time period between the times tl2 and t22, and the parameter level PR3 during the time period between the times t22 and t32.

[00151] As another illustration, the parameter 212 transitions from the parameter level PR1 to the parameter level PR2 at approximately the same time, such as at the time tl2 or within a pre-defined time period from the time tl2, at which the digital pulse signal 204 transitions from the logic level 1 to the logic level 2. As yet another illustration, the parameter 212 transitions from the parameter level PR2 to the parameter level PR3 at approximately the same time, such as at the time t22 or within the pre-defined time period from the time t22, at which the digital pulse signal 204 transitions from the logic level 2 to the logic level 3. As another illustration, the parameter 212 transitions from the parameter level PR3 to the parameter level PR1 at approximately the same time, such as at the time t32 or within the pre defined time period from the time t32, at which the digital pulse signal 204 transitions from the logic level 3 to the logic level 1. An example of the pre-defined time period, as used herein, from a time is a time period that is within 0-10% from the time. For example, the pre defined time period from the time t32 is within 1-10% from the time t32. As another example, the pre-defined time period from the time tl2 is within 1-10% from the time tl2.

[00152] As another example, the parameter levels PR1 through PR3 repeat periodically after the time t32. To illustrate, the parameter 212 has the state Sl during the time period between the times t32 and t42, the state S2 during the time period between the times t42 and t52, and the state S3 during the time period between the times t52 and t62. As another illustration, the parameter 212 has the state Sl during the time period between the times t62 and t72, the state S2 during the time period between the times t72 and t82, and the state S3 during the time period between the times t82 and t92. As another illustration, the parameter 212 transitions from the parameter level PR1 to the parameter level PR2 at approximately the same time, such as at the time t42 or within the pre-defined time period from the time t42, at which the digital pulse signal 204 transitions from the logic level 1 to the logic level 2. As yet another illustration, the parameter 212 transitions from the parameter level PR2 to the parameter level PR3 at approximately the same time, such as at the time t52 or within the pre-defined time period from the time t52, at which the digital pulse signal 204 transitions from the logic level 2 to the logic level 3. As another illustration, the parameter 212 transitions from the parameter level PR3 to the parameter level PR1 at approximately the same time, such as at the time t62 or within the pre-defined time period from the time t62, at which the digital pulse signal 204 transitions from the logic level 3 to the logic level 1.

[00153] There is a stepwise increase from the parameter level PR1 to the parameter level PR3. For example, the parameter level PR2 is greater than the parameter level PR1 and the parameter level PR3 is greater than the parameter level PR2.

[00154] An example of the parameter level PR1 is al% of a maximum amount of bias voltage that is supplied to the substrate support 114 of figure 1. An example of al% ranges from and including 0% to 35%. Similarly, an example of the parameter level PR2 is bl% of the maximum amount of the bias voltage that is supplied to the substrate support 114. An example of bl% ranges from and including 35% to 70%. Also, an example of the parameter level PR3 is cl% of the maximum amount of the bias voltage that is supplied to the substrate support 114. An example of cl% ranges from and including 70% to 100% of the maximum amount of the bias voltage that is supplied to the substrate support 114. Another example of the parameter level PR3 ranges from and including 5 volts to 2 kilovolts (kV). As an example, the maximum amount of bias voltage is supplied to the substrate support 114 when the RF generator RFGA generates the RF signal 122 having a maximum magnitude of the parameter. In this example, the RF generator RFGA is not capable of generating a magnitude greater than the maximum magnitude of the parameter.

[00155] It should be noted that a difference between any two consecutive ones of the parameter levels PR1, PR2, and PR3 ranges from and including 15% to 35%. For example, the parameter level PR2 is at least 20% greater than the parameter level PR1 and the parameter level PR3 is at least 20% greater than the parameter level PR2. As another example, a parameter level increase from the parameter level PR1 to the parameter level PR2 or from the parameter level PR2 to the parameter level PR3 ranges from and including 30% to 35%. The parameter level PR2 is consecutive to the parameter level PR1. Similarly, the parameter level PR3 is consecutive to the parameter level PR2.

[00156] The graph 214 plots the frequency levels fl and f2 of a frequency 216 of the RF signal 122 versus the time t. The frequency level fl ranges between 0.8 megahertz and 2 megahertz. For example, the frequency level fl is 1 megahertz. The frequency level f2 ranges between 10 and 14 megahertz. For example, the frequency level f2 ranges from and including 10 megahertz to 13.5 megahertz.

[00157] The frequency 216 is concurrent with, such as is substantially synchronized with, the digital pulse signal 208. For example, the frequency 216 is at the frequency level fl during the state SO and at the frequency level f2 during the state Sl. To illustrate, the frequency 216 is at the frequency level fl during a time period between the time 0 and the time tl2 and is at the frequency level f2 for a time period between the time tl2 and the time t32. As another illustration, the frequency 216 transitions from the frequency level fl to the frequency level f2 at approximately the same time, such as at the time tl2 or within the pre-defined time period from the time tl2, at which the digital pulse signal 208 transitions from the logic level 0 to the logic level 1. As yet another illustration, the frequency 216 transitions from the frequency level f2 to the frequency level fl at approximately the same time, such as at the time t32 or within the pre-defined time period from the time t32, at which the digital pulse signal 208 transitions from the logic level 1 to the logic level 0.

[00158] As another example, the frequency levels fl and f2 repeat periodically after the time t32. To illustrate, the frequency 216 is at the frequency level fl during a time period between the time t32 and the time t42 and is at the frequency level f2 for a time period between the time t42 and the time t62. As another illustration, the frequency 216 is at the frequency level fl during a time period between the time t62 and the time t72 and is at the frequency level f2 for a time period between the time t72 and the time t92. As another illustration, the frequency 216 transitions from the frequency level fl to the frequency level f2 at approximately the same time, such as at the time t42 or within the pre-defined time period from the time t42, at which the digital pulse signal 208 transitions from the logic level 0 to the logic level 1. As yet another illustration, the frequency 216 transitions from the frequency level f2 to the frequency level fl at approximately the same time, such as at the time t62 or within the pre-defined time period from the time t62, at which the digital pulse signal 208 transitions from the logic level 1 to the logic level 0.

[00159] A difference between the frequency levels f 1 and f2 is greater than a preset range. As an example, the frequency level f2 is greater than the frequency level fl by at least 20%. To illustrate, an example of the frequency level fl ranges from including 400 kHz to 2 MHz and an example of the frequency level f2 ranges from and including 10 MHz to 13 MHz.

[00160] When the parameter 212 is pulsed to be at a low level simultaneous with pulsing the frequency 216 at a low level and the parameter 212 is pulsed to be at a high level simultaneous with pulsing the frequency 216 at a high level, there is a decrease in an angular spread of ions of plasma within the plasma chamber 112 of figure 1. The decrease in the angular spread increases rate of processing, such as etching, the substrate 118 of figure 1. An example of the low level of the frequency 216 is the frequency level fl and a high level of the frequency 216 is the frequency level fl. An example of the low level of the parameter 212 is the parameter level PR1 and of the high level of the parameter 212 is the parameter level PR3.

[00161] In some embodiments, instead of pulsing of the frequency 216 between the frequency levels fl and f2, the RF signal 122 has a constant frequency level. For example, a difference between any two values of the constant frequency level is less than the preset range. To illustrate, a highest of values of the constant frequency level is at most 20% from a lowest of the values of the constant frequency level.

[00162] In various embodiments, a duty cycle of the frequency 216 is different than that illustrated in Figure 2A. For example, instead of 66.66%, a duty cycle of the frequency 216 ranges from and including 20% to 80%.

[00163] Figure 2B shows embodiments of the graphs 202 and 210, a graph 218, and a graph 222 to illustrate reverse pulsing of a frequency 224 of the RF signal 122 of figure 1 compared to pulsing of the parameter 212 of the RF signal 122.

[00164] The graph 218 plots a logic level of a digital pulse signal 220, which is an example of the digital pulse signal 136 of figure 1, versus the time t. The digital pulse signal 220 has the logic level of one during the state S 1 and the logic level of zero during the state SO and is reverse pulsed with respect to the digital pulse signal 208 of figure 2A. For example, the digital pulse signal 220 has the logic level of one during the time period between zero and the time tl2 and has the logic level of zero during a time period between the time tl2 and the time t32.

[00165] The digital pulse signal 220 repeats the states SO and Sl after the time t32. For example, the digital pulse signal 220 has the logic level of one during the time period between t32 and the time t42, has the logic level of zero during the time period between the time t42 and the time t62, has the logic level of one during the time period between t62 and the time t72, and has the logic level of zero during the time period between the time t72 and the time t92.

[00166] The graph 222 plots the frequency 224 of the RF signal 122 versus the time t. The frequency 224 is concurrent with, such as substantially synchronized with, the digital pulse signal 220 and is reverse pulsed compared to the frequency 216 of figure 2 A. For example, the frequency 224 has the state S 1 during the time period between the times 0 and tl2 and has the state SO during the time period between the times tl2 and t32. To illustrate, the frequency 224 has the frequency level f2 during the time period between the times 0 and tl2 and has the frequency level fl during the time period between the times tl2 and t32. As another illustration, the frequency 224 transitions from the frequency level f2 to the frequency level fl at approximately the same time, such as at the time tl2 or within the pre-defined time period from the time tl2, at which the digital pulse signal 220 transitions from the logic level 1 to the logic level 0. As yet another illustration, the frequency 224 transitions from the frequency level fl to the frequency level f2 at approximately the same time, such as at the time t32 or within the pre-defined time period from the time t32, at which the digital pulse signal 220 transitions from the logic level 0 to the logic level 1.

[00167] The frequency 224 repeats the states SO and Sl after the time t32. For example, the frequency 224 has the frequency level f2 during the time period between t32 and the time t42, has the frequency level fl during the time period between the time t42 and the time t62, has the frequency level f2 during the time period between t62 and the time t72, and has the frequency level fl during the time period between the time t72 and the time t92.

[00168] When the parameter 212 is pulsed at the low level, the frequency 224 is pulsed at the high level, such as the frequency level f2. To illustrate, during the time period between the times zero and tl2, the parameter 212 is at the parameter level PR1 and the frequency 224 is at the frequency level f2. As another example, when the parameter 212 is pulsed at the high level, the frequency 224 is pulsed at the low level, such as the frequency level fl. To illustrate, during a time period between the times t22 and t32, the parameter 212 is at the parameter level PR3 and the frequency 224 is at the frequency level fl. It should be noted that pulsing of the parameter 212 to be at the high level simultaneous with pulsing of the frequency 224 to be at the low level and pulsing of the parameter 212 to be at the low level simultaneous with pulsing of the frequency 224 to be at the high level increases mask selectivity of the substrate 118. The mask selectivity, in some embodiments, is usually a ratio of an etch rate of etching a substrate layer of the substrate 118 below a mask layer of the substrate 118 and an etch rate of etching the mask layer. The mask layer is overlaid over the substrate layer of the substrate 118. The substrate layer 118 is overlaid on top of a silicon layer of the substrate 118. The mask layer allows patterns with very small features to be formed on the substrate layer. For example, the mask layer protects the substrate layer, such as a structured layer, that is located below the mask layer and above the silicon layer. [00169] It should be noted that a time difference between the times t22 and tl2 is the same as a time difference between tl2 and 0. Similarly, a time difference between the times t32 and t22 is the same as the time difference between t22 and tl2, and a time difference between the times t42 and t32 is the same as the time difference between the times t32 and t22. Also, a time difference between the times t52 and t42 is the same as the time difference between the times t42 and t32, and a time difference between the times t62 and t52 is the same as the time difference between the times t52 and t42. A time difference between the times t72 and t62 is the same as the time difference between t62 and t52, and a time difference between the times t82 and t72 is the same as the time difference between the times t72 and t62. A time difference between the times t92 and t82 is the same as the time difference between the times t82 and t72.

[00170] In various embodiments, a duty cycle of the frequency 224 is different than that illustrated in Figure 2B. For example, instead of 33.33%, a duty cycle of the frequency 224 ranges from and including 20% to 80%.

[00171] Figure 3 A shows embodiments of graphs 302, 306, 310, and 314 to illustrate four-level pulsing of the parameter of the RF signal 122 (figure 1) generated by the RF generator RFGA (figure 1) and two-level pulsing of the frequency of the RF signal 122. The graph 302 plots a logic level of a digital pulse signal 304 versus the time t. The digital pulse signal 304 is an example of the digital pulse signal 138 of figure 1.

[00172] During the state Sl, the graph 302 has the logic level of one. Also, during the state S2, the graph 302 has the logic level of two. Moreover, during the state S3, the graph 302 has the logic level of three. During the state S4, the graph 302 has a logic level of four. For example, during a time period between 0 and tl3, the logic level of the digital pulse signal 304 is one, during a time period between tl3 and t23, the logic level of the digital pulse signal 304 is two, during the time period between t23 and t33, the logic level of the digital pulse signal 304 is three, and during the time period between t33 and t43, the logic level of the digital pulse signal 304 is four.

[00173] The states S 1 through S4 of the digital pulse signal 304 repeat periodically after the time t43. For example, during a time period between t43 and t53, the logic level of the digital pulse signal 304 is one, during a time period between t53 and t63, the logic level of the digital pulse signal 304 is two, during the time period between t63 and t73, the logic level of the digital pulse signal 304 is three, and during the time period between t73 and t83, the logic level of the digital pulse signal 304 is four. As another example, during a time period between t83 and t93, the logic level of the digital pulse signal 304 is one, during a time period between t93 and tl03, the logic level of the digital pulse signal 304 is two, during the time period between tl03 and tll3, the logic level of the digital pulse signal 204 is three, and during the time period between tl 13 and tl23, the logic level of the digital pulse signal 204 is four.

[00174] It should be noted that a duty cycle of the digital pulse signal 304 during the state Sl is pl l%, where pll is a positive real number less than 100. For example, pll% ranges from and including 15% to 35%. Moreover, a duty cycle of the digital pulse signal 304 during the state S2 is ql 1%, where ql l is a positive real number less than 100%. For example, ql 1% ranges from and including 15% to 35%. Also, a duty cycle of the digital pulse signal 304 during the state S3 is rll%. For example, rl l% ranges from and including 15% to 35%. A duty cycle of the digital pulse signal 304 during the state S4 is (lOO-pl l-ql l- rl l)%. It should be noted that the duty cycles for the states Sl through S4 of the digital pulse signal 304 add to 100%, which is one occurrence of a cycle of the digital pulse signal 304.

[00175] The graph 306 plots a logic level of a digital pulse signal 308, which is an example of the digital pulse signal 136 of figure 1, versus the time t. The digital pulse signal 308 has the logic level of zero during the state SO and the logic level of one during the state Sl. For example, the digital pulse signal 308 has the logic level of zero during a time period between zero and the time tl3 and has the logic level of one during a time period between the time tl3 and the time t43.

[00176] The digital pulse signal 308 repeats the states SO and Sl after the time t43. For example, the digital pulse signal 308 has the logic level of zero during a time period between t43 and the time t53, has the logic level of one during a time period between the time t53 and the time t83, has the logic level of zero during a time period between t83 and the time t93, and has the logic level of one during a time period between the time t93 and the time tl23.

[00177] The graph 310 plots the parameter levels PR11, PR21, PR31, and PR41 of a parameter 312 of the RF signal 122 of figure 1 versus the time t. The parameter 312 is concurrent with, such as substantially synchronized with, the digital pulse signal 304. For example, the parameter 312 has the state Sl during the time period between the times 0 and tl3, the state S2 during the time period between the times tl3 and t23, the state S3 during the time period between the times t23 and t33, and the state S4 during the time period between the times t33 and t43. To illustrate, the parameter 312 has the parameter level PR11 during the time period between the times 0 and 113, the parameter level PR21 during the time period between the times tl3 and t23, the parameter level PR31 during the time period between the times t23 and t33, and the parameter level PR41 during the time period between the times t33 and t43.

[00178] As another illustration, the parameter 312 transitions from the parameter level PR11 to the parameter level PR21 at approximately the same time, such as at the time tl3 or within the pre-defined time period from the time tl3, at which the digital pulse signal 304 transitions from the logic level 1 to the logic level 2. As yet another illustration, the parameter 312 transitions from the parameter level PR21 to the parameter level PR31 at approximately the same time, such as at the time t23 or within the pre-defined time period from the time t23, at which the digital pulse signal 304 transitions from the logic level 2 to the logic level 3. As another illustration, the parameter 312 transitions from the parameter level PR31 to the parameter level PR41 at approximately the same time, such as at the time t33 or within the pre-defined time period from the time t33, at which the digital pulse signal 304 transitions from the logic level 3 to the logic level 4. As another illustration, the parameter 312 transitions from the parameter level PR41 to the parameter level PR11 at approximately the same time, such as at the time t43 or within the pre-defined time period from the time t43, at which the digital pulse signal 304 transitions from the logic level 4 to the logic level 1.

[00179] As another example, the parameter levels PR11 through PR41 repeat periodically after the time t43. To illustrate, the parameter 312 has the state Sl during the time period between the times t43 and t53, the state S2 during the time period between the times t53 and t63, the state S3 during the time period between the times t63 and t73, and the state S4 during the time period between the times t73 and t83. As another illustration, the parameter 312 has the state Sl during the time period between the times t83 and t93, the state S2 during the time period between the times t93 and tl03, the state S3 during the time period between the times tl03 and tl l3, and the state S4 during the time period between the times tl l3 and tl23.

[00180] There is a stepwise increase from the parameter level PR11 to the parameter level PR41. For example, the parameter level PR21 is greater than the parameter level PR11, the parameter level PR31 is greater than the parameter level PR21, and the parameter level PR41 is greater than the parameter level PR31.

[00181] An example of the parameter level PR 11 is all % of the maximum amount of bias voltage that is supplied to the substrate support 114 of figure 1. An example of al l% ranges from and including 0% to 25% of the maximum value. An example of the parameter level PR21 is bll% of the maximum amount of the bias voltage that is supplied to the substrate support 114. An example of bl l% ranges from and including 25% to 50% of the maximum value. Also, an example of the parameter level PR31 is cl l% of the maximum amount of the bias voltage that is supplied to the substrate support 114. An example of cl l% ranges from and including 50% to 75% of the maximum value. An example of the parameter level PR41 ranges from and including 5 volts to 2 kV. The parameter level PR41 ranges from and including 75% to 100% of the maximum value.

[00182] It should be noted that a difference between any two consecutive ones of the parameter levels PR11, PR21, PR31, and PR41 ranges from and including 15% to 30%. For example, the parameter level PR21 is at least 20% greater than the parameter level PR11, the parameter level PR31 is at least 20% greater than the parameter level PR21, and the parameter level PR41 is at least 20% greater than the parameter level PR31. As another example, a parameter level increase from the parameter level PR11 to the parameter level PR21 or from the parameter level PR21 to the parameter level PR31 or from the parameter level PR31 to the parameter level PR41 ranges from and including 20% to 30%. The parameter level PR21 is consecutive to the parameter level PR11. Similarly, the parameter level PR31 is consecutive to the parameter level PR21 and the parameter level PR41 is consecutive to the parameter level PR31.

[00183] The graph 314 plots the frequency levels fl and f2 of a frequency 316 of the RF signal 122 versus the time t. The frequency 316 is concurrent with, such as substantially synchronized with, the digital pulse signal 308. For example, the frequency 316 is at the frequency level fl during the state SO and at the frequency level f2 during the state Sl. To illustrate, the frequency 316 is at the frequency level fl during a time period between the time zero and the time tl3 and is at the frequency level f2 for a time period between the time tl3 and the time t43. As another illustration, the frequency 316 transitions from the frequency level fl to the frequency level f2 at approximately the same time, such as at the time tl3 or within the pre-defined time period from the time tl3, at which the digital pulse signal 308 transitions from the logic level 0 to the logic level 1. As yet another illustration, the frequency 316 transitions from the frequency level f2 to the frequency level fl at approximately the same time, such as at the time t43 or within the pre-defined time period from the time t43, at which the digital pulse signal 308 transitions from the logic level 1 to the logic level 0.

[00184] As another example, the frequency levels fl and f2 repeat periodically after the time t43. To illustrate, the frequency 316 is at the frequency level fl during a time period between the time t43 and the time t53 and is at the frequency level f2 for a time period between the time t53 and the time t83. As another illustration, the frequency 316 is at the frequency level fl during a time period between the time t83 and the time t93 and is at the frequency level f2 for a time period between the time t93 and the time tl23. As another illustration, the frequency 316 transitions from the frequency level fl to the frequency level f2 at the time t53 at which the digital pulse signal 308 transitions from the logic level 0 to the logic level 1. As yet another illustration, the frequency 316 transitions from the frequency level f2 to the frequency level fl at the time t83 at which the digital pulse signal 308 transitions from the logic level 1 to the logic level 0.

[00185] When the parameter 312 is pulsed to be at a low level simultaneous with pulsing the frequency 316 at a low level and the parameter 312 is pulsed to be at a high level simultaneous with pulsing the frequency 316 at a high level, there is a decrease in the angular spread of ions of plasma within the plasma chamber 112 of figure 1. The decrease in the angular spread increases the rate of processing the substrate 118 of figure 1. An example of the low level of the frequency 316 is the frequency level fl and a high level of the frequency 316 is the frequency level f2. An example of the low level of the parameter 312 is the parameter level PR 11 and of the high level of the parameter 312 is the parameter level PR41. Another example of the high level of the parameter 312 is the parameter level PR31.

[00186] It should further be noted that when the frequency 316 is at the low level, there is a decrease in temperature of ions of plasma within the plasma chamber 112. A relationship between the temperature of ions, voltage supplied to the ions, and of the angular spread is expressed as Q = tan ¹ ~ , where Q is the angular spread, Ti is the temperature of ions, and Vs is a sheath voltage of plasma sheath of plasma within the plasma chamber 112.

[00187] In some embodiments, instead of pulsing of the frequency 316 between the frequency levels fl and f2, the RF signal 122 has the constant frequency level.

[00188] In various embodiments, a duty cycle of the frequency 316 is different than that illustrated in Figure 3A. For example, instead of 75%, a duty cycle of the frequency 316 ranges from and including 20% to 80%.

[00189] Figure 3B shows embodiments of the graphs 302 and 310, a graph 318, and a graph 322 to illustrate reverse pulsing of a frequency 324 of the RF signal 122 of figure 1 compared to pulsing of the parameter 312 of the RF signal 122. The graph 318 plots a logic level of a digital pulse signal 320, which is an example of the digital pulse signal 136 of figure 1, versus the time t. The digital pulse signal 320 has the logic level of one during the state Sl and the logic level of zero during the state SO and is reverse pulsed with respect to the digital pulse signal 308 of figure 3A. For example, the digital pulse signal 320 has the logic level of one during the time period between zero and the time tl3 and has the logic level of zero during a time period between the time tl3 and the time t43.

[00190] The digital pulse signal 320 repeats the states SO and Sl after the time t43. For example, the digital pulse signal 320 has the logic level of one during the time period between t43 and the time t53, has the logic level of zero during the time period between the time t53 and the time t83, has the logic level of one during the time period between t83 and the time t93, and has the logic level of zero during the time period between the time t93 and the time tl23.

[00191] The graph 322 plots the frequency 324 of the RF signal 122 versus the time t. The frequency 324 is concurrent with, such as substantially synchronized with, the digital pulse signal 320 and is reverse pulsed compared to the frequency 316 of figure 2 A. For example, the frequency 324 has the state S 1 during the time period between the times 0 and tl3 and has the state SO during the time period between the times tl3 and t43. To illustrate, the frequency 324 has the frequency level f2 during the time period between the times 0 and tl3 and has the frequency level fl during the time period between the times tl3 and t43. As another illustration, the frequency 324 transitions from the frequency level f2 to the frequency level fl at approximately the same time, such as at the time tl3 or within the pre-defined time period from the time tl3, at which the digital pulse signal 320 transitions from the logic level 1 to the logic level 0. As yet another illustration, the frequency 324 transitions from the frequency level fl to the frequency level f2 at approximately the same time, such as at the time t43 or within the pre-defined time period from the time t43, at which the digital pulse signal 320 transitions from the logic level 0 to the logic level 1.

[00192] The frequency 324 repeats the states SO and Sl after the time t43. For example, the frequency 324 has the frequency level f2 during the time period between t43 and the time t53, has the frequency level fl during the time period between the time t53 and the time t83, has the frequency level f2 during the time period between t83 and the time t93, and has the frequency level fl during the time period between the time t93 and the time tl23.

[00193] When the parameter 312 is pulsed at the low level, the frequency 324 is pulsed at the high level, such as the frequency level f2. To illustrate, during the time period between the times zero and tl3, the parameter 312 is at the parameter level PR11 and the frequency 324 is at the frequency level f2. As another example, when the parameter 312 is pulsed at the high level, the frequency 324 is pulsed at the low level, such as the frequency level fl. To illustrate, during a time period between the times t33 and t43, the parameter 312 is at the parameter level PR41 and the frequency 324 is at the frequency level fl. As another illustration, during a time period between the times t23 and t33, the parameter 312 is at the parameter level PR31 and the frequency 324 is at the frequency level fl. It should be noted that pulsing of the parameter 312 to be at the high level simultaneous with pulsing of the frequency 324 to be at the low level and pulsing of the parameter 312 to be at the low level simultaneous with pulsing of the frequency 324 to be at the high level increases the mask selectivity.

[00194] It should be noted that a time difference between the times t23 and tl3 is the same as a time difference between tl3 and 0. Similarly, a time difference between the times t33 and t23 is the same as the time difference between t23 and tl3, and a time difference between the times t43 and t33 is the same as the time difference between the times t33 and t23. Similarly, a time difference between the times t53 and t43 is the same as the time difference between the times t43 and t33, and a time difference between the times t63 and t53 is the same as the time difference between the times t53 and t43. A time difference between the times t73 and t63 is the same as the time difference between t63 and t53, and a time difference between the times t83 and t73 is the same as the time difference between the times t73 and t63. A time difference between the times t93 and t83 is the same as the time difference between t83 and t73, and a time difference between the times tl03 and t93 is the same as the time difference between the times t93 and t83. Also, a time difference between the times tl l3 and tl03 is the same as the time difference between tl03 and t93, and a time difference between the times tl23 and tl l3 is the same as the time difference between the times tll3 and tl03.

[00195] In various embodiments, a duty cycle of the frequency 324 is different than that illustrated in Figure 3B. For example, instead of 25%, a duty cycle of the frequency 324 ranges from and including 20% to 80%.

[00196] Figure 3C shows embodiments of the graphs 302 and 310, a graph 326, and a graph 330 to illustrate pulsing of a frequency 332 of the RF signal 122 of figure 1 and pulsing of the parameter 312 of the RF signal 122. The graph 326 plots a logic level of a digital pulse signal 328, which is an example of the digital pulse signal 136 of figure 1, versus the time t. The digital pulse signal 328 has the logic level of zero during the state SO and the logic level of one during the state S 1 and has a different duty cycle compared to that of the digital pulse signal 308 of figure 3A. For example, the digital pulse signal 328 has the logic level of zero during the time period between zero and the time t23 and has the logic level of one during the time period between the time t23 and the time t43. As another example, the digital pulse signal 328 has the duty cycle of 50% and the digital pulse signal 308 has the duty cycle of 75%.

[00197] The digital pulse signal 328 repeats the states SO and Sl after the time t43. For example, the digital pulse signal 328 has the logic level of zero during the time period between t43 and the time t63, has the logic level of one during the time period between the time t63 and the time t83, has the logic level of zero during the time period between t83 and the time tl03, and has the logic level of one during the time period between the time tl03 and the time tl23.

[00198] The graph 330 plots the frequency 332 of the RF signal 122 versus the time t. The frequency 332 is concurrent with, such as substantially synchronized with, the digital pulse signal 328. For example, the frequency 332 has the state SO during the time period between the times 0 and t23 and has the state S 1 during the time period between the times t23 and t43. To illustrate, the frequency 332 has the frequency level fl during the time period between the times 0 and t23 and has the frequency level f2 during the time period between the times t23 and t43. As another illustration, the frequency 332 transitions from the frequency level fl to the frequency level f2 at approximately the same time, such as at the time t23 or within the pre-defined time period from the time t23, at which the digital pulse signal 328 transitions from the logic level 0 to the logic level 1. As yet another illustration, the frequency 332 transitions from the frequency level f2 to the frequency level fl at approximately the same time, such as at the time t43 or within the pre-defined time period from the time t43, at which the digital pulse signal 308 transitions from the logic level 1 to the logic level 0.

[00199] The frequency 332 repeats the states SO and Sl after the time t43. For example, the frequency 332 has the frequency level fl during the time period between t43 and the time t63, has the frequency level f2 during the time period between the time t63 and the time t83, has the frequency level fl during the time period between t83 and the time tl03, and has the frequency level f2 during the time period between the time tl03 and the time tl23.

[00200] When the parameter 328 is pulsed to be at a low level simultaneous with pulsing the frequency 332 at a low level and the parameter 328 is pulsed to be at a high level simultaneous with pulsing the frequency 332 at a high level, there is a decrease in the angular spread of ions of plasma within the plasma chamber 112 of figure 1. An example of the low level of the frequency 332 is the frequency level fl and a high level of the frequency 332 is the frequency level f2. An example of the low level of the parameter 328 is the parameter level PR11 and of the high level of the parameter 328 is the parameter level PR41. Another example of the low level of the parameter 328 is the parameter level PR21 and of the high level of the parameter 328 is the parameter level PR31.

[00201] In various embodiments, a duty cycle of the frequency 332 is different than that illustrated in Figure 3C. For example, instead of 50%, a duty cycle of the frequency 332 ranges from and including 20% to 80%.

[00202] Figure 3D shows embodiments of the graphs 302 and 310, a graph 334, and a graph 338 to illustrate reverse pulsing of a frequency 340 of the RF signal 122 of figure 1 compared to pulsing of the parameter 312 of the RF signal 122. The graph 334 plots a logic level of a digital pulse signal 336, which is an example of the digital pulse signal 136 of figure 1, versus the time t. The digital pulse signal 336 has the logic level of one during the state Sl and the logic level of zero during the state SO and is reverse pulsed with respect to the digital pulse signal 328 of figure 3C. For example, the digital pulse signal 336 has the logic level of one during the time period between zero and the time t23 and has the logic level of zero during a time period between the time t23 and the time t43.

[00203] The digital pulse signal 336 repeats the states SO and Sl after the time t43. For example, the digital pulse signal 336 has the logic level of one during the time period between t43 and the time t63, has the logic level of zero during the time period between the time t63 and the time t83, has the logic level of one during the time period between t83 and the time tl03, and has the logic level of zero during the time period between the time tl03 and the time tl23.

[00204] The graph 338 plots the frequency 340 of the RF signal 122 versus the time t. The frequency 340 is concurrent with, such as is substantially synchronized with, the digital pulse signal 336 and is reverse pulsed compared to the frequency 332 of figure 3C. For example, the frequency 340 has the state S 1 during the time period between the times 0 and t23 and has the state SO during the time period between the times t23 and t43. To illustrate, the frequency 340 has the frequency level f2 during the time period between the times 0 and t23 and has the frequency level fl during the time period between the times t23 and t43. As another illustration, the frequency 340 transitions from the frequency level f2 to the frequency level f 1 at approximately the same time, such as at the time t23 or within the pre-defined time period from the time t23, at which the digital pulse signal 336 transitions from the logic level 1 to the logic level 0. As yet another illustration, the frequency 340 transitions from the frequency level fl to the frequency level f2 at approximately the same time, such as at the time t43 or within the pre-defined time period from the time t43, at which the digital pulse signal 336 transitions from the logic level 0 to the logic level 1.

[00205] The frequency 340 repeats the states SO and Sl after the time t43. For example, the frequency 340 has the frequency level f2 during the time period between t43 and the time t63, has the frequency level fl during the time period between the time t63 and the time t83, has the frequency level f2 during the time period between t83 and the time tl03, and has the frequency level fl during the time period between the time tl03 and the time tl23.

[00206] When the parameter 312 is pulsed at the low level, the frequency 340 is pulsed at the high level. To illustrate, during the time period between the times zero and tl3, the parameter 312 is at the parameter level PR11 and the frequency 340 is at the frequency level f2. As another illustration, during the time period between the times tl3 and t23, the parameter 312 is at the parameter level PR21 and the frequency 340 is at the frequency level f2. As another example, when the parameter 312 is pulsed at the high level, the frequency 340 is pulsed at the low level. To illustrate, during a time period between the times t33 and t43, the parameter 312 is at the parameter level PR41 and the frequency 340 is at the frequency level fl. As another illustration, during a time period between the times t23 and t33, the parameter 312 is at the parameter level PR31 and the frequency 340 is at the frequency level fl. It should be noted that pulsing of the parameter 312 to be at the high level simultaneous with pulsing of the frequency 340 to be at the low level and pulsing of the parameter 312 to be at the low level simultaneous with pulsing of the frequency 340 to be at the high level increases the mask selectivity.

[00207] In various embodiments, a duty cycle of the frequency 340 is different than that illustrated in Figure 3D. For example, instead of 50%, a duty cycle of the frequency 340 ranges from and including 20% to 80%.

[00208] Figure 4 A shows embodiments of graphs 402, 406, 410, and 414 to illustrate five-level pulsing of the parameter of the RF signal 122 (figure 1) generated by the RF generator RFGA (figure 1) and two-level pulsing of the frequency of the RF signal 122. The graph 402 plots a logic level of a digital pulse signal 404 versus time t. The digital pulse signal 404 is an example of the digital pulse signal 138 of figure 1.

[00209] During the state Sl, the graph 402 has the logic level of one. Also, during the state S2, the graph 402 has the logic level of two. Moreover, during the state S3, the graph 402 has the logic level of three. During the state S4, the graph 402 has a logic level of four. During the state S5, the graph 402 has a logic level of five. For example, during a time period between 0 and tl4, the logic level of the digital pulse signal 404 is one, during a time period between tl4 and t24, the logic level of the digital pulse signal 404 is two, during the time period between t24 and t34, the logic level of the digital pulse signal 404 is three, during the time period between t34 and t44, the logic level of the digital pulse signal 404 is four, and during the time period between t44 and t54, the logic level of the digital pulse signal 404 is five.

[00210] The states S 1 through S5 of the digital pulse signal 404 repeat periodically after the time t54. For example, during a time period between t54 and t64, the logic level of the digital pulse signal 404 is one, during a time period between t64 and t74, the logic level of the digital pulse signal 404 is two, during the time period between t74 and t84, the logic level of the digital pulse signal 404 is three, during the time period between t84 and t94, the logic level of the digital pulse signal 404 is four, and during the time period between t94 and tl04, the logic level of the digital pulse signal 404 is five.

[00211] It should be noted that a duty cycle of the digital pulse signal 404 during the state Sl is pl ll%, where pll l is a positive real number less than 100. For example, pll l% ranges from and including 10% to 24%. Moreover, a duty cycle of the digital pulse signal 404 during the state S2 is ql 11%, where qll l is a positive real number less than 100%. For example, ql 11 % ranges from and including 10% to 24%. Also, a duty cycle of the digital pulse signal 404 during the state S3 is rl l l%. For example, rl 11% ranges from and including 10% to 24%. A duty cycle of the digital pulse signal 404 during the state S4 is slll%. For example, sl 11% ranges from and including 10% to 24%. A duty cycle of the digital pulse signal 304 during the state S5 is (100-pl ll-ql ll-rl ll-sl ll)%. It should be noted that the duty cycles for the states S 1 through S5 of the digital pulse signal 404 add to 100%, which is one occurrence of a cycle of the digital pulse signal 404.

[00212] The graph 406 plots a logic level of a digital pulse signal 408, which is an example of the digital pulse signal 136 of figure 1, versus the time t. The digital pulse signal 408 has the logic level of zero during the state SO and the logic level of one during the state Sl. For example, the digital pulse signal 408 has the logic level of zero during a time period between zero and the time t34 and has the logic level of one during a time period between the time t34 and the time t54.

[00213] The digital pulse signal 408 repeats the states SO and Sl after the time t54. For example, the digital pulse signal 408 has the logic level of zero during a time period between t54 and the time t84 and has the logic level of one during a time period between the time t84 and the time tl04. [00214] The graph 410 plots the parameter levels PR111, PR211, PR311, PR411, and PR511 of a parameter 412 of the RF signal 122 of figure 1 versus the time t. The parameter 412 is concurrent with, such as substantially synchronized with, the digital pulse signal 404. For example, the parameter 412 has the state Sl during the time period between the times 0 and tl4, the state S2 during the time period between the times tl4 and t24, the state S3 during the time period between the times t24 and t34, the state S4 during the time period between the times t34 and t44, the state S5 during the time period between the times t44 and t54. To illustrate, the parameter 412 has the parameter level PR111 during the time period between the times 0 and tl4, the parameter level PR211 during the time period between the times tl4 and t24, the parameter level PR311 during the time period between the times t24 and t34, the parameter level PR411 during the time period between the times t34 and t44, and the parameter level PR511 during the time period between the times t44 and t54.

[00215] As another illustration, the parameter 412 transitions from the parameter level PR111 to the parameter level PR211 at approximately the same time, such as at the time tl4 or within the pre-defined time period from the time tl4, at which the digital pulse signal 404 transitions from the logic level 1 to the logic level 2. As yet another illustration, the parameter 412 transitions from the parameter level PR211 to the parameter level PR311 at approximately the same time, such as at the time t24 or within the pre-defined time period from the time t24, at which the digital pulse signal 404 transitions from the logic level 2 to the logic level 3. As another illustration, the parameter 412 transitions from the parameter level PR311 to the parameter level PR411 at approximately the same time, such as at the time t34 or within the pre-defined time period from the time t34, at which the digital pulse signal 404 transitions from the logic level 3 to the logic level 4. As yet another illustration, the parameter 412 transitions from the parameter level PR411 to the parameter level PR511 at approximately the same time, such as at the time t44 or within the pre-defined time period from the time t44, at which the digital pulse signal 404 transitions from the logic level 4 to the logic level 5. As another illustration, the parameter 412 transitions from the parameter level PR511 to the parameter level PR111 at approximately the same time, such as at the time t54 or within the pre-defined time period from the time t54, at which the digital pulse signal 404 transitions from the logic level 5 to the logic level 1.

[00216] As another example, the parameter levels PR111 through PR511 repeat periodically after the time t54. To illustrate, the parameter 412 has the state Sl during the time period between the times t54 and t64, the state S2 during the time period between the times t64 and t74, the state S3 during the time period between the times t74 and t84, the state S4 during the time period between the times t84 and t94, and the state S5 during the time period between the times t94 and tl04. As another illustration, the parameter 412 transitions from the parameter level PR111 to the parameter level PR211 at approximately the same time, such as at the time t64 or within the pre-defined time period from the time t64, at which the digital pulse signal 404 transitions from the logic level 1 to the logic level 2. As yet another illustration, the parameter 412 transitions from the parameter level PR211 to the parameter level PR311 at approximately the same time, such as at the time t74 or within the pre-defined time period from the time t74, at which the digital pulse signal 404 transitions from the logic level 2 to the logic level 3. As another illustration, the parameter 412 transitions from the parameter level PR311 to the parameter level PR411 at approximately the same time, such as at the time t84 or within the pre-defined time period from the time t84, at which the digital pulse signal 404 transitions from the logic level 3 to the logic level 4. As yet another illustration, the parameter 412 transitions from the parameter level PR411 to the parameter level PR511 at approximately the same time, such as at the time t94 or within the pre-defined time period from the time t94, at which the digital pulse signal 404 transitions from the logic level 4 to the logic level 5. As another illustration, the parameter 412 transitions from the parameter level PR511 to the parameter level PR111 at approximately the same time, such as at the time tl04 or within the pre-defined time period from the time tl04, at which the digital pulse signal 404 transitions from the logic level 5 to the logic level 1.

[00217] There is a stepwise increase from the parameter level PR111 to the parameter level PR511. For example, the parameter level PR211 is greater than the parameter level PR111, the parameter level PR311 is greater than the parameter level PR211, the parameter level PR411 is greater than the parameter level PR311, and the parameter level PR511 is greater than the parameter level PR411.

[00218] An example of the parameter level PR111 is all l% of the maximum amount of bias voltage that is supplied to the substrate support 114 of figure 1. An example of al ll% ranges from and including 0% to 20% of the maximum value. An example of the parameter level PR211 is bl 11% of the maximum amount of the bias voltage that is supplied to the substrate support 114. An example of bl 11% ranges from and including 20% to 40% of the maximum value. Also, an example of the parameter level PR311 is cl 11% of the maximum amount of the bias voltage that is supplied to the substrate support 114. An example of cl 11% ranges from and including 40% to 60% of the maximum value. An example of the parameter level PR411 is dll 1% of the maximum amount of the bias voltage that is supplied to the substrate support 114. An example of dll l% ranges from and including 60% to 80% of the maximum value. An example of the parameter level PR511 ranges from and including 5 volts to 2 kV. The parameter level PR511 ranges from and including 80% to 100% of the maximum value of bias voltage that is supplied to the substrate support 114.

[00219] It should be noted that a difference between any two consecutive ones of the parameter levels PR111, PR211, PR311, PR411, and PR511 ranges from and including 15% to 25%. For example, the parameter level PR211 is at least 20% greater than the parameter level PR111, the parameter level PR311 is at least 20% greater than the parameter level PR211, the parameter level PR411 is at least 20% greater than the parameter level PR311, and the parameter level PR511 is at least 20% greater than the parameter level PR411. As another example, a parameter level increase from the parameter level PR111 to the parameter level PR211 or from the parameter level PR211 to the parameter level PR311 or from the parameter level PR311 to the parameter level PR411 or from the parameter level PR411 to the parameter level PR511 ranges from and including 15% to 25%. The increase in the parameter level facilitates a higher amount of peak energy of ions of plasma within the plasma chamber 112 and a narrow angular spread of the ions. The parameter level PR211 is consecutive to the parameter level PR111. Similarly, the parameter level PR311 is consecutive to the parameter level PR211, the parameter level PR411 is consecutive to the parameter level PR311, and the parameter level PR511 is consecutive to the parameter level PR411.

[00220] The graph 414 plots the frequency levels fl and f2 of a frequency 416 of the RF signal 122 versus the time t. The frequency 416 is concurrent with, such as substantially synchronized with, the digital pulse signal 408. For example, the frequency 416 is at the frequency level fl during the state SO and at the frequency level f2 during the state Sl. To illustrate, the frequency 416 is at the frequency level fl during a time period between the time zero and the time t34 and is at the frequency level f2 for a time period between the time t34 and the time t54. As another illustration, the frequency 416 transitions from the frequency level fl to the frequency level f2 at approximately the same time, such as at the time t34 or within the pre-defined time period from the time t34, at which the digital pulse signal 408 transitions from the logic level 0 to the logic level 1. As yet another illustration, the frequency 416 transitions from the frequency level f2 to the frequency level fl at approximately the same time, such as at the time t54 or within the pre-defined time period from the time t54, at which the digital pulse signal 408 transitions from the logic level 1 to the logic level 0. As another example, the frequency levels fl and f2 repeat periodically after the time t54. To illustrate, the frequency 416 is at the frequency level fl during a time period between the time t54 and the time t84 and is at the frequency level f2 for a time period between the time t84 and the time tl04.

[00221] When the parameter 412 is pulsed to be at a low level simultaneous with pulsing the frequency 416 at a low level and the parameter 412 is pulsed to be at a high level simultaneous with pulsing the frequency 416 at a high level, there is a decrease in the angular spread of ions of plasma within the plasma chamber 112 of figure 1. An example of the low level of the frequency 416 is the frequency level fl and a high level of the frequency 416 is the frequency level f2. An example of the low level of the parameter 412 is the parameter level PR111 and of the high level of the parameter 412 is the parameter level PR511. Another example of the low level of the parameter 412 is the parameter level PR211 and of the high level of the parameter 412 is the parameter level PR411. It should be noted that when the frequency 416 is at the low level, there is a decrease in temperature of ions of plasma within the plasma chamber 112.

[00222] In some embodiments, instead of pulsing of the frequency 416 between the frequency levels fl and f2, the RF signal 122 has the constant frequency level.

[00223] In various embodiments, a duty cycle of the frequency 416 is different than that illustrated in Figure 4 A. For example, instead of 40%, a duty cycle of the frequency 416 ranges from and including 20% to 80%.

[00224] Figure 4B shows embodiments of the graphs 402 and 410, a graph 418, and a graph 422 to illustrate reverse pulsing of a frequency 424 of the RF signal 122 of figure 1 compared to pulsing of the parameter 412 of the RF signal 122.

[00225] The graph 418 plots a logic level of a digital pulse signal 420, which is an example of the digital pulse signal 136 of figure 1, versus the time t. The digital pulse signal 420 has the logic level of one during the state S 1 and the logic level of zero during the state SO and is reverse pulsed with respect to the digital pulse signal 408 of figure 4A. For example, the digital pulse signal 420 has the logic level of one during the time period between zero and the time t34 and has the logic level of zero during a time period between the time t34 and the time t54.

[00226] The digital pulse signal 420 repeats the states SO and Sl after the time t54. For example, the digital pulse signal 420 has the logic level of one during the time period between t54 and the time t84 and has the logic level of zero during the time period between the time t84 and the time tl04. [00227] The graph 422 plots the frequency 424 of the RF signal 122 versus the time t. The frequency 424 is concurrent with, such as substantially synchronized with, the digital pulse signal 420 and is reverse pulsed compared to the frequency 416 of figure 4 A. For example, the frequency 424 has the state S 1 during the time period between the times 0 and t34 and has the state SO during the time period between the times t34 and t54. To illustrate, the frequency 424 has the frequency level f2 during the time period between the times 0 and t34 and has the frequency level fl during the time period between the times t34 and t54. As another illustration, the frequency 424 transitions from the frequency level f2 to the frequency level fl at approximately the same time, such as at the time t34 or within the pre-defined time period from the time t34, at which the digital pulse signal 420 transitions from the logic level 1 to the logic level 0. As yet another illustration, the frequency 424 transitions from the frequency level fl to the frequency level f2 at approximately the same time, such as at the time t54 or within the pre-defined time period from the time t54, at which the digital pulse signal 420 transitions from the logic level 0 to the logic level 1.

[00228] The frequency 424 repeats the states SO and Sl after the time t54. For example, the frequency 424 has the frequency level f2 during the time period between t54 and the time t84 and has the frequency level fl during the time period between the time t84 and the time tl04.

[00229] When the parameter 412 is pulsed at the low level, the frequency 424 is pulsed at the high level, such as the frequency level f2. To illustrate, during the time period between the times zero and tl4, the parameter 412 is at the parameter level PR11 and the frequency 424 is at the frequency level f2. As another illustration, during the time period between the times tl4 and t24, the parameter 412 is at the parameter level PR21 and the frequency 424 is at the frequency level f2. As another example, when the parameter 412 is pulsed at the high level, the frequency 424 is pulsed at the low level, such as the frequency level fl. To illustrate, during a time period between the times t44 and t54, the parameter 412 is at the parameter level PR511 and the frequency 424 is at the frequency level f 1. As another illustration, during a time period between the times t34 and t44, the parameter 412 is at the parameter level PR411 and the frequency 424 is at the frequency level fl. It should be noted that pulsing of the parameter 412 to be at the high level simultaneous with pulsing of the frequency 424 to be at the low level and pulsing of the parameter 412 to be at the low level simultaneous with pulsing of the frequency 424 to be at the high level increases the mask selectivity. [00230] It should be noted that a time difference between the times t24 and tl4 is the same as a time difference between tl4 and 0. Similarly, a time difference between the times t34 and t24 is the same as the time difference between t24 and tl4, and a time difference between the times t44 and t34 is the same as the time difference between the times t34 and t24. Similarly, a time difference between the times t54 and t44 is the same as the time difference between the times t44 and t34, and a time difference between the times t64 and t54 is the same as the time difference between the times t54 and t44. A time difference between the times t74 and t64 is the same as the time difference between t64 and t54, and a time difference between the times t84 and t74 is the same as the time difference between the times t74 and t64. A time difference between the times t94 and t84 is the same as the time difference between t84 and t74, and a time difference between the times tl04 and t94 is the same as the time difference between the times t94 and t84.

[00231] It should be noted that the time t is measured in terms of nanoseconds or microseconds. For example, each pulse of a digital pulse signal, described herein, ranges from a few nanoseconds to a few microseconds. As another example, the time t22 (figures 2A and 2B) or t43 (figures 3A-3D) or t54 is a few nanoseconds or a few microseconds.

[00232] It should further be noted that the RF generator RFGA is controlled by the processor 108 of figure 1 to generate the RF signal 122 that concurrently pulses between multiple parameter levels and between multiple frequency levels during a time period. For example, the RF generator RFGA is controlled by the processor 108 of figure 1 to generate the RF signal 122 that pulses between the multiple parameter levels while the RF generator RFGA is controlled by the processor 108 to generate the RF signal 122 that pulses between the multiple frequency levels. To illustrate, the RF generator RFGA generates the RF signal 122 that pulses between the parameter levels PR1, PR2, and PR3 of Figures 2A and 2B in response to receiving the digital pulse signal 138 of figure 1. The RF signal 122 pulses between the parameter levels PR1 through PR3 during a time period between the times t92 and 0 of figures 2A and 2B. Moreover, the RF generator RFGA generates the RF signal 122 that pulses between the frequency levels fl and f2 of Figures 2A and 2B in response to receiving the digital pulse signal 136 of figure 1. The RF signal 122 pulses between the frequency levels fl and f2 during the time period between the times t92 and 0.

[00233] As another illustration, the RF generator RFGA generates the RF signal 122 that pulses between the parameter levels PR11, PR21, PR31, and PR41 of Figures 3A-3D in response to receiving the digital pulse signal 138 of figure 1. The RF signal 122 pulses between the parameter levels PR11 through PR41 during a time period between the times tl23 and 0 of figures 3A-3D. Moreover, the RF generator RFGA generates the RF signal 122 that pulses between the frequency levels fl and f2 of Figures 3 A- 3D in response to receiving the digital pulse signal 136 of figure 1. The RF signal 122 pulses between the frequency levels fl and f2 during the time period between the times tl23 and 0.

[00234] As yet another illustration, the RF generator RFGA generates the RF signal 122 that pulses between the parameter levels PR111, PR211, PR311, PR411, and PR511 of Figures 4A and 4B in response to receiving the digital pulse signal 138 of figure 1. The RF signal 122 pulses between the parameter levels PR111 through PR511 during a time period between the times tl04 and 0 of figures 4 A and 4B. Moreover, the RF generator RFGA generates the RF signal 122 that pulses between the frequency levels fl and f2 of Figures 4 A and 4B in response to receiving the digital pulse signal 136 of figure 1. The RF signal 122 pulses between the frequency levels fl and f2 during the time period between the times tl04 and 0.

[00235] As still another illustration, with reference to Figure 2A, the frequency level fl is pulsed to the frequency level f2 at approximately the same time, such as the time tl2 or t42 or t72 or within the pre-defined time period from the time tl2 or t42 or t72, at which the parameter level PR1 is pulsed to the parameter level PR2. Moreover, the frequency level f2 is pulsed to the frequency level fl at approximately the same time, such as the time 0 or t32 or t62 or t92 or t42 or t72 or within the pre-defined time period from the time 0 or t32 or t62 or t92 or t42 or t72, at which the parameter level PR3 is pulsed to the parameter level PR1.

[00236] As another illustration, with reference to Figure 2B, the frequency level f2 is pulsed to the frequency level fl at approximately the same time, such as the time tl2 or t42 or t72 or within the pre-defined time period from the time tl2 or t42 or t72, at which the parameter level PR1 is pulsed to the parameter level PR2. Moreover, the frequency level fl is pulsed to the frequency level f2 at approximately the same time, such as the time 0 or t32 or t62 or t92 or within the pre-defined time period from the time 0 or t32 or t62 or t92, at which the parameter level PR3 is pulsed to the parameter level PR1.

[00237] As yet another illustration, with reference to Figure 3A, the frequency level fl is pulsed to the frequency level f2 at approximately the same time, such as the time tl3 or t53 or t93 or within the pre-defined time period from the time tl3 or t53 or t93, at which the parameter level PR11 is pulsed to the parameter level PR21. Moreover, the frequency level f2 is pulsed to the frequency level fl at approximately the same time, such as the time 0 or t43 or t83 or tl23 or within the pre-defined time period from the time 0 or t43 or t83 or tl23, at which the parameter level PR41 is pulsed to the parameter level PR11.

[00238] As still another illustration, with reference to Figure 3B, the frequency level f2 is pulsed to the frequency level fl at approximately the same time, such as the time tl3 or t53 or t93 or within the pre-defined time period from the time tl3 or t53 or t93, at which the parameter level PR11 is pulsed to the parameter level PR21. Moreover, the frequency level fl is pulsed to the frequency level f2 at approximately the same time, such as the time 0 or t43 or t83 or tl23 or within the pre-defined time period from the time 0 or t43 or t83 or tl23, at which the parameter level PR41 is pulsed to the parameter level PR11.

[00239] As yet another illustration, with reference to Figure 3C, the frequency level fl is pulsed to the frequency level f2 at approximately the same time, such as the time t23 or t63 or tl03 or within the pre-defined time period from the time t23 or t63 or tl03, at which the parameter level PR21 is pulsed to the parameter level PR31. Moreover, the frequency level f2 is pulsed to the frequency level fl at approximately the same time, such as the time 0 or t43 or t83 or tl23 or within the pre-defined time period from the time 0 or t43 or t83 or tl23, at which the parameter level PR41 is pulsed to the parameter level PR11.

[00240] As still another illustration, with reference to Figure 3D, the frequency level f2 is pulsed to the frequency level fl at approximately the same time, such as the time t23 or t63 or tl03 or within the pre-defined time period from the time t23 or t63 or tl03, at which the parameter level PR21 is pulsed to the parameter level PR31. Moreover, the frequency level fl is pulsed to the frequency level f2 at approximately the same time, such as the time 0 or t43 or t83 or tl23 or within the pre-defined time period from the time 0 or t43 or t83 or tl23, at which the parameter level PR41 is pulsed to the parameter level PR11.

[00241] As yet another illustration, with reference to Figure 4A, the frequency level fl is pulsed to the frequency level f2 at approximately the same time, such as the time t34 or t84 or within the pre-defined time period from the time t34 or t84, at which the parameter level PR311 is pulsed to the parameter level PR411. Moreover, the frequency level f2 is pulsed to the frequency level fl at approximately the same time, such as the time 0 or t54 or tl04 or within the pre-defined time period from the time 0 or t54 or tl04, at which the parameter level PR511 is pulsed to the parameter level PR111.

[00242] As another illustration, with reference to Figure 4B, the frequency level f2 is pulsed to the frequency level fl at approximately the same time, such as the time t34 or t84 or tl04 or within the pre-defined time period from the time t34 or t84, at which the parameter level PR311 is pulsed to the parameter level PR411. Moreover, the frequency level fl is pulsed to the frequency level f2 at approximately the same time, such as the time 0 or t54 or tl04 or tl04 or within the pre-defined time period from the time 0 or t54 or tl04 or tl04, at which the parameter level PR511 is pulsed to the parameter level PR111.

[00243] It should be noted that the terms "at approximately the same time" is sometimes referred to herein as "in substantial synchronization with", and these terms are used interchangeably herein. Moreover, it should further be noted that the frequency of the RF signal 122 pulses concurrently with, such as in substantial synchronization with, the parameter of the RF signal 122. For example, the frequency level f2 is pulsed to the frequency level fl in substantial synchronization with, such as the time t34 or t84 or tl04 or within the pre-defined time period from the time t34 or t84, pulsing from the parameter level PR311 to the parameter level PR411. Moreover, the frequency level fl is pulsed to the frequency level f2 in substantial synchronization with, such as the time 0 or t54 or tl04 or tl04 or within the pre-defined time period from the time 0 or t54 or tl04 or tl04, pulsing from the parameter level PR511 to the parameter level PR111.

[00244] It should further be noted that an occurrence of a state of a signal, such as a digital pulse signal or the parameter or the frequency, is a pulse of the signal during a periodic cycle of the signal. For example, with reference to Figure 2A, an occurrence of the state Sl of the digital pulse signal 204 is a pulse of the digital pulse signal 204 that occurs during the time period between the times tl2 and 0. Another occurrence of the state Sl of the digital pulse signal 204 is a pulse of the digital pulse signal 204 that occurs during the time period between the times t42 and t32. Similarly, an occurrence of the state S2 of the digital pulse signal 204 is a pulse of the digital pulse signal 204 that occurs during the time period between the times t22 and tl2. An occurrence of the state S3 of the digital pulse signal 204 is a pulse of the digital pulse signal 204 that occurs during the time period between the times t32 and t22. In this manner, there are three occurrences of each of the states Sl, S2, and S3 of the digital pulse signal 204 during the time period between the times t92 and 0. Also, there are three occurrences of each of the states SO and Sl of the digital pulse signal 208 during the time period between the times t92 and 0. Similarly, there are three occurrences of each of the states Sl, S2, and S3 of the parameter 212 during the time period between the times t92 and 0 and there are three occurrences of each of the states SO and Sl of the frequency 216 during the time period between the times t92 and 0.

[00245] With reference to Figure 3A, there are three occurrences of each of the states Sl, S2, S3, and S4 of the digital pulse signal 304 during the time period between the times tl23 and 0. Similarly, there are three occurrences of each of the states SO and Sl of the digital pulse signal 308 during the time period between the times tl23 and 0. There are three occurrences of each of the states Sl, S2, S3, and S4 of the parameter 312 during the time period between the times tl23 and 0 and there are three occurrences of each of the states SO and Sl of the frequency 316 during the time period between the times tl23 and 0.

[00246] With reference to Figure 3C, there are three occurrences of each of the states SO and Sl of the digital pulse signal 328 during the time period between the times tl23 and 0. There are three occurrences of each of the states SO and Sl of the frequency 332 during the time period between the times tl23 and 0.

[00247] With reference to Figure 4A, there are two occurrences of each of the states Sl, S2, S3, S4, and S5 of the digital pulse signal 404 during the time period between the times tl04 and 0. Similarly, there are two occurrences of each of the states SO and Sl of the digital pulse signal 408 during the time period between the times tl04 and 0. There are two occurrences of each of the states Sl, S2, S3, S4, and S5 of the parameter 412 during the time period between the times tl04 and 0 and there are two occurrences of each of the states SO and Sl of the frequency 416 during the time period between the times tl04 and 0.

[00248] In various embodiments, a duty cycle of the frequency 424 is different than that illustrated in Figure 4B. For example, instead of 60%, a duty cycle of the frequency 424 ranges from and including 20% to 80%.

[00249] It should be noted that any parameter level of the RF signal 122 is an envelope, such as a peak-to-peak amplitude or a zero-to-peak amplitude, of multiple parameter values of the RF signal 122. For example, each of the parameter levels PR1, PR2, PR3, PR11, PR21, PR31, PR41, PR111, PR211, PR311, PR411, and PR5ll is a peak-to-peak amplitude of magnitudes of the parameter of the RF signal 122.

[00250] Similarly, it should be noted that any frequency level of the RF signal 122 is an envelope, such as a peak-to-peak amplitude or a zero-to-peak amplitude, of multiple frequency values of the RF signal 122. For example, each of the frequency levels fl and f2 is a peak-to-peak amplitude of magnitudes of the frequency of the RF signal 122.

[00251] It should be noted that the state Sl of the parameter 212 is the same as the state Sl of the digital pulse signal 204 of figure 2A or 2B. Similarly, the state S2 of the parameter 212 is the same as the state S2 of the digital pulse signal 204 of figure 2A or 2B and the state S3 of the parameter 212 is the same as the state S3 of the digital pulse signal 204 of figure 2A or 2B. Similarly, the state Sl of the parameter 312 of figure 3A, or 3B, or 3C, 3D is the same as the state Sl of the digital pulse signal 304 of figure 3A, or 3B, or 3C, 3D. Similarly, the state S2 of the parameter 312 is the same as the state S2 of the digital pulse signal 304, the state S3 of the parameter 312 is the same as the state S3 of the digital pulse signal 304, and the state S4 of the parameter 312 is the same as the state S4 of the digital pulse signal 304. The state Sl of the parameter 412 of figure 4 A and 4B is the same as the state Sl of the digital pulse signal 404 of figure 4 A or 4B. Similarly, the state S2 of the parameter 412 is the same as the state S2 of the digital pulse signal 404, the state S3 of the parameter 412 is the same as the state S3 of the digital pulse signal 404, the state S4 of the parameter 412 is the same as the state S4 of the digital pulse signal 404, and the state S5 of the parameter 412 is the same as the state S5 of the digital pulse signal 404.

[00252] Figure 5A is an embodiment of a graph 502 to illustrate an angular distribution, such as a peak energy angular distribution, of ions of plasma within a plasma reactor (not shown) when a continuous wave voltage signal of 200 volts is applied as a bias voltage Vb to a wafer support (not shown) within the plasma reactor. The graph 502 plots energy of ions of plasma within the plasma reactor versus the angular distribution.

[00253] Figure 5B is an embodiment of a graph 504 to illustrate the angular distribution of ions of plasma within the plasma reactor when a continuous wave voltage signal of 400 volts is applied as the bias voltage to the wafer support. The graph 504 plots energy of ions of plasma within the plasma reactor versus the angular distribution.

[00254] Figure 5C is an embodiment of a graph 506 to illustrate the angular distribution of ions of plasma within the plasma reactor when a continuous wave voltage signal of 800 volts is applied as the bias voltage to the wafer support. The graph 506 plots energy of ions of plasma within the plasma reactor versus the angular distribution.

[00255] Figure 5D is an embodiment of a graph 508 to illustrate the angular distribution of ions of plasma within the reactor when a continuous wave voltage signal of 1600 volts is applied as the bias voltage to the wafer support. The graph 508 plots energy of ions of plasma within the reactor versus the angular distribution.

[00256] It should be noted that as illustrated in the graphs 502-508, the angular distribution decreases with an increase in a magnitude of a continuous wave voltage signal applied to the wafer support. For example, with an increase in the magnitude of the continuous wave voltage signal from 200 volts to 1600 volts, the angular distribution decreases.

[00257] It should further be noted that the RF signal 122 of figure 1 is not a continuous wave voltage signal. For example, the RF signal 122 is a pulse signal that pulses between two or more states, such as the states Sl through S5 of the parameter. As another example, a difference between a magnitude of a parameter level of one of the states Sl through S5 of the RF signal 122 is outside the predefined range, such as 20%, compared to a magnitude of a parameter level of another one of the states Sl through S5.

[00258] Figure 5E is an embodiment of the graph 510 to illustrate a decrease in the angular distribution with the increase in a voltage of a continuous wave signal. The graph 510 plots the angular distribution versus the bias voltage. A plot 510A of the graph 510 illustrates the angular distribution when the bias voltage of 200 volts is applied to the wafer support. Similarly, a plot 510B of the graph 510 illustrates the angular distribution when the bias voltage of 400 volts is applied to the wafer support, a plot 510C of the graph 510 illustrates the angular distribution when the bias voltage of 800 volts is applied to the wafer support, and a plot 510D of the graph 510 illustrates the angular distribution when the bias voltage of 1600 volts is applied to the wafer support. As shown from the plots 510 A to 510D, there is a decrease in the angular distribution with the increase in the bias voltage.

[00259] Figure 5F is an embodiment of a graph 512 to illustrate an energy of ions of plasma within the plasma reactor versus the angular distribution when a continuous wave voltage signal of 300 volts is applied to the wafer support.

[00260] Figure 5G is an embodiment of a graph 514 to illustrate an energy of ions of plasma within the plasma chamber 112 of figure 1 when two-level pulsing of the parameter of the RF signal 122 of figure 1 is applied to the substrate support 114 (figure 1) and the RF signal 122 has the constant frequency level. The graph 514 plots an energy of ions of plasma within the plasma chamber 112 versus the angular spread of the ions within the plasma chamber 112. The two-level pulsing of the RF signal 122 includes pulsing parameter levels the RF signal 122 between the two states Sl and S2 and does not include the states S3 through S5.

[00261] Figure 5H an embodiment of a graph 516 to illustrate an energy of ions of plasma within the plasma chamber 112 of figure 1 when three-level pulsing of the parameter of the RF signal 122 of figure 1 is applied to the substrate support 114 (figure 1) and the RF signal 122 has the constant frequency level. The graph 516 plots an energy of ions of plasma within the plasma chamber 112 versus the angular spread of the ions within the plasma chamber 112. The three-level pulsing of the parameter of the RF signal 122 includes pulsing parameter levels of the RF signal 122 among the three states Sl through S3 and does not include the states S4 through S5. For example, the graph 210 of figures 2A and 2B illustrate the three-level pulsing of the parameter of the RF signal 122. Moreover, the graph 516 is generated when the RF signal 122 has the constant frequency level. For example, a frequency of the RF signal 122 is not pulsed and is continuous. [00262] Figure 51 is an embodiment of a graph 518 to illustrate an energy of ions of plasma within the plasma chamber 112 of figure 1 when three-level pulsing of the parameter of the RF signal 122 of figure 1 is applied to the substrate support 114 (figure 1) in addition to applying two-level pulsing of the frequency of the RF signal 122. The graph 518 plots an energy of ions of plasma within the plasma chamber 112 versus the angular spread of the ions within the plasma chamber 112. The two-level pulsing of the frequency of the RF signal 122 is pulsing frequency levels the RF signal 122 between the two states SO and Sl. The two-level pulsing of the frequency of the RF signal 122 is illustrated in the graph 214 of figure 2 A and the graph 222 of figure 2B.

[00263] Figure 5J is an embodiment of a graph 520 to illustrate an energy of ions of plasma within the plasma chamber 112 of figure 1 when five-level pulsing of the parameter of the RF signal 122 of figure 1 is applied to the substrate support 114 (figure 1) and the RF signal 122 has the constant frequency level. The graph 520 plots an energy of ions of plasma within the plasma chamber 112 versus the angular spread of the ions within the plasma chamber 112. The five-level pulsing of the parameter of the RF signal 122 is pulsing parameter levels the RF signal 122 among the five states Sl through S5. The five-level pulsing of the parameter of the RF signal 122 is illustrated in the graph 410 of figures 4A and 4B. As illustrated in the graphs 514, 516, 518, and 520, the angular spread at a top of a channel formed within the mask layer is lower than the angular distribution, which is illustrated in the graphs 502, 504, 506, 508, and 512. In addition, energy of ions of plasma within the plasma chamber 112 is lower at a bottom of the channel compared to energy of ions of plasma within the plasma reactor achieved using a continuous wave voltage signal. Furthermore, as illustrated from the graphs 516, 580, and 520, with an increase in the number of levels of the parameter of the RF signal 122, there is an increase in the mask selectivity associated with the substrate 118 of figure 1.

[00264] Figure 5K is an embodiment of a graph 522 to illustrate a comparison between the angular distribution achieved using a continuous wave voltage signal and the angular spread achieved using multi-level pulsing of the parameter of the RF signal 122. The graph 522 plots the angular distribution for a continuous wave voltage signal and plots the angular spread for multi-level pulsing of the parameter. The graph 522 has a plot 522A of the angular distribution for a continuous wave voltage signal, has a plot 522B of the angular spread for the two-level pulsing of the parameter of the RF signal 122 and the constant frequency level of the RF signal 122, has a plot 522C for the three-level pulsing of the parameter of the RF signal 122 and the constant frequency level of the RF signal 122, has a plot 522D for the three-level pulsing of the parameter of the RF signal 122 and the two-level pulsing of the frequency of the RF signal 122, and has a plot 522E for the five-level pulsing of the RF signal 122 and the constant frequency level of the RF signal 122. It should be noted that the angular spread for any of the plots 522B through 522E is lower than the angular distribution for the plot 522A.

[00265] Figure 6A is an embodiment of a graph 602 that is generated when a continuous wave voltage signal is applied to the wafer support of the plasma reactor. The graph 602 plots an energy of ions of plasma within the plasma reactor versus an angular distribution of ions of the plasma.

[00266] Figure 6B is an embodiment of a graph 604 that is generated when the five-level pulsing of the parameter of the RF signal 122 (figure 1) and the constant frequency level, such as 1 megahertz, of the RF signal 122 are applied to the substrate support 114 of figure 1. The graph 604 plots an energy of ions of plasma within the plasma chamber 112 of figure 1 versus the angular spread of the ions.

[00267] Figure 6C is an embodiment of a graph 606 that is generated when the five-level pulsing of the parameter of the RF signal 122 (figure 1) and the constant frequency level, such as 2 megahertz, of the RF signal 122 are applied to the substrate support 114 of figure 1. The graph 606 plots an energy of ions of plasma within the plasma chamber 112 of figure 1 versus the angular spread of the ions.

[00268] Figure 6D is an embodiment of a graph 608 that is generated when the three-level pulsing of the parameter of the RF signal 122 (figure 1) and the two-level pulsing of the frequency of the RF signal 122 are applied to the substrate support 114 of figure 1. The graph 608 plots an energy of ions of plasma within the plasma chamber 112 of figure 1 versus the angular spread of the ions.

[00269] Figure 6E is an embodiment of a graph 610 that is generated when the three-level pulsing of the parameter of the RF signal 122 (figure 1) and the two-level pulsing of the frequency of the RF signal 122 are applied to the substrate support 114 of figure 1. The graph 610 plots an energy of ions of plasma within the plasma chamber 112 of figure 1 versus the angular spread of the ions.

[00270] Figure 6F is an embodiment of a graph 612 that is generated when the five-level pulsing of the parameter of the RF signal 122 (figure 1) and the two-level pulsing of the frequency of the RF signal 122 are applied to the substrate support 114 of figure 1. The graph 612 plots an energy of ions of plasma within the plasma chamber 112 of figure 1 versus the angular spread of the ions. [00271] As illustrated from the graphs 602, 604, 606, 608, 610, and 612, the angular spread at the bottom of the channel for multi-level pulsing of the parameter is lower compared to the angular distribution for a continuous wave signal. The angular spread at the bottom of the channel is achieved when multi-level pulsing of the parameter of the RF signal 122 is applied to the substrate support 114 of figure 1. Moreover, the angular distribution is achieved when a continuous wave voltage signal is applied to the wafer support of the plasma reactor.

[00272] Figure 7A is an embodiment of a graph 702 that is generated when a continuous wave voltage signal is applied to the wafer support of the plasma reactor. The graph 702 plots an energy of ions of plasma within the plasma reactor versus the angular distribution of ions of the plasma.

[00273] Figure 7B is an embodiment of a graph 704 that is generated when the two-level pulsing of the parameter of the RF signal 122 (figure 1) and the constant frequency level of the RF signal 122 are applied to the substrate support 114 of figure 1. The graph 704 plots an energy of ions of plasma within the plasma chamber 112 of figure 1 versus the angular spread of the ions.

[00274] Figure 7C is an embodiment of a graph 706 that is generated when the two-level pulsing of the parameter of the RF signal 122 (figure 1) and the constant frequency level of the RF signal 122 are applied to the substrate support 114 of figure 1. The graph 706 plots an energy of ions of plasma within the plasma chamber 112 of figure 1 versus the angular spread of the ions.

[00275] Figure 7D is an embodiment of a graph 708 that is generated when the three-level pulsing of the parameter of the RF signal 122 (figure 1) and the two-level pulsing of the frequency of the RF signal 122 are applied to the substrate support 114 of figure 1. The graph 708 plots an energy of ions of plasma within the plasma chamber 112 of figure 1 versus the angular spread of the ions.

[00276] Figure 7E is an embodiment of a graph 710 that is generated when the five-level pulsing of the parameter of the RF signal 122 (figure 1) and the two-level pulsing of the frequency of the RF signal 122 are applied to the substrate support 114 of figure 1. The graph 710 plots an energy of ions of plasma within the plasma chamber 112 of figure 1 versus the angular spread of the ions. As illustrated from the graphs 702, 704, 706, 708, and 710, the angular spread at the bottom of the channel for multi-level pulsing of the parameter is lower compared to the angular distribution for a continuous wave voltage signal. [00277] Figure 8A is an embodiment of a graph 802 that plots a DC bias at the substrate support 114 of figure 1 versus the time t. The graph 802 is plotted when the two- level pulsing of the parameter and the constant frequency level of the RF signal 122 are applied to the substrate support 114.

[00278] Figure 8B is an embodiment of a graph 804 that plots the DC bias at the substrate support 114 of figure 1 versus the time t. The graph 804 is plotted when the three- level pulsing of the parameter and the constant frequency level of the RF signal 122 are applied to the substrate support 114.

[00279] Figure 8C is an embodiment of a graph 806 that plots the DC bias at the substrate support 114 of figure 1 versus the time t. The graph 806 is plotted when the three- level pulsing of the parameter and the two-level pulsing of the frequency of the RF signal 122 are applied to the substrate support 114.

[00280] Figure 8D is an embodiment of a graph 808 that plots the DC bias at the substrate support 114 of figure 1 versus the time t. The graph 808 is plotted when the five- level pulsing of the parameter and the constant frequency level of the RF signal 122 are applied to the substrate support 114. By comparing the graphs 802 through 808, it is shown that with an increase in a number of levels for which the parameter of the RF signal 122 is pulsed, there is an increase in the DC bias. The increase in the DC bias increases a voltage of a plasma sheath of plasma within the plasma chamber 112 of figure 1. The increase in the voltage of the plasma sheath enhances energy of ions of plasma within the plasma chamber 112 and the increase in the energy decrease the angular spread of the ions.

[00281] A voltage of plasma sheath of plasma within the plasma chamber 112 charges and discharges based on an equation Vni _ghj v _ak = Vm _gh + V _LOW e ^(_t/RC) , where Vni _gh is a voltage level during a high state, such as the state S3, or S4, or S5, V _LOW is a voltage level during a low state, such as the state Sl or S2, t is the time, RC is a resistor capacitor (RC) time constant, and Vni _ghj v _ak is the voltage of the plasma sheath. As the voltage level increases from the low state to the high state, one plasma sheath develops on another plasma sheath, based on the equation, to form a unified plasma sheath. A cumulative voltage of the unified plasma sheath increases to result in a higher sheath voltage, such as that illustrated in Figures 8A through 8D.

[00282] Figure 9A is an embodiment of a graph 902 to illustrate a sheath voltage 902 A of plasma formed within the plasma reactor when an RF signal 902B, which is a continuous wave voltage signal, is applied to the wafer support. The graph 902 plots the RF signal 902B versus the time t. As illustrated in the graph 902, the sheath voltage 902A is constant.

[00283] Figure 9B is an embodiment of a graph 904 to illustrate a sheath voltage 904A of plasma formed within the plasma chamber 112 of figure 1 when an RF signal 904B is applied to the substrate support 114 of figure 1. The graph 904 plots the RF signal 904B versus the time t. The RF signal 904B is an example of the RF signal 122 of figure 1. The RF signal 904B illustrates the two-level pulsing of the RF signal 122. For example, the RF signal 904B pulses between a parameter level 908 and another parameter level 910. The RF signal 904B is a sinusoidal signal. The parameter level 910 is greater than the parameter level 908. The parameter level 910 is achieved during the state Sl and the parameter level 908 is achieved during the state S2.

[00284] Figure 9C is an embodiment of a graph 906 to illustrate a sheath voltage 906A of plasma formed within the plasma chamber 112 of figure 1 when an RF signal 906B is applied to the substrate support 114 of figure 1. The graph 906 plots the RF signal 906B versus the time t. The RF signal 906B is an example of the RF signal 122 of figure 1 and is a sinusoidal signal. The RF signal 906B illustrates multi-level pulsing of the parameter of the RF signal 122. For example, the RF signal 906B pulses among a parameter level 912, a parameter level 914, a parameter level 916, and a parameter level 918. The parameter level 918 is greater than the parameter level 916 which is greater than the parameter level 914. The parameter level 914 is greater than the parameter level 912. The parameter level 912 is achieved during the state Sl, the parameter level 914 is achieved during the state S2, the parameter level 916 is achieved during the state S3, and the parameter level 918 is achieved during the state S4.

[00285] As illustrated with respect to Figures 9A through 9C, there is an amplitude modulation of the RF signal 122 due to charging and discharging of plasma sheath of plasma within the plasma chamber 112 of figure 1. As a number of parameter levels of the RF signal 122 increases, envelopes, such as the parameter levels 908, 910, 908, 912, 914, 916, and 918, changes with a slower rate that ions of plasma within the plasma chamber 112 can follow and respond to. For example, the sheath voltage 906A increases with a slower rate compared to the sheath voltage 904A. The slower rate of increase in the sheath voltage 906A increases energy of ions within the plasma chamber 112 of figure 1. The increase in the energy of ions increases an etch rate of etching the substrate 118 and improves, such as decreases, the critical dimension of the substrate 118. [00286] Figure 10A is an embodiment of a graph 1002 that plots the DC bias at the substrate support 114 of figure 1 generated by the RF signal 122 (figure 1) versus the time t. The graph 1002 is generated when multi-level pulsing of the parameter of the RF signal 122 and the constant frequency level of the RF signal 122 are applied to the substrate support 114. It should be noted that the RC time constant of the DC bias plotted in the graph 1002 is approximately 40 microseconds (ps).

[00287] Figure 10B is an embodiment of a graph 1006 that plots the DC bias at the substrate support 114 of figure 1 generated by the RF signal 122 (figure 1) versus the time t. The graph 1006 is generated when multi-level pulsing of the parameter of the RF signal 122 and the two-level pulsing of the frequency of the RF signal 122 are applied to the substrate support 114. It should be noted that the RC time constant of the DC bias plotted in the graph 1002 is approximately 200 ps. Accordingly, there is an increase in the RC time constant when the frequency of the RF signal 122 is pulsed compared to when the frequency of the RF signal 122 is at the constant frequency level. The increase in the RC time constant facilitates an increase in a sheath voltage of plasma within the plasma chamber 112 of figure 1. Moreover, the increase in the RC time constant increases a number of peak energy ions of plasma within the plasma chamber 112. The increase in the number of peak energy ions increases energy of the ions and the increase in the energy increases an etch rate of etching the substrate 118.

[00288] As illustrated in Figures 10A and 10B, since application of the frequency levels fl and f2 increases the RC time constant of plasma sheath of plasma within the plasma chamber 112, during a transition from a high parameter level, such as a parameter level during the state S3, or S4, or S5, to a low parameter level, such as the state Sl, and during a transition from a high frequency level, such as the frequency level f2, to a low frequency level, such as the frequency level fl, peak energy of ions of plasma within the plasma chamber 112 is sustained longer to increase peak ion energy during the low parameter level and the low frequency level to increase an etch rate for etching the substrate 118 of Figure 1.

[00289] Figure 11 A is an embodiment of a graph 1102 that plots a vertical distance Z, measured in nanometers (nm), versus a horizontal distance R, also measured in nm. The graph 1102 is generated when the continuous wave voltage signal is applied to the wafer support of the plasma reactor. The graph 1102 plots the vertical distance of a mask layer 1102 A and the vertical distance of a substrate layer 1102B. The vertical distance of a layer is a height of the layer. Moreover, the graph 1102 plots a critical dimension of a channel formed within the mask layer 1102 A during an etch operation. In addition, the graph 1102 plots the critical dimension of the channel formed within the substrate layer 1102B. A critical dimension of a channel formed within a layer is a thickness th, which is measured in nm, of the channel.

[00290] Figure 11B is an embodiment of a graph 1104 that plots the vertical distance Z versus the horizontal distance R. The graph 1104 is generated when the two-level pulsing of the parameter of the RF signal 122 of figure 1 and the constant frequency level are applied to the substrate support 114 of figure 1. The graph 1104 plots the vertical distance of a mask layer 1104A of the substrate 118 of figure 1 and the vertical distance of a substrate layer 1104B of the substrate 118. Moreover, the graph 1104 plots the critical dimension of a channel formed within the mask layer 1104 A during an etch operation. In addition, the graph 1104 plots the critical dimension of the channel formed within the substrate layer 1104B.

[00291] Figure 11C is an embodiment of a graph 1106 that plots the vertical distance Z versus the horizontal distance R. The graph 1106 is generated when the three-level pulsing of the parameter of the RF signal 122 of figure 1 and the constant frequency level are applied to the substrate support 114 of figure 1. The graph 1106 plots the vertical distance of a mask layer 1106A of the substrate 118 of figure 1 and the vertical distance of a substrate layer 1106B of the substrate 118. Moreover, the graph 1106 plots the critical dimension of a channel formed within the mask layer 1106 A during an etch operation. In addition, the graph 1106 plots the critical dimension of the channel formed within the substrate layer 1106B.

[00292] Figure 11D is an embodiment of a graph 1108 that plots the vertical distance Z versus the horizontal distance R. The graph 1108 is generated when the three-level pulsing of the parameter of the RF signal 122 of figure 1 and the two-level pulsing of the frequency of the RF signal 122 are applied to the substrate support 114 of figure 1. The graph 1108 plots the vertical distance of a mask layer 1108A of the substrate 118 of figure 1 and the vertical distance of a substrate layer 1108B of the substrate 118. Moreover, the graph 1108 plots the critical dimension of a channel formed within the mask layer 1108 A during an etch operation. In addition, the graph 1108 plots the critical dimension of the channel formed within the substrate layer 1108B.

[00293] Figure 11E is an embodiment of a graph 1110 that plots the vertical distance Z versus the horizontal distance R. The graph 1110 is generated when the five-level pulsing of the parameter of the RF signal 122 of figure 1 and the constant frequency level of the RF signal 122 are applied to the substrate support 114 of figure 1. The graph 1110 plots the vertical distance of a mask layer 1110A of the substrate 118 of figure 1 and the vertical distance of a substrate layer 1110B of the substrate 118. Moreover, the graph 1110 plots the critical dimension of a channel formed within the mask layer 1110A during an etch operation. In addition, the graph 1110 plots the critical dimension of the channel formed within the substrate layer 1110B.

[00294] It should be noted that multi-level pulsing of the parameter of the RF signal 122 in conjunction with the constant frequency level or in conjunction with the two- level pulsing of the frequency of the RF signal 122 increases an etch rate of etching the substrate 122 of figure 1 during an etch operation. Moreover, multi-level pulsing of the parameter of the RF signal 122 in conjunction with the constant frequency level or in conjunction with the two-level pulsing of the frequency of the RF signal 122 decreases a critical dimension of a channel formed within the mask layer of the substrate 118 compared to the critical dimension of the channel formed within the mask layer 1102A of figure 11 A. Moreover, multi-level pulsing of the parameter of the RF signal 122 in conjunction with the constant frequency level or in conjunction with the two-level pulsing of the frequency of the RF signal 122 decreases the critical dimension of a channel formed within the substrate layer of the substrate 118 compared to the critical dimension of the channel formed within the substrate layer 1102B of figure 11 A.

[00295] Figure 11F is an embodiment of a graph 1112 that plots the vertical distance of a mask layer 1112A versus the horizontal distance of the mask layer 1112A. It should be noted that the mask layer 1112A is not yet processed, such as etched.

[00296] Figure 11G is an embodiment of a graph 1114 that plots the vertical distance of the mask layer 1102A versus the horizontal distance of the mask layer 1102A. The graph 1114 is generated when the continuous wave voltage signal is applied to the wafer support of the plasma reactor. Moreover, the graph 1114 plots the critical dimension of the channel formed within the mask layer 1102A during an etch operation.

[00297] Figure 11H is an embodiment of a graph 1116 that plots the vertical distance of the mask layer 1104A versus the horizontal distance of the mask layer 1104A. The graph 1116 is generated when the two-level pulsing of the parameter of the RF signal 122 of figure 1 and the constant frequency level are applied to the substrate support 114 of figure 1. Moreover, the graph 1116 plots the critical dimension of the channel formed within the mask layer 1104B during an etch operation.

[00298] Figure 111 is an embodiment of a graph 1118 that plots the vertical distance of the mask layer 1106A versus the horizontal distance of the mask layer 1106A. The graph 1118 is generated when the three-level pulsing of the parameter of the RF signal 122 of figure 1 and the constant frequency level are applied to the substrate support 114 of figure 1. Moreover, the graph 1118 plots the critical dimension of the channel formed within the mask layer 1106A during an etch operation.

[00299] Figure 11J is an embodiment of a graph 1120 that plots the vertical distance of the mask layer 1108A versus the horizontal distance of the mask layer 1108A. The graph 1120 is generated when the three-level pulsing of the parameter of the RF signal 122 of figure 1 and the two-level pulsing of the frequency of the RF signal 122 are applied to the substrate support 114 of figure 1. Moreover, the graph 1120 plots the critical dimension of the channel formed within the mask layer 1108 A during an etch operation.

[00300] Figure 11K is an embodiment of a graph 1122 that plots the vertical distance of the mask layer 1110A versus the horizontal distance of the mask layer 1110A. The graph 1112 is generated when the five-level pulsing of the parameter of the RF signal 122 of figure 1 and the constant frequency level of the RF signal 122 are applied to the substrate support 114 of figure 1. Moreover, the graph 1122 plots the critical dimension of the channel formed within the mask layer 1110A during an etch operation.

[00301] It should be noted that multi-level pulsing of the parameter of the RF signal 122 in conjunction with the constant frequency level or in conjunction with the two- level pulsing of the frequency of the RF signal 122 increases mask selectivity during an etch operation. For example, the critical dimension of the channel of the mask layer of the substrate 118 of figure 1 decreases when multi-level pulsing of the parameter of the RF signal 122 is applied in conjunction with the constant frequency level or in conjunction with the two-level pulsing of the frequency of the RF signal 122. The critical dimension of the channel of the mask layer of the substrate 118 of figure 1 decreases compared to the critical dimension of the channel of the mask layer 1102 A of figure 11G.

[00302] Figure 11L is an embodiment of a graph 1124 to illustrate a decrease in mask erosion when multi-level pulsing of the parameter of the RF signal 122 is applied in conjunction with the constant frequency level or in conjunction with the two-level pulsing of the frequency of the RF signal 122. The graph 1124 has a plot 1124A, which is generated when the continuous wave voltage signal is applied to the wafer support of the plasma reactor. In addition, the graph 1124 has another plot 1124B, which is generated when the two-level pulsing of the parameter of the RF signal 122 of figure 1 and the constant frequency level are applied to the substrate support 114 of figure 1. Moreover, the graph 1124 has another plot 1124C that is produced when the three-level pulsing of the parameter of the RF signal 122 of figure 1 and the constant frequency level are applied to the substrate support 114 of figure 1. [00303] Also, the graph 1124 has a plot 1124D that is generated when the three- level pulsing of the parameter of the RF signal 122 of figure 1 and the two-level pulsing of the frequency of the RF signal 122 are applied to the substrate support 114 of figure 1. In addition, the graph 1124 has a plot 1124E generated when the five-level pulsing of the parameter of the RF signal 122 of figure 1 and the constant frequency level of the RF signal 122 are applied to the substrate support 114 of figure 1.

[00304] It should be noted that there is the decrease in an erosion of the mask layer of the substrate 118 of figure 1 compared to an erosion of the mask layer 1102A of Figure 11G. The decrease in the erosion occurs when multi-level pulsing of the parameter of the RF signal 122 is applied in conjunction with the constant frequency level or in conjunction with the two-level pulsing of the frequency of the RF signal 122.

[00305] Figure 12 is a diagram of an embodiment of a system 1200 to illustrate a supply of a DC signal 1214 to the substrate support 114 while multi-level pulsing of the parameter and multi-level pulsing of the frequency of the RF signal 122 are applied to the substrate support 114. The system 1200 is the same as the system 100 of figure 1 except the system 1200 includes a driver system 1202, a DC power supply 1204, and an RF filter 1206. An example of the driver system 1202 includes one or more transistors that are coupled to each other. An example of the DC power supply 1204 is a power supply that supplies a constant parameter, such as a constant amount of voltage or a constant amount of power. The processor 108 is coupled to the driver system 1202 via a connection medium 1208.

[00306] Moreover, the driver system 1202 is coupled to the DC power supply 1204, which is coupled to the RF filter 1206. The RF filter 1206 is coupled to the substrate support 114 via a transmission medium 1210, such as a conductor or a cable. For example, the RF filter 1206 is coupled to the lower electrode of the substrate support 114 via the transmission medium 1210.

[00307] The processor 108 generates and sends a digital pulse signal 1212, such as a clock signal, via the connection medium 1208 to the driver system 1202. The digital pulse signal 1212 has multiple occurrences of a state SO and multiple occurrences of another state Sl. For example, the digital pulse signal 1212 pulses between the states SO and Sl. In addition, during the state SO of the digital pulse signal 1212, the processor 108 sends a parameter level, such as a parameter level DC1, or DC11, or DC111, of the DC signal 1214 to be generated by the DC power supply 1204. Similarly, during the state Sl of the digital pulse signal 1212, the processor 108 sends a parameter level, such as a parameter level DC0, or DC01, or DC001, of the DC signal 1214 to be generated by the DC power supply 1204. [00308] Upon receiving the digital pulse signal 1212 and the parameter level of the DC signal 1214 during an occurrence of the state SO of the digital pulse signal 1212, the driver system 1202 generates a current signal based on the parameter level of the DC signal 1214 for the state SO of the digital pulse signal 1212 and sends the current signal to the DC power supply 1204. For example, during the state Sl of the parameter 212 of figure 2A or figure 2B, the driver system 1202 sends the current signal to the DC power supply 1204. As another example, during the state Sl of the parameter 312 of figure 3A, or 3B, or 3C, or 3D, the driver system 1202 sends the current signal to the DC power supply 1204. As yet another example, during the state Sl of the parameter 412 of figure 4A and 4B, the driver system 1202 sends the current signal to the DC power supply 1204.

[00309] It should be noted that with reference to Figures 2 A and 2B, an occurrence of the state SO of the digital pulse signal 1212 occurs during the time period between the times tl2 and 0, another occurrence of the state SO of the digital pulse signal 1212 occurs during the time period between the times t42 and t32, and yet another occurrence of the state SO of the digital pulse signal 1212 occurs during the time period between the times t72 and t62. Similarly, with reference to Figures 3A through 3D, an occurrence of the state SO of the digital pulse signal 1212 occurs during the time period between the times tl3 and 0, another occurrence of the state SO of the digital pulse signal 1212 occurs during the time period between the times t53 and t43, and yet another occurrence of the state SO of the digital pulse signal 1212 occurs during the time period between the times t93 and t83. Moreover, with reference to Figures 4 A and 4B, an occurrence of the state SO of the digital pulse signal 1212 occurs during the time period between the times tl4 and 0 and another occurrence of the state SO of the digital pulse signal 1212 occurs during the time period between the times t64 and t54.

[00310] Upon receiving the current signal during the occurrence of the state SO of the digital pulse signal 1212, the DC power supply 1204 generates the DC signal 1214 having the parameter level DC1 or DC 11 or DC111, and supplies the DC signal 1214 to the lower electrode of the substrate support 114 via the RF filter 1206 and the transmission medium 1210. An example of the DC signal 1214 includes a DC voltage signal or a DC power signal. To illustrate, the DC signal 1214 has a positive amount of voltage or a positive amount of power. The DC signal 1214 is not sinusoidal. The DC signal 1214 during the state SO of the digital pulse signal 1212 has the parameter level DC1 or DC11 or DC111.

[00311] On the other hand, upon receiving the digital pulse signal 1212 and the parameter level of the DC signal 1214 during an occurrence of the state Sl of the digital pulse signal 1212, the driver system 1202 generates the current signal based on the parameter level of the DC signal 1214 for the state Sl of the digital pulse signal 1212 and sends the current signal to the DC power supply 1204. For example, during the states S2 and S3 of the parameter 212 of figure 2A or figure 2B, the driver system 1202 sends the current signal to the DC power supply 1204. As another example, during the states S2, S3, and S4 of the parameter 312 of figure 3A, or 3B, or 3C, or 3D, the driver system 1202 sends the current signal to the DC power supply 1204. As yet another example, during the states S2, S3, S4, and S5 of the parameter 412 of figure 4A and 4B, the driver system 1202 sends the current signal to the DC power supply 1204.

[00312] It should be noted that with reference to Figures 2 A and 2B, an occurrence of the state Sl of the digital pulse signal 1212 occurs during the time period between the times t32 and tl2, another occurrence of the state Sl of the digital pulse signal 1212 occurs during the time period between the times t62 and t42, and yet another occurrence of the state Sl of the digital pulse signal 1212 occurs during the time period between the times t92 and t72. Similarly, with reference to Figures 3 A through 3D, an occurrence of the state Sl of the digital pulse signal 1212 occurs during the time period between the times t43 and tl3, another occurrence of the state Sl of the digital pulse signal 1212 occurs during the time period between the times t83 and t53, and yet another occurrence of the state Sl of the digital pulse signal 1212 occurs during the time period between the times tl23 and t93. Moreover, with reference to Figures 4 A and 4B, an occurrence of the state Sl of the digital pulse signal 1212 occurs during the time period between the times t54 and tl4 and another occurrence of the state Sl of the digital pulse signal 1212 occurs during the time period between the times tl04 and t64.

[00313] Upon receiving the current signal during the occurrence of the state S 1 of the digital pulse signal 1212, the DC power supply 1204 generates the DC signal 1214 having the parameter level DC0 or DC01 or DC001, and supplies the DC signal 1214 to the lower electrode of the substrate support 114 via the RF filter 1206 and the transmission medium 1210. The DC signal 1214 during the state Sl of the digital pulse signal 1212 has the parameter level DC0 or DC01 or DC001.

[00314] With reference back to figure 12, in addition to supplying the modified RF signal 124 to the lower electrode of the substrate support 114 and the one or more process gases to the plasma chamber 112, the modified RF signal 146 is supplied to the TCP coil 116 and the DC signal 1214 is supplied to the lower electrode of the substrate support 114 to process the substrate 118. The RF filter 1206 filters out, such as removes, RF power that is reflected from the plasma chamber 112 via the transmission medium 1210 towards the DC power supply 1204 to protect the DC power supply 1204 from being damaged by the RF power.

[00315] It should be noted that in some embodiments, the parameter level PR1 (figures 2A and 2B) or PR11 (figures 3A-3D) or PR111 (figures 4A and 4B) of the RF signal 122 of figure 1 is substantially zero during the time period in which the DC signal 1214 is supplied by the DC power supply 1204 to replace the RF signal 122 with the DC signal 1214. For example, with reference to figures 2 A and 2B, the parameter level PR1 is zero or within a pre-defined limit from zero during the time period between the times tl2 and 0, during the time period between the times t42 and t32, and during the time period between the times t72 and t62. The pre-defined limit is stored in the memory device 110 to be accessed by the processor 106. An example of the pre-defined limit is within 0.5-10% from zero. To illustrate, the pre-defined limit is 1-10% greater than zero. As another example, with reference to figures 3 A through 3D, the parameter level PR11 is zero or within a pre-defined limit from zero during the time period between the times tl3 and 0, the time period between the times t53 and t43, and the time period between the times t93 and t83. As yet another example, with reference to figures 4 A and 4B, the parameter level PR111 is zero or within a pre-defined limit from zero during the time period between the times tl4 and 0 and the time period between the times t64 and t54.

[00316] When the parameter level PR1, or PR11, or PR111 is zero, the RF signal 122 is replaced with the DC signal 1214. The replacement of the parameter levels PR1 with the parameter level DC1 or of the parameter levels PR11 with the parameter level DC11 or of the parameter levels PR111 with the parameter level DC111 decelerates high energy ions of plasma within the plasma chamber 112 while preserving a low amount of the angular spread of the ions at low energies.

[00317] In various embodiments, any DC parameter levels, described herein, of the DC signal 1214 are provided from the processor 108 via the connection medium 1208 or another connection medium to driver system 1202. The DC parameter levels, described herein, of the DC signal 1214 are stored in the memory device 110.

[00318] Figure 13 A shows an embodiment of a graph 1302 to illustrate an example of the digital pulse signal 1212 of figure 12. Figure 13A also shows an embodiment of a graph 1306 to illustrate an example of a parameter 1308 of the DC signal 1214 of figure 12. The graph 1302 plots a digital pulse signal 1304 versus the time t. The digital pulse signal 1304 is an example of the digital pulse signal 1212. The digital pulse signal 1304 pulses, such as alternates, between the states SO and Sl. For example, the digital pulse signal 1304 pulses between the logic level 0 and 1 in the same manner in which the digital pulse signal 208 of figure 2A pulses between the logic levels 0 and 1. To illustrate, the digital pulse signal 1304 has the logic level of zero during a time period between zero and the time tl2 and has the logic level of one during a time period between the time tl2 and the time t32. Moreover, the digital pulse signal 1304 has the logic level of zero during a time period between t32 and the time t42 and has the logic level of one during a time period between the time t42 and the time t62. Also, the digital pulse signal 1304 has the logic level of zero during a time period between t62 and the time t72 and has the logic level of one during a time period between the time t72 and the time t92. The logic level of zero of the digital pulse signal 1304 is the state SO of the digital pulse signal 1304 and the logic level of one of the digital pulse signal 1304 is the state Sl of the digital pulse signal 1304.

[00319] The graph 1314 plots the parameter 1308 versus the time t. The parameter 1308 pulses between the parameter level DC1 and the parameter level DC0 and is substantially synchronized to the digital pulse signal 1302. For example, the parameter 1308 has the parameter level of DC1 during the state SO of the digital pulse signal 1304 and the parameter level of DC0 during the state Sl of the digital pulse signal 1304. To illustrate, the parameter 1308 has the parameter level of DC1 during the time period between zero and the time tl2 and has the parameter level of DC0 during the time period between the time tl2 and the time t32. As another illustration, the parameter 1308 has the parameter level of DC1 during the time period between t32 and the time t42, has the parameter level of DC0 during the time period between the time t42 and the time t62, has the parameter level of DC1 during the time period between t62 and the time t72, and has the parameter level of DC0 during the time period between the time t72 and the time t92.

[00320] As another illustration, the parameter 1308 transitions from the parameter level of DC0 to the parameter level DC1 at approximately the same time, such as at the time 0 or within the pre-defined time period from the time 0, at which the digital pulse signal 1302 transitions from the logic level 1 to the logic level 0. The parameter 1308 transitions from the parameter level DC1 to the parameter level DC0 at approximately the same time, such as at the time tl2 or within the pre-defined time period from the time tl2, at which the digital pulse signal 1304 transitions from the logic level 0 to the logic level 1. The parameter 1308 further transitions from the parameter level DC0 to the parameter level DC1 at approximately the same time, such as at the time t32 or within the pre-defined time period from the time t32, at which the digital pulse signal 1304 transitions from the logic level one to the logic level zero. [00321] The parameter 1308 transitions from the parameter level DC1 to the parameter level of DC0 at approximately the same time, such as at the time t42 or within the pre-defined time period from the time t42, at which the digital pulse signal 1304 transitions from the logic level 0 to the logic level 1. The parameter 1308 thereafter transitions from the parameter level DC0 to the parameter level DC1 at approximately the same time, such as at the time t62 or within the pre-defined time period from the time t62, at which the digital pulse signal 1304 transitions from the logic level 1 to the logic level 0. The parameter 1308 thereafter transitions from the parameter level DC1 to the parameter level DC0 at approximately the same time, such as at the time t72 or within the pre-defined time period from the time t72, at which the digital pulse signal 1304 transitions from the logic level 0 to the logic level 1. The parameter 1308 thereafter transitions from the parameter level DC0 to the parameter level DC1 at approximately the same time, such as at the time t92 or within the pre-defined time period from the time t92, at which the digital pulse signal 1304 transitions from the logic level 1 to the logic level 0.

[00322] An example of the parameter level DC0 ranges from and including 0% to 50% of a maximum parameter value. For example, all magnitudes of the parameter level DC0 are within 5% to 20% of the maximum parameter value. An example of the parameter level DC1 ranges from and including 80% to 100% of the maximum parameter value. As an example, the DC power supply 1204 is not capable of generating a value greater than the maximum parameter value.

[00323] It should be noted that the DC signal 1308 is synchronized substantially with the parameter 212 of the RF signal 122 of Figures 2A and 2B. For example, the DC signal 1308 has the parameter level of DC1 and the parameter 212 has the parameter level of PR1 during the time period between the times tl2 and 0, during the time period between the times t42 and t32, and during the time period between the times t72 and t62. As another example, the DC signal 1308 transitions from the parameter level DC1 to the parameter level DC0 at approximately the same time, such as at the time tl2 or within the pre-defined time period from the time tl2 and at the time t42 or within the pre-defined time period from the time t42 or at the time t72 or within the pre-defined time period from the time t72, at which the parameter 212 transitions from the parameter level PR1 to the parameter level PR2.

[00324] As another example, the DC signal 1308 has the parameter level of DC0 and the parameter 212 has the parameter level of PR2 during the time period between the times t22 and tl2, during the time period between the times t52 and t42, and during the time period between the times t82 and t72. As another example, the DC signal 1308 has the parameter level of DCO and the parameter 212 has the parameter level of PR3 during the time period between the times t32 and t22, during the time period between the times t62 and t52, and during the time period between the times t92 and t82. As yet another example, the DC signal 1308 transitions from the parameter level DCO to the parameter level DC1 at approximately the same time, such as at the time t32 or within the pre-defined time period from the time t32 and at the time t62 or within the pre-defined time period from the time t62 or at the time t92 or within the pre-defined time period from the time t92, at which the parameter 212 transitions from the parameter level PR3 to the parameter level PR1.

[00325] Figure 13B shows an embodiment of a graph 1310 to illustrate an example of the digital pulse signal 1212 of figure 12. Figure 13B also shows an embodiment of a graph 1314 to illustrate an example of a parameter 1316 of the DC signal 1214 of figure 12. The graph 1310 plots a digital pulse signal 1312 versus the time t. The digital pulse signal 1312 is an example of the digital pulse signal 1212. The digital pulse signal 1312 pulses, such as alternates, between states SO and Sl. For example, the digital pulse signal 1312 pulses between the logic level 0 and 1 in the same manner in which the digital pulse signal 308 of figure 3A pulses between the logic levels 0 and 1. To illustrate, the digital pulse signal 1312 has the logic level of zero during a time period between zero and the time tl3 and has the logic level of one during a time period between the time tl3 and the time t43. Moreover, the digital pulse signal 1312 has the logic level of zero during a time period between t43 and the time t53 and has the logic level of one during a time period between the time t53 and the time t83. Also, the digital pulse signal 1312 has the logic level of zero during a time period between t83 and the time t93 and has the logic level of one during a time period between the time t93 and the time tl23. The logic level of zero of the digital pulse signal 1312 is the state SO of the digital pulse signal 1312 and the logic level of one of the digital pulse signal 1312 is the state Sl of the digital pulse signal 1312.

[00326] The graph 1314 plots the parameter 1316 versus the time t. The parameter 1316 pulses between the parameter level DC 11 and another parameter level of DC01 and is synchronized to the digital pulse signal 1312. For example, the parameter 1316 has the parameter level of DC11 during the state SO of the digital pulse signal 1312 and the parameter level of DC01 during the state Sl of the digital pulse signal 1312. To illustrate, the parameter 1316 has the parameter level of DC 11 during the time period between zero and the time tl3 and has the parameter level of DC01 during the time period between the time tl3 and the time t43. As another illustration, the parameter 1316 has the parameter level of DC 11 during the time period between t43 and the time t53, has the parameter level of DC01 during the time period between the time period between t53 and the time t83, has the parameter level of DC11 during the time period between the time t83 and the time t93, and has the parameter level of DC01 during the time period between the time t93 and the time 123.

[00327] As another illustration, the parameter 1316 transitions from the parameter level DC01 to the parameter level DC11 at approximately the same time, such as at the time 0 or within the pre-defined time period from the time 0, at which the digital pulse signal 1312 transitions from the logic level 1 to the logic level 0. The parameter 1316 transitions from the parameter level DC 11 to the parameter level DC01 at approximately the same time, such as at the time tl3 or within the pre-defined time period from the time tl3, at which the digital pulse signal 1312 transitions from the logic level 0 to the logic level 1. The parameter 1316 further transitions from the parameter level DC01 to the parameter level DC 11 at approximately the same time, such as at the time t43 or within the pre-defined time period from the time t43, at which the digital pulse signal 1312 transitions from the logic level one to the logic level zero.

[00328] The parameter 1316 transitions from the parameter level DC 11 to the parameter level of DC01 at approximately the same time, such as at the time t53 or within the pre-defined time period from the time t53, at which the digital pulse signal 1312 transitions from the logic level 0 to the logic level 1. The parameter 1316 thereafter transitions from the parameter level DC01 to the parameter level DC11 at approximately the same time, such as at the time t83 or within the pre-defined time period from the time t83, at which the digital pulse signal 1312 transitions from the logic level 1 to the logic level 0. The parameter 1316 thereafter transitions from the parameter level DC 11 to the parameter level DC01 at approximately the same time, such as at the time t93 or within the pre-defined time period from the time t93, at which the digital pulse signal 1312 transitions from the logic level 0 to the logic level 1. The parameter 1316 thereafter transitions from the parameter level DC01 to the parameter level DC11 at approximately the same time, such as at the time tl23 or within the pre-defined time period from the time tl23, at which the digital pulse signal 1312 transitions from the logic level 1 to the logic level 0.

[00329] An example of the parameter level DC01 ranges from and including 0% to 50% of the maximum parameter value. For example, all magnitudes of the parameter level DC01 are within 5% to 20% of the maximum parameter value. An example of the parameter level DC11 ranges from and including 80% to 100% of the maximum parameter value.

[00330] It should be noted that the DC signal 1316 is synchronized substantially with the parameter 312 of Figures 3 A through 3D. For example, the DC signal 1316 has the parameter level of DC 11 and the parameter 312 has the parameter level of PR 11 during the time period between the times tl3 and 0, during the time period between the times t53 and t43, and during the time period between the times t93 and t83. As another example, the DC signal 1316 transitions from the parameter level DC 11 to the parameter level DC01 at approximately the same time, such as at the time tl3 or within the pre-defined time period from the time tl3 and at the time t53 or within the pre-defined time period from the time t53 or at the time t93 or within the pre-defined time period from the time t93 or at the time tl23 or within the pre-defined time period from the time tl23, at which the parameter 312 transitions from the parameter level PR11 to the parameter level PR21.

[00331] As another example, the DC signal 1316 has the parameter level of DC01 and the parameter 312 has the parameter level of PR21 during the time period between the times t23 and tl3, during the time period between the times t63 and t53, and during the time period between the times tl03 and t93. As another example, the DC signal 1316 has the parameter level of DC01 and the parameter 312 has the parameter level of PR31 during the time period between the times t33 and t23, during the time period between the times t73 and t63, and during the time period between the times tll3 and tl03. As yet another example, the DC signal 1316 has the parameter level of DC01 and the parameter 312 has the parameter level of PR41 during the time period between the times t43 and t33, during the time period between the times t83 and t73, and during the time period between the times tl23 and tll3. As yet another example, the DC signal 1316 transitions from the parameter level DC01 to the parameter level DC 11 at approximately the same time, such as at the time t43 or within the pre-defined time period from the time t43 and at the time t83 or within the pre-defined time period from the time t83 or at the time tl23 or within the pre-defined time period from the time tl23, at which the parameter 312 transitions from the parameter level PR41 to the parameter level PR11.

[00332] Figure 13C shows an embodiment of a graph 1318 to illustrate an example of the digital pulse signal 1212 of figure 12. Figure 13C also shows an embodiment of a graph 1324 to illustrate an example of a parameter 1324 of the DC signal 1214 of figure 12. The graph 1318 plots a digital pulse signal 1320 versus the time t. The digital pulse signal 1320 is an example of the digital pulse signal 1212. The digital pulse signal 1320 pulses, such as alternates, between states SO and Sl. For example, the digital pulse signal 1320 has the logic level of zero during the time period between zero and the time tl4 and has the logic level of one during the time period between the time tl4 and the time t54. Moreover, the digital pulse signal 1320 has the logic level of zero during the time period between t54 and the time t64 and has the logic level of one during the time period between the time t64 and the time tl04. The logic level of zero of the digital pulse signal 1320 is the state SO of the digital pulse signal 1320 and the logic level of one of the digital pulse signal 1320 is the state Sl of the digital pulse signal 1320.

[00333] The graph 1322 plots the parameter 1324 versus the time t. The parameter 1324 pulses between the parameter level DC111 and another parameter level of zero and is synchronized to the digital pulse signal 1320. For example, the parameter 1324 has the parameter level of DC111 during the state SO of the digital pulse signal 1320 and the parameter level of DC001 during the state Sl of the digital pulse signal 1320. To illustrate, the parameter 1324 has the parameter level of DC111 during the time period between zero and the time tl4 and has the parameter level of DC001 during the time period between the time tl4 and the time t54. As another illustration, the parameter 1324 has the parameter level of DC111 during the time period between t54 and the time t64, and has the parameter level of DC001 during the time period between the time t64 and the time tl04.

[00334] As another illustration, the parameter 1324 transitions from the parameter level DC001 to the parameter level DC111 at approximately the same time, such as at the time 0 or within the pre-defined time period from the time 0, at which the digital pulse signal 1320 transitions from the logic level 1 to the logic level 0. The parameter 1324 transitions from the parameter level DC111 to the parameter level DC001 at approximately the same time, such as at the time tl4 or within the pre-defined time period from the time tl4, at which the digital pulse signal 1320 transitions from the logic level 0 to the logic level 1. The parameter 1324 further transitions from the parameter level DC001 to the parameter level DC111 at approximately the same time, such as at the time t54 or within the pre-defined time period from the time t54, at which the digital pulse signal 1320 transitions from the logic level one to the logic level zero.

[00335] The parameter 1324 transitions from the parameter level DC111 to the parameter level of DC001 at approximately the same time, such as at the time t64 or within the pre-defined time period from the time t64, at which the digital pulse signal 1320 transitions from the logic level 0 to the logic level 1. The parameter 1320 thereafter transitions from the parameter level DC001 to the parameter level DC111 at approximately the same time, such as at the time tl04 or within the pre-defined time period from the time tl04, at which the digital pulse signal 1320 transitions from the logic level 1 to the logic level 0.

[00336] An example of the parameter level DC011 ranges from and including 0% to 50% of the maximum parameter value. For example, all magnitudes of the parameter level DC011 are within 5% to 20% of the maximum parameter value. An example of the parameter level DC111 ranges from and including 80% to 100% of the maximum parameter value.

[00337] It should be noted that the DC signal 1324 is synchronized substantially with the parameter 412 of Figures 4A and 4B. For example, the DC signal 1324 has the parameter level of DC111 and the parameter 412 has the parameter level of PR111 during the time period between the times tl4 and 0 and during the time period between the times t64 and t54. As another example, the DC signal 1324 transitions from the parameter level DC111 to the parameter level DC001 at approximately the same time, such as at the time tl4 or within the pre-defined time period from the time tl4 and at the time t64 or within the pre-defined time period from the time t64 or, at which the parameter 412 transitions from the parameter level PR111 to the parameter level PR211.

[00338] As another example, the DC signal 1324 has the parameter level of DC001 and the parameter 412 has the parameter level of PR211 during the time period between the times t24 and tl4 and during the time period between the times t74 and t64. As another example, the DC signal 1324 has the parameter level of DC001 and the parameter 412 has the parameter level of PR311 during the time period between the times t34 and t24 and during the time period between the times t84 and t74. As yet another example, the DC signal 1324 has the parameter level of DC001 and the parameter 412 has the parameter level of PR411 during the time period between the times t44 and t34 and during the time period between the times t94 and t84. As another example, the DC signal 1324 has the parameter level of DC001 and the parameter 412 has the parameter level of PR511 during the time period between the times t54 and t44 and during the time period between the times tl04 and t94. As yet another example, the DC signal 1324 transitions from the parameter level DC001 to the parameter level DC111 at approximately the same time, such as at the time t54 or within the pre-defined time period from the time t54 and at the time tl04 or within the pre-defined time period from the time tl04, at which the parameter 412 transitions from the parameter level PR511 to the parameter level PR111.

[00339] Figure 14A is a diagram of an embodiment of a system 1400 to illustrate multi-level pulsing of the parameter of an RF signal 1406 that is generated by an RF generator RFGC that is coupled to the TCP coil 116. The system 1400 and is the same as the system 100 of figure 1 except that the system 1400 includes the RF generator RFGC instead of the RF generator RFGB of Figure 1. The processor 108 is coupled to the RF generator RFGC via a connection medium 1404. The RF generator RFGC is coupled to the impedance patch 120 via the RF cable 130. The RF generator RFGC operates in a frequency range from and including 400 kHz to 60 MHz.

[00340] The processor 108 generates and sends a digital pulse signal 1402, such as a clock signal, via the connection medium 1402 to the RF generator RFGC. Upon receiving the digital pulse signal 1402, the RF generator RFGC generates an RF signal 1406 that pulses between multiple parameter levels, such as a parameter level PR1C and another parameter level PR2C, or a parameter level PR11C and another parameter level PR21C, or a parameter level PR111C and another parameter level PR211C. As an example, the parameter level PR1C is at most 20% of the parameter level PR2C and the parameter level PR2C is at 100% power or voltage that the RF generator RFGC is capable of supplying. Similarly, as an example, the parameter level PR11C is at most 20% of the parameter level PR21C and the parameter level PR21C is at 100% power or voltage that the RF generator RFGC is capable of supplying. As yet another example, the parameter level PR111C is at most 20% of the parameter level PR211C and the parameter level PR211C is at 100% power or voltage that the RF generator RFGC is capable of supplying. The RF signal 1406 is supplied from the RF generator RFGC via the RF cable 130 to the impedance match 120.

[00341] The impedance match 120 matches an impedance of the load coupled to the output of the impedance match 120 with that of a source, such as the RF generator RFGC and the RF cable 130, coupled to the input of the impedance match 120 to generate a modified RF signal 1408 from the RF signal 1406. The modified RF signal 1408 is sent from the impedance match 120 to the TCP coil 116. Upon receiving the modified RF signal 1408 in addition to receiving the modified RF signal 124 and the one or more process gases, plasma is stricken or maintained within the plasma chamber 112 to process the substrate 118. The application of the modified RF signal 1408 generated from the RF signal 1406 reduces the angular spread of ions of plasma within the plasma chamber 112 at low energies of the ions.

[00342] Figure 14B is a block diagram of an embodiment of the RF generator RFGC to illustrate components of the RF generator RFGC. The RF generator RFGC includes a digital signal processor DSPC, a parameter controller PRCS0, another parameter controller PRCS1, a driver system DRVRC, a frequency controller FC, and an RF power supply 1452. The digital signal processor DSPC is coupled via the connection medium 1404 to the processor 108. Moreover, the digital signal processor DSPC is coupled to the parameter controllers PRCS0 and PRCS1 and to the frequency controller FC. The frequency controller FC and the parameter controllers PRCS0 and PRCS1 are coupled to the driver system DRVRC, which is coupled to the RF power supply 1452. The RF power supply 1452 is coupled to the impedance match 120 via the RF cable 130.

[00343] Upon receiving the digital pulse signal 1402 from the processor 108, the digital signal processor DSPC identifies an occurrence of a state of the digital pulse signal 1402. For example, the digital signal processor DSPC determines whether the logic level of the digital pulse signal 1402 is greater or lower than the predetermined threshold. Upon determining that the logic level of the digital pulse signal 1402 is greater than the predetermined threshold, the digital signal processor DSPC identifies an occurrence of the state of the digital pulse signal 1402 to be Sl. On the other hand, upon determining that the logic level of the digital pulse signal 1402 is less than the predetermined threshold, the digital signal processor DSPC identifies an occurrence of the state of the digital pulse signal 1402 to be SO. As another example, the digital signal processor DSPC determines whether the logic level of the digital pulse signal 1402 is zero or one. Upon determining that the logic level of the digital pulse signal 1402 is one, the digital signal processor DSPC identifies the occurrence of the state of the digital pulse signal 1402 to be Sl. On the other hand, upon determining that the logic level of the digital pulse signal 1402 is zero, the digital signal processor DSPC identifies the occurrence of the state of the digital pulse signal 1402 to be SO.

[00344] Moreover, in response to identifying the occurrence of the state of the digital pulse signal 1402 to be SO, the digital signal processor DSPC sends a signal to the parameter controller PRCS0. Upon receiving the signal during the occurrence of the state SO of the digital pulse signal 1402, the parameter controller PRCS0 accesses a parameter level stored within the parameter controller PRCS0 and provides the parameter level to the driver system DRVRC. Examples of the parameter level, for the state SO of the digital pulse signal 1402, stored within the parameter controller PRCS0 include the parameter level PR1C or PR11C or PR111C (figures 15A-15C), which is further described below.

[00345] Also, in response to identifying the occurrence of the state of the digital pulse signal 1402 to be Sl, the digital signal processor DSPC sends a signal to the parameter controller PRCS1. Upon receiving the signal during the occurrence of the state Sl of the digital pulse signal 1402, the parameter controller PRCS1 accesses a parameter level stored within the parameter controller PRCS 1 and provides the parameter level to the driver system DRVRC. Examples of the parameter level, for the state Sl of the digital pulse signal 1402, stored within the parameter controller PRCS1 include the parameter level PR2C or PR21C or PR211C (figures 15A-15C), which is further described below. [00346] Moreover, in response to identifying the occurrence of the state of the digital pulse signal 1402 to be SO, the digital signal processor DSPC sends a signal to the frequency controller FC. Upon receiving the signal during the occurrence of the state SO of the digital pulse signal 1402, the frequency controller FC accesses a continuous frequency level stored within the frequency controller FC and provides the continuous frequency level to the driver system DRVRC. For example, a difference between any two values of the continuous frequency level is less than the preset range. To illustrate, a highest of values of the continuous frequency level is at most 20% from a lowest of the values of the continuous frequency level. As another example, the continuous frequency level is not pulsed between two or more frequency levels.

[00347] During the occurrence of the state SO of the digital pulse signal 1402, the driver system DRVRC generates a current signal based on the parameter level PR1C or PR11C or PR111C and the continuous frequency level and provides the current signal to the RF power supply 1452. Also, the RF power supply 1452 generates an RF signal 1406 upon receiving the current signal from the driver system DRVRC during the occurrence of the state SO of the digital pulse signal 1402. The RF signal 1406 has the parameter level PR1C and the continuous frequency level during the occurrence of the state SO of the digital pulse signal 1402.

[00348] Similarly, during the occurrence of the state Sl of the digital pulse signal 1402, the driver system DRVRC generates the current signal based on the parameter level PR2C or PR21C or PR211C and the continuous frequency level and provides the current signal to the RF power supply 1452. Also, the RF power supply 1452 generates the RF signal 1406 upon receiving the current signal from the driver system DRVRC during the occurrence of the state Sl of the digital pulse signal 1402. The RF signal 1406 has the parameter level PR2C and the continuous frequency level during the occurrence of the state S 1 of the digital pulse signal 1402.

[00349] In several embodiments, a combination of the digital signal processor DSPC, the parameter controllers PRCS0 through PRCS1, and the frequency controller FC are sometimes referred to herein as a controller. For example, each of the digital signal processor DSPC, the parameter controller PRCS0, the parameter controller PRCS1, and the frequency controller FC is a portion, such as a hardware circuit or a software module, of the controller.

[00350] In various embodiments, any parameter levels, described herein, of the RF signal 1406 are provided from the processor 108 via the connection medium 1404 or another connection medium to the digital signal processor DSPC. In some embodiments, any frequency levels, described herein, of the RF signal 1406 are provided from the processor 108 via the connection medium 1404 or another connection medium to the digital signal processor DSPC. The parameter levels and the frequency levels, described herein, of the RF signal 1406 are stored in the memory device 110.

[00351] Figure 15A shows an embodiment of a graph 1502 and an embodiment of another graph 1506 to illustrate pulsing of a parameter 1504 of the RF signal 1406 generated by the RF generator RFGC of figure 14A. The graph 1502 plots the parameter 1504 versus the time t. The graph 1506 plots a digital pulse signal 1508 versus the time t. The digital pulse signal 1508 is an example of the digital pulse signal 1402 of figure 14A.

[00352] The digital pulse signal 1508 transitions periodically between occurrences of the states SO and Sl. For example, during the time period between the times zero and tl2, the digital pulse signal 1508 has the logic level of zero, which is an occurrence of the state SO. Moreover, during the time period between the times tl2 and t32, the digital pulse signal 1508 has the logic level of one, which is an occurrence of the state Sl. In addition, during the time period between the times t32 and t42, the digital pulse signal 1508 has the logic level of zero, which is another occurrence of the state SO. Also, during the time period between the times t42 and t62, the digital pulse signal 1508 has the logic level of one, which is another occurrence of the state Sl. During the time period between the times t62 and t72, the digital pulse signal 1508 has the logic level of zero and during the time period between the times t72 and t92, the digital pulse signal 1508 has the logic level of one.

[00353] As another example, at the time tl2, the digital pulse signal 1508 transitions from the logic level 0 to the logic level 1 and at the time t32, the digital pulse signal 1508 transitions from the logic level 1 to the logic level 0. Similarly, at the time t42, the digital pulse signal 1508 transitions from the logic level 0 to the logic level 1 and at the time t62, the digital pulse signal 1508 transitions from the logic level 1 to the logic level 0. Also, at the time t72, the digital pulse signal 1508 transitions from the logic level 0 to the logic level 1 and at the time t92, the digital pulse signal 1508 transitions from the logic level 1 to the logic level 0.

[00354] The parameter 1504 is substantially synchronized with the digital pulse signal 1508. For example, during the state SO of the digital pulse signal 1508, the parameter 1504 has the parameter level PR1C and during the state Sl of the digital pulse signal 1508, the parameter 1504 has the parameter level PR2C. As another example, the parameter 1504 transitions from the parameter level PR1C to the parameter level PR2C at approximately the same time, such as at the time tl2 or within the pre-defined time period from the time tl2, at which the digital pulse signal 1508 transitions from the SO to the state Sl. The parameter 1504 transitions from the parameter level PR2C to the parameter level PR1C at approximately the same time, such as at the time t32 or within the pre-defined time period from the time t32, at which the digital pulse signal 1508 transitions from the Sl to the state SO. Moreover, the parameter 1504 transitions from the parameter level PR1C to the parameter level PR2C at approximately the same time, such as at the time t42 or within the pre-defined time period from the time t42, at which the digital pulse signal 1508 transitions from the SO to the state Sl. The parameter 1504 transitions from the parameter level PR2C to the parameter level PR1C at approximately the same time, such as at the time t62 or within the pre-defined time period from the time t62, at which the digital pulse signal 1508 transitions from the Sl to the state SO. Also, the parameter 1504 transitions from the parameter level PR1C to the parameter level PR2C at t approximately the same time, such as at the time t72 or within the pre-defined time period from the time t72, at which the digital pulse signal 1508 transitions from the SO to the state Sl. The parameter 1504 transitions from the parameter level PR2C to the parameter level PR1C at approximately the same time, such as at the time t92 or within the pre-defined time period from the time t92, at which the digital pulse signal 1508 transitions from the Sl to the state SO.

[00355] It should be noted that the parameter 1504 is substantially synchronized substantially with the parameter 212 of the RF signal 122 of Figures 2 A and 2B. For example, the parameter 1504 has the parameter level of PR1C and the parameter 212 of the RF signal 122 has the parameter level of PR1 during the time period between the times tl2 and 0, during the time period between the times t42 and t32, and during the time period between the times t72 and t62. As another example, the parameter 1504 transitions from the parameter level PR1C to the parameter level PR2C at approximately the same time, such as at the time tl2 or within the pre-defined time period from the time tl2 and at the time t42 or within the pre-defined time period from the time t42 or at the time t72 or within the pre defined time period from the time t72, at which the parameter 212 of the RF signal 122 transitions from the parameter level PR1 to the parameter level PR2.

[00356] As another example, the parameter 1504 has the parameter level of PR2C and the parameter 212 of the RF signal 122 has the parameter level of PR2 during the time period between the times t22 and tl2, during the time period between the times t52 and t42, and during the time period between the times t82 and t72. As another example, the parameter 1504 has the parameter level of PR2C and the parameter 212 of the RF signal 122 has the parameter level of PR3 during the time period between the times t32 and t22, during the time period between the times t62 and t52, and during the time period between the times t92 and t82. As yet another example, the parameter 1504 transitions from the parameter level PR2C to the parameter level PR1C at approximately the same time, such as at the time t32 or within the pre-defined time period from the time t32 and at the time t62 or within the pre-defined time period from the time t62 or at the time t92 or within the pre-defined time period from the time t92, at which the parameter 212 of the RF signal 122 transitions from the parameter level PR3 to the parameter level PR1.

[00357] An example of the parameter level PR1C is xl% of a maximum amount of power that is supplied to the TCP coil 116 of figure 14A. An example of xl% ranges from and including 0% to 50%. For example, xl% is 5% of the maximum amount of power. Similarly, an example of the parameter level PR2C is yl% of the maximum amount of power that is supplied to the TCP coil 116. An example of yl% ranges from and including 80% to 100%. As another example, yl% is the maximum amount of power.

[00358] It should be noted that the parameter level PR2C is greater than the parameter level PR1C. For example, the parameter level PR2C is greater by at least 20% compared to the parameter level PR1C. As another example, all magnitudes of the parameter at the parameter level PR2C are greater by at least 20% compared to all magnitudes of the parameter at the parameter level PR1C.

[00359] It should further be noted that by pulsing the parameter 1504 at a low level during a time period in which the parameter of the RF signal 122 of figure 14A is pulsed at the low level, low energy ions of plasma within the plasma chamber 112 having a low angular spread are generated. An example of the low level of the parameter 1504 is the parameter level PR1C and of a high level of the parameter 1504 is the parameter level PR2C.

[00360] The low energy ions having the low angular spread provide a faster etch rate and reduce the critical dimension of the substrate layer of the substrate 118. Moreover, the low energy ions having the low energy spread increase mask selectivity of the mask layer of the substrate 118.

[00361] Figure 15B shows an embodiment of a graph 1514 and an embodiment of another graph 1510 to illustrate pulsing of a parameter 1512 of the RF signal 1406 generated by the RF generator RFGC of figure 14A. The graph 1510 plots the parameter 1512 versus the time t. The graph 1506 plots a digital pulse signal 1516 versus the time t. The digital pulse signal 1516 is an example of the digital pulse signal 1402 of figure 14A.

[00362] The digital pulse signal 1516 transitions periodically between occurrences of the states SO and Sl. For example, during the time period between the times zero and tl3, the digital pulse signal 1516 has the logic level of zero, which is an occurrence of the state SO. Moreover, during the time period between the times tl3 and t43, the digital pulse signal 1516 has the logic level of one, which is an occurrence of the state Sl. In addition, during the time period between the times t43 and t53, the digital pulse signal 1516 has the logic level of zero, which is another occurrence of the state SO. Also, during the time period between the times t53 and t83, the digital pulse signal 1516 has the logic level of one, which is another occurrence of the state Sl. During the time period between the times t83 and t93, the digital pulse signal 1516 has the logic level of zero and during the time period between the times t93 and tl23, the digital pulse signal 1516 has the logic level of one.

[00363] As another example, at the time tl3, the digital pulse signal 1516 transitions from the logic level 0 to the logic level 1 and at the time t43, the digital pulse signal 1516 transitions from the logic level 1 to the logic level 0. Similarly, at the time t53, the digital pulse signal 1516 transitions from the logic level 0 to the logic level 1 and at the time t83, the digital pulse signal 1516 transitions from the logic level 1 to the logic level 0. Also, at the time t93, the digital pulse signal 1516 transitions from the logic level 0 to the logic level 1 and at the time tl23, the digital pulse signal 1516 transitions from the logic level 1 to the logic level 0.

[00364] The parameter 1512 is substantially synchronized with the digital pulse signal 1516. For example, during the state SO of the digital pulse signal 1516, the parameter 1512 has the parameter level PR11C and during the state Sl of the digital pulse signal 1516, the parameter 1512 has the parameter level PR21C. As another example, the parameter 1512 transitions from the parameter level PR11C to the parameter level PR21C at approximately the same time, such as at the time tl3 or within the pre-defined time period from the time tl3, at which the digital pulse signal 1516 transitions from the SO to the state Sl. The parameter 1512 transitions from the parameter level PR21C to the parameter level PR11C at approximately the same time, such as at the time t43 or within the pre-defined time period from the time t43, at which the digital pulse signal 1516 transitions from the Sl to the state SO. Moreover, the parameter 1512 transitions from the parameter level PR11C to the parameter level PR21C at approximately the same time, such as at the time t53 or within the pre-defined time period from the time t53, at which the digital pulse signal 1516 transitions from the SO to the state Sl. The parameter 1512 transitions from the parameter level PR21C to the parameter level PR11C at approximately the same time, such as at the time t83 or within the pre-defined time period from the time t83, at which the digital pulse signal 1516 transitions from the Sl to the state SO. Also, the parameter 1512 transitions from the parameter level PR11C to the parameter level PR21C at approximately the same time, such as at the time t93 or within the pre-defined time period from the time t93, at which the digital pulse signal 1516 transitions from the SO to the state Sl. The parameter 1512 transitions from the parameter level PR21C to the parameter level PR11C at approximately the same time, such as at the time tl23 or within the pre-defined time period from the time tl23, at which the digital pulse signal 1516 transitions from the Sl to the state SO.

[00365] It should be noted that the parameter 1512 is synchronized substantially with the parameter 312 of Figures 3 A through 3D. For example, the parameter 1512 has the parameter level of PR11C and the parameter 312 has the parameter level of PR11 during the time period between the times tl3 and 0, during the time period between the times t53 and t43, and during the time period between the times t93 and t83. As another example, the parameter 1512 transitions from the parameter level PR11C to the parameter level PR21C at approximately the same time, such as at the time tl3 or within the pre-defined time period from the time tl3 and at the time t53 or within the pre-defined time period from the time t53 or at the time t93 or within the pre-defined time period from the time t93, at which the parameter 312 transitions from the parameter level PR11 to the parameter level PR21.

[00366] As another example, the parameter 1512 has the parameter level of PR21C and the parameter 312 has the parameter level of PR21 during the time period between the times t23 and tl3, during the time period between the times t63 and t53, and during the time period between the times tl03 and t93. As another example, the parameter 1512 has the parameter level of PR21C and the parameter 312 has the parameter level of PR31 during the time period between the times t33 and t23, during the time period between the times t73 and t63, and during the time period between the times tll3 and tl03. As yet another example, the parameter 1512 has the parameter level of PR21C and the parameter 312 has the parameter level of PR41 during the time period between the times t43 and t33, during the time period between the times t83 and t73, and during the time period between the times tl23 and tll3. As yet another example, the parameter 1512 transitions from the parameter level PR21C to the parameter level PR11C at approximately the same time, such as at the time t43 or within the pre-defined time period from the time t43 and at the time t83 or within the pre-defined time period from the time t83 or at the time tl23 or within the pre-defined time period from the time tl23, at which the parameter 312 transitions from the parameter level PR41 to the parameter level PR11.

[00367] An example of the parameter level PR1C is xll% of the maximum amount of power that is supplied to the TCP coil 116 of figure 14 A. An example of xll% ranges from and including 0% to 50%. For example, xl l% is 10% of the maximum amount of power. Similarly, an example of the parameter level PR21C is y 11 % of the maximum amount of power that is supplied to the TCP coil 116. An example of y 11 % ranges from and including 80% to 100%. As another example, y 11 % is the maximum amount of power.

[00368] It should be noted that by pulsing the parameter 1512 at a low level during a time period in which the parameter of the RF signal 122 of figure 14A is pulsed at the low level, low energy ions of plasma within the plasma chamber 112 having a low angular spread are generated. An example of the low level of the parameter 1512 is the parameter level PR11C and of a high level of the parameter 1512 is the parameter level PR21C.

[00369] Figure 15C shows an embodiment of a graph 1522 and an embodiment of another graph 1518 to illustrate pulsing of a parameter 1520 of the RF signal 1406 generated by the RF generator RFGC of figure 14A. The graph 1518 plots the parameter 1520 versus the time t. The graph 1522 plots a digital pulse signal 1524 versus the time t. The digital pulse signal 1524 is an example of the digital pulse signal 1402 of figure 14A.

[00370] The digital pulse signal 1524 transitions periodically between occurrences of the states SO and Sl. For example, during the time period between the times zero and tl4, the digital pulse signal 1524 has the logic level of zero, which is an occurrence of the state SO. Moreover, during the time period between the times tl4 and t54, the digital pulse signal 1524 has the logic level of one, which is an occurrence of the state Sl. In addition, during the time period between the times t54 and t64, the digital pulse signal 1524 has the logic level of zero, which is another occurrence of the state SO. Also, during the time period between the times t64 and tl04, the digital pulse signal 1516 has the logic level of one, which is another occurrence of the state Sl.

[00371] As another example, at the time tl4, the digital pulse signal 1520 transitions from the logic level 0 to the logic level 1 and at the time t54, the digital pulse signal 1520 transitions from the logic level 1 to the logic level 0. Similarly, at the time t64, the digital pulse signal 1520 transitions from the logic level 0 to the logic level 1 and at the time tl04, the digital pulse signal 1520 transitions from the logic level 1 to the logic level 0.

[00372] The parameter 1520 is synchronized substantially with the digital pulse signal 1524. For example, during the state SO of the digital pulse signal 1524, the parameter 1520 has the parameter level PR111C and during the state Sl of the digital pulse signal 1524, the parameter 1520 has the parameter level PR211C. As another example, the parameter 1520 transitions from the parameter level PR111C to the parameter level PR211C at approximately the same time, such as at the time tl4 or within the pre-defined time period from the time tl4, at which the digital pulse signal 1524 transitions from the SO to the state Sl. The parameter 1520 transitions from the parameter level PR211C to the parameter level PR111C at approximately the same time, such as at the time t54 or within the pre-defined time period from the time t54, at which the digital pulse signal 1524 transitions from the Sl to the state SO. Moreover, the parameter 1520 transitions from the parameter level PR111C to the parameter level PR211C at approximately the same time, such as at the time t64 or within the pre-defined time period from the time t64, at which the digital pulse signal 1524 transitions from the SO to the state Sl. The parameter 1524 transitions from the parameter level PR211C to the parameter level PR111C at approximately the same time, such as at the time tl04 or within the pre-defined time period from the time tl04, at which the digital pulse signal 1524 transitions from the S 1 to the state SO.

[00373] It should be noted that the parameter 1520 is synchronized substantially with the parameter 412 of Figures 4A and 4B. For example, the parameter 1520 has the parameter level of PR111C and the parameter 412 has the parameter level of PR111 during the time period between the times tl4 and 0 and during the time period between the times t64 and t54. As another example, the parameter 1520 transitions from the parameter level PR111C to the parameter level PR211C at approximately the same time, such as at the time tl4 or within the pre-defined time period from the time tl4 and at the time t64 or within the pre-defined time period from the time t64 or, at which the parameter 412 transitions from the parameter level PR111 to the parameter level PR211.

[00374] As another example, the parameter 1520 has the parameter level of PR211C and the parameter 412 has the parameter level of PR211 during the time period between the times t24 and tl4 and during the time period between the times t74 and t64. As another example, the parameter 1520 has the parameter level of PR211C and the parameter 412 has the parameter level of PR311 during the time period between the times t34 and t24 and during the time period between the times t84 and t74. As yet another example, the parameter 1520 has the parameter level of PR211C and the parameter 412 has the parameter level of PR411 during the time period between the times t44 and t34 and during the time period between the times t94 and t84. As another example, the parameter 1520 has the parameter level of PR211C and the parameter 412 has the parameter level of PR511 during the time period between the times t54 and t44 and during the time period between the times tl04 and t94. As yet another example, the DC parameter 1520 transitions from the parameter level PR211C to the parameter level PR111C at approximately the same time, such as at the time t54 or within the pre-defined time period from the time t54 and at the time tl04 or within the pre-defined time period from the time tl04, at which the parameter 412 transitions from the parameter level PR511 to the parameter level PR111.

[00375] An example of the parameter level PR111C is xll l% of the maximum amount of power that is supplied to the TCP coil 116 of figure 14A. An example of xll l% ranges from and including 0% to 50%. For example, xl ll% is 5% of the maximum amount of power. Similarly, an example of the parameter level PR211C is yll l% of the maximum amount of power that is supplied to the TCP coil 116. An example of yl 11% ranges from and including 80% to 100%. As another example, y 111 % is the maximum amount of power.

[00376] It should be noted that by pulsing the parameter 1520 at a low level during a time period in which the parameter of the RF signal 122 of figure 14A is pulsed at the low level, low energy ions of plasma within the plasma chamber 112 having a low angular spread are generated. An example of the low level of the parameter 1520 is the parameter level PR111C and of a high level of the parameter 1520 is the parameter level PR211C.

[00377] Figure 16A is an embodiment of the graph 512. The graph 512 is described above.

[00378] Figure 16B is an embodiment of a graph 1604 to illustrate that the angular spread of ions of plasma within the plasma chamber 112 of figure 1 decreases when the five- level pulsing of the parameter and the two-level frequency pulsing of the RF signal 122 of figure 1 are applied to the substrate support 114 (figure 1). The graph 1604 includes a plot of energy of ions of plasma within the plasma chamber 112 of figure 1 versus the angular spread of the ions within the plasma chamber 112. It is noted that there is a decrease in the angular spread of ions when the five-level parameter pulsing and the two-level frequency pulsing of the RF signal 122 are applied compared to the angular distribution of ions within the plasma reactor when the continuous wave voltage signal of 300 volts is applied to the wafer support.

[00379] Figure 16C is an embodiment of a graph 1606 to illustrate that the angular spread of ions of plasma within the plasma chamber 112 of figure 12 decreases when the four-level pulsing of the parameter of the RF signal 122 of figure 1 and the two-level frequency pulsing of the RF signal 122 are applied to the substrate support 114 (figure 1), and the DC signal 1214 of figure 12 pulses between two DC parameter levels. The pulsing of the DC signal between the two DC parameter levels is sometimes referred to herein as two-level DC pulsing. An example of the two DC parameter levels includes the DC parameter level DC0 and the DC parameter level DC1 (figure 13A). Another example of the two DC parameter levels includes the DC parameter level DC01 and the DC parameter level DC 11 (figure 13B). Yet another example of the two DC parameter levels includes the DC parameter level DC001 and the DC parameter level DC111 (figure 13C).

[00380] The graph 1606 includes a plot of energy of ions of plasma within the plasma chamber 112 of figure 12 versus the angular spread of the ions within the plasma chamber 112. It is noted that there is a decrease in the angular spread of ions when the four- level parameter pulsing and the two-level frequency pulsing of the RF signal 122 are applied with the two-level DC pulsing compared to the angular distribution of ions within the plasma reactor when the continuous wave voltage signal of 300 volts is applied to the wafer support. In addition, there is a decrease in the peak energy of ions within the plasma chamber 112 when the four-level parameter pulsing and the two-level frequency pulsing of the RF signal 122 are applied with the two-level DC pulsing compared to the angular distribution of ions within the plasma reactor when the continuous wave voltage signal of 300 volts is applied to the wafer support.

[00381] Figure 16D is an embodiment of a graph 1608 to illustrate that the angular spread of ions of plasma within the plasma chamber 112 of figure 14 A decreases when the four-level pulsing of the parameter and the two-level frequency pulsing of the RF signal 122 of figure 1 are applied to the substrate support 114 (figure 1), and the RF signal 1406 of figure 14A pulses between two parameter levels. An example of the two parameter levels of the RF signal 1406 includes the parameter level PR1C and PR2C of Figure 15A. Another example of the two parameter levels of the RF signal 1406 includes the parameter levels PR11C and PR21C of Figure 15B. Yet another example of the two parameter levels of the RF signal 1406 includes the parameter levels PR111C and PR211C of Figure 15C. The graph 1608 includes a plot of energy of ions of plasma within the plasma chamber 112 of figure 14A versus the angular spread of the ions within the plasma chamber 112. It is noted that there is a decrease in the angular spread of ions when the five-level parameter pulsing and the two-level frequency pulsing of the RF signal 122 is applied with the two-level parameter pulsing of the RF signal 1406 compared to the angular distribution of ions within the plasma reactor when the continuous wave voltage signal of 300 volts is applied to the wafer support. In addition, there is a decrease in the peak energy of ions within the plasma chamber 112 when the five-level parameter pulsing and the two-level frequency pulsing of the RF signal 122 is applied with the two-level parameter pulsing of the RF signal 1406 compared to the angular distribution of ions within the plasma reactor when the continuous wave voltage signal of 300 volts is applied to the wafer support. [00382] It should be noted that when the DC signal 1214 is applied in addition to application of the multi-level frequency pulsing and the multi-level parameter pulsing of the RF signal 122, a DC positive voltage is applied during a time period in which a lowest parameter level, such as the parameter level PR1 (figure 2A) or PR11 (figure 3 A) or PR111 (figure 4A), is applied. Similarly, if the RF signal 1406 (figure 14A) is applied in addition to application of the multi-level frequency pulsing and the multi-level parameter pulsing, a small amount of TCP power is used during the time period in which the lowest parameter level is applied. For example, the small amount of TCP power is applied during the state SO of the digital pulse signal 1402 of figure 14A. The application of the DC signal 1214 decelerates high energy ions of plasma within the plasma chamber 112 as shown in Fig. 16(c). Similarly, the application of the small amount of TCP power decelerates the high energy ions of plasma within the plasma chamber 112 as shown in Fig. 16(d). The high energy ions that are decelerated maintain a relatively narrow angular spread compared to low energy ions of plasma within the plasma reactor. The low energy ions, as illustrated in figure 16 A, of plasma are generated within the plasma reactor by applying a continuous wave voltage signal. When the small amount of TCP power is applied, temperature of ions of plasma within the plasma chamber 112 cools down to provide increased directionality of the low energy ions to further increase an etch rate of etching the substrate 118 of figure 14 A.

[00383] During a transition from a low parameter level to a high parameter level in application of the multi-level frequency pulsing and the multi-level parameter pulsing, a high amount of electric field is created in plasma within the plasma chamber 112. As a result of the high amount of electric field, there is an increase in energy ions of plasma within the plasma chamber 112 and there is a decrease in an angular spread of the ions as illustrated in Figure 16B. For example, an application of the multiple voltage levels and multiple frequency levels increases an etch rate of etching the substrate 118 by approximately 60% and decreases the critical dimension of the substrate by about 7% as illustrated in Figure 16F. Moreover, when the DC voltage is applied in addition to the multiple voltage levels and multiple frequency levels, the high energy ions lose energy due to a decrease in an amount of an electric field of plasma within the plasma chamber 112. The loss of energy decelerates ions of plasma within the plasma chamber 112 and the ions do not scatter like they do in case of a negative potential sheath of plasma. As an example, the ions that loose the energy maintain an approximately 50% narrower low energy angular spread, as illustrated in figure 16C, compared to the low energy ions, illustrated in Figure 16A, produced by applying a continuous wave voltage signal. The application of the DC voltage produces a large population of the low energy ions with a relatively narrow angular spread at lower energies and the low energy ions enhance an etch rate of etching the substrate 118 by, for example, approximately 60% and reduces a critical dimension of the substrate 118, for example, by approximately 12%, compared to a continuous wave voltage signal, as is illustrated in Figure 16G.

[00384] Moreover, when the multi-level frequency pulsing and the multi-level parameter pulsing are applied in conjunction with pulsing of the TCP power, temperature of ions within the plasma chamber 112 reduces to preserve directionality of the ions as illustrated in Figure 16D. When the directionality of ions is preserved, an etch rate of etching the substrate 118 increases, for example, by about 50% compared to that achieved using a continuous wave voltage signal and the critical dimension of the substrate 118 decreases by about 16%, as illustrated in Figure 16H, compared to the critical dimension achieved using the continuous wave voltage signal.

[00385] Figure 16E is an embodiment of the graph 1102. The graph 1102 is described above.

[00386] Figure 16F is an embodiment of a graph 1604 that plots the vertical distance Z versus the horizontal distance R. The graph 1604 is generated when the five-level pulsing of the parameter and the two-level frequency pulsing of the RF signal 122 of figure 1 are applied to the substrate support 114 of figure 1. The graph 1604 plots the vertical distance of a mask layer 1604A of the substrate 118 of figure 1 and the vertical distance of a substrate layer 1604B of the substrate 118. Moreover, the graph 1604 plots the critical dimension of a channel formed within the mask layer 1604 A during an etch operation. In addition, the graph 1604 plots the critical dimension of the channel formed within the substrate layer 1604B.

[00387] Figure 16G is an embodiment of a graph 1606 that plots the vertical distance Z versus the horizontal distance R. The graph 1606 is generated when the four- level pulsing of the parameter and the two-level frequency pulsing of the RF signal 122 of figure 12 are applied to the substrate support 114 of figure 12 in conjunction with the two-level DC pulsing. The graph 1606 plots the vertical distance of a mask layer 1606 A of the substrate 118 of figure 12 and the vertical distance of a substrate layer 1606B of the substrate 118. Moreover, the graph 1606 plots the critical dimension of a channel formed within the mask layer 1606A during an etch operation. Also, the graph 1606 plots the critical dimension of the channel formed within the substrate layer 1606B.

[00388] Figure 16H is an embodiment of a graph 1608 that plots the vertical distance Z versus the horizontal distance R. The graph 1608 is generated when the five-level pulsing of the parameter and the two-level frequency pulsing of the RF signal 122 of figure 14A are applied to the substrate support 114 of figure 14A in conjunction with the two-level pulsing of the parameter of the RF signal 1406 of figure 14A. The graph 1608 plots the vertical distance of a mask layer 1608A of the substrate 118 of figure 14A and the vertical distance of a substrate layer 1608B of the substrate 118. Moreover, the graph 1608 plots the critical dimension of a channel formed within the mask layer 1608 A during an etch operation. Also, the graph 1608 plots the critical dimension of the channel formed within the substrate layer 1608B.

[00389] It should be noted that with an increase in a number of levels of pulsing of the parameter and the frequency of the RF signal 122, there is a decrease in the angular spread of ions within the plasma chamber 112. The decrease in the angular spread increases an etch rate of etching the substrate 118 to further decrease the critical dimension of the substrate 118 and to increase mask selectivity of the substrate 112. Moreover, it should further be noted that by pulsing the DC power supply 1204 of figure 12, there is a further decrease in the angular spread of ions within the plasma chamber 112 compared to the angular spread for the multi-level frequency and multi-level parameter pulsing of the RF signal 122. Again, with the further decrease in the angular spread, there is a decrease in the critical dimension of the substrate 118 and an increase in an etch rate of etching the substrate 118. In addition to the further decrease in the angular spread, there is a decrease in energy of ions of plasma within the plasma chamber 112 compared to the energy of ions for the multi level frequency and multi-level parameter pulsing of the RF signal 122.

[00390] It should also be noted that by pulsing the RF generator RFGC of figure 14A, there is a further decrease in the angular spread of ions within the plasma chamber 112 compared to the angular spread for the multi-level frequency and multi-level parameter pulsing of the RF signal 122. Again, with the further decrease in the angular spread, there is a decrease in energy of ions of plasma within the plasma chamber 112 compared to the energy of ions for the multi-level frequency and multi-level parameter pulsing of the RF signal 122. With the decrease in the energy of the ions of plasma within the plasma chamber 112, there is a reduction in a temperature of the ions. When the temperature of the ions decreases, the angular spread decreases according to the equation above and there is an increase in an etch rate of etching the substrate.

[00391] Figure 17A is an embodiment of the graph 1112. The graph 1112 is described above. Figure 17B is an embodiment of the graph 1114, which is described above. [00392] Figure 17C is an embodiment of a graph 1706 that plots the vertical distance of a mask layer 1706A of the substrate 118 of figure 1 versus the horizontal distance of the mask layer 1706A. The graph 1706 is generated when the five-level pulsing of the parameter and the two-level pulsing of the frequency of the RF signal 122 of figure 1 are applied to the substrate support 114 of figure 1. Moreover, the graph 1706 plots the critical dimension of the channel formed within the mask layer 1706 A during an etch operation. When the multi-level frequency pulsing and the multi-level parameter pulsing are applied, a mask layer of the substrate 118 is eroded by, for example, about 92%, compared to erosion of the mask layer when a continuous wave voltage signal is applied, as is illustrated by Figures 17B and 17C.

[00393] Figure 17D is an embodiment of a graph 1708 that plots the vertical distance of a mask layer 1708A of the substrate 118 of figure 1 versus the horizontal distance of the mask layer 1708A. The graph 1708 is generated when the four-level pulsing of the parameter and the two-level pulsing of the frequency of the RF signal 122 of figure 1 are applied to the substrate support 114 of figure 12 in addition to applying the two-level DC pulsing. Moreover, the graph 1708 plots the critical dimension of the channel formed within the mask layer 1708A during an etch operation.

[00394] In some embodiments, when the constant frequency level of the RF signal 146 of figures 1 and 12 is applied to the TCP coil 116, the parameter of the RF signal 144 is also at a constant parameter level. For example, the RF generator RFGB of figures 1 and 12 generates the RF signal 144 that has the constant parameter level. An example of the constant parameter level is a parameter level having magnitudes of the parameter that are not outside the preset range. To illustrate, a highest magnitude of the constant parameter level is at most 20% greater than a lowest magnitude of the constant parameter level.

[00395] Figure 17E is an embodiment of a graph 1710 that plots the vertical distance of a mask layer 1710A of the substrate 118 of figure 1 versus the horizontal distance of the mask layer 1710A. The graph 1710 is generated when the five-level pulsing of the parameter and the two-level pulsing of the frequency of the RF signal 122 of figure 1 are applied to the substrate support 114 of figure 12 in addition to applying the two-level parameter pulsing of the RF signal 1406 to the TCP coil 116 of figure 14A. Moreover, the graph 1710 plots the critical dimension of the channel formed within the mask layer 1710A during an etch operation.

[00396] It should be noted that for any of the graphs 1706-1710, there is less erosion of a mask layer of the substrate 118 compared to an amount of erosion of the mask layer 1102 A. If the DC signal 1214 of figure 12 is applied during a low voltage level of the multi-level parameter pulsing, a mask layer of the substrate 118 is eroded by approximately 85% compared to erosion of the mask layer when a continuous wave voltage signal is applied, as is illustrated by Figures 17B and 17D. Similarly, if the small amount of TCP power is applied during the low voltage level of the multi-level parameter pulsing, a mask layer of the substrate 118 is eroded, for example, by approximately 95%, compared to erosion of the mask layer when the continuous wave voltage signal is applied, as is illustrated by Figures 17B and 17E.

[00397] In some embodiments, each parameter level, described herein, of an RF signal, is an envelope of the RF signal. For example, a parameter level, described herein, of an RF signal is a zero-to-peak magnitude of the RF signal or a peak-to-peak magnitude of the RF signal.

[00398] Embodiments described herein may be practiced with various computer system configurations including hand-held hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers and the like. The embodiments can also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a network.

[00399] In some embodiments, a controller is part of a system, which may be part of the above-described examples. Such systems include semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and/or specific processing components (a wafer pedestal, a gas flow system, etc.). These systems are integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics is referred to as the“controller,” which may control various components or subparts of the system or systems. The controller, depending on the processing requirements and/or the type of system, is programmed to control any of the processes disclosed herein, including the delivery of process gases, temperature settings (e.g., heating and/or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and/or load locks coupled to or interfaced with a system.

[00400] Broadly speaking, in a variety of embodiments, the controller is defined as electronics having various integrated circuits, logic, memory, and/or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as ASICs, PLDs, and/or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). The program instructions are instructions communicated to the controller in the form of various individual settings (or program files), defining the parameters, the factors, the variables, etc., for carrying out a particular process on or for a semiconductor wafer or to a system. The program instructions are, in some embodiments, a part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or dies of a wafer.

[00401] The controller, in some embodiments, is a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller is in a“cloud” or all or a part of a fab host computer system, which allows for remote access of the wafer processing. The computer enables remote access to the system to monitor current progress of fabrication operations, examines a history of past fabrication operations, examines trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process.

[00402] In some embodiments, a remote computer (e.g. a server) provides process recipes to a system over a network, which includes a local network or the Internet. The remote computer includes a user interface that enables entry or programming of parameters and/or settings, which are then communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of data, which specify the parameters, factors, and/or variables for each of the processing steps to be performed during one or more operations. It should be understood that the parameters, factors, and/or variables are specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus as described above, the controller is distributed, such as by including one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes includes one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber. [00403] Without limitation, in various embodiments, example systems to which the methods are applied include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing systems that is associated or used in the fabrication and/or manufacturing of semiconductor wafers.

[00404] It is further noted that in some embodiments, the above-described operations apply to several types of plasma chambers, e.g., a plasma chamber including an inductively coupled plasma (ICP) reactor, a transformer coupled plasma chamber, conductor tools, dielectric tools, a plasma chamber including an electron cyclotron resonance (ECR) reactor, etc. For example, one or more RF generators are coupled to an inductor within the ICP reactor. Examples of a shape of the inductor include a solenoid, a dome-shaped coil, a flat-shaped coil, etc.

[00405] As noted above, depending on the process step or steps to be performed by the tool, the host computer communicates with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and/or load ports in a semiconductor manufacturing factory.

[00406] With the above embodiments in mind, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored in computer systems. These operations are those physically manipulating physical quantities. Any of the operations described herein that form part of the embodiments are useful machine operations.

[00407] Some of the embodiments also relate to a hardware unit or an apparatus for performing these operations. The apparatus is specially constructed for a special purpose computer. When defined as a special purpose computer, the computer performs other processing, program execution or routines that are not part of the special purpose, while still being capable of operating for the special purpose.

[00408] In some embodiments, the operations may be processed by a computer selectively activated or configured by one or more computer programs stored in a computer memory, cache, or obtained over the computer network. When data is obtained over the computer network, the data may be processed by other computers on the computer network, e.g., a cloud of computing resources.

[00409] One or more embodiments can also be fabricated as computer-readable code on a non-transitory computer-readable medium. The non-transitory computer-readable medium is any data storage hardware unit, e.g., a memory device, etc., that stores data, which is thereafter be read by a computer system. Examples of the non-transitory computer- readable medium include hard drives, network attached storage (NAS), ROM, RAM, compact disc-ROMs (CD-ROMs), CD-recordables (CD-Rs), CD-rewri tables (CD-RWs), magnetic tapes and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer-readable medium includes a computer-readable tangible medium distributed over a network-coupled computer system so that the computer- readable code is stored and executed in a distributed fashion.

[00410] Although the method operations above were described in a specific order, it should be understood that in various embodiments, other housekeeping operations are performed in between operations, or the method operations are adjusted so that they occur at slightly different times, or are distributed in a system which allows the occurrence of the method operations at various intervals, or are performed in a different order than that described above.

[00411] It should further be noted that in an embodiment, one or more features from any embodiment described above are combined with one or more features of any other embodiment without departing from a scope described in various embodiments described in the present disclosure.

[00412] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.