BACKGROUND

[0001] Majority of the electronic computation today is carried out in Boolean logic in digital computers and electronics. Boolean logic is a form of algebra in which all values are reduced to either TRUE (1) or FALSE (0). Boolean logic gates have scaled following the Moore's law as gate lengths have scaled (e.g., to 20 nm). Some limitations to Boolean logic are: limited density of logic gates limited by algebraic constrains in two level logic (Galois field-2 algebra); limited density of interconnect bandwidth limited by the number representation in base 2 number system; and limited density of memory states limited by the information content per bit.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0003] Fig. 1 illustrates a plot showing magnetic crystalline energy of a four state magnet and corresponding 4-state magnet used for forming a 4-state spin logic device, in accordance with some embodiments of the disclosure.

[0004] Fig. 2 illustrates a spin logic device with stacking of a 4-State magnet above a spin channel and with matched spacer, in accordance with some embodiments of the disclosure.

[0005] Fig. 3 illustrates a spin logic device with stacking of a 4-State magnet above a spin channel, with matched spacer leaving recessed metal region, in accordance with some embodiments of the disclosure.

[0006] Fig. 4 illustrates a spin logic device with stacking of a 4-State magnet including a filtering layer above a spin channel and with matched spacer, in accordance with some embodiments of the disclosure.

[0007] Fig. 5 illustrates a spin logic device with stacking of a 4-State magnet including a filtering layer above a spin channel and with matched spacer, in accordance with some embodiments of the disclosure. [0008] Figs. 6A-B illustrate proposed stacks for spin logic devices showing atomic templating of Heusler alloys for generating atomistic crystalline matched layers, according to some embodiments of the disclosure.

[0009] Fig. 7 illustrates a 4-state non-inverting spin gate or buffer injecting spins in the

+x direction and receiving spins in the -x direction, in accordance with some embodiments of the disclosure.

[0010] Fig. 8 illustrates a 4-state non-inverting spin gate or buffer injecting spins in the

+y direction and receiving spins in the +y direction, in accordance with some embodiments of the disclosure.

[0011] Fig. 9 illustrates a 4-state inverting spin gate injecting spins in the -x direction and receiving spins in the +x direction, in accordance with some embodiments of the disclosure.

[0012] Fig. 10 illustrates a 4-state inverting spin gate injecting spins in the -y direction and receiving spins in the -y direction, in accordance with some embodiments of the disclosure.

[0013] Fig. 11 illustrates a flowchart of a method for fabricating a spin logic device with

4-state magnets, according to some embodiments of the disclosure.

[0014] Fig. 12 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with a spin logic device with 4-state magnets, according to some embodiments of the disclosure.

DETAILED DESCRIPTION

[0015] Various embodiments describe a 4-state logic memory element which has four uniquely defined logic states. In some embodiments, the four states are separated by high energy barrier (e.g., 40kT or 60kT) to provide low error rate operation. In some embodiments, a metal interconnect is provided which can conduct four uniquely defined interconnect states. In some embodiments, a quaternary logic gate is described which comprises two quaternary magnetic elements sharing a spin channel. In some embodiments, the quaternary logic gate is operable to function as a buffer or non-inverting gate that can buffer or invert spin current in two different orientations (e.g., +/- x and +/- y orientations). In some embodiments, the quaternary logic gate is operable to function as an inverter that can invert an input spin current. This input spin current can be in +/- x or +/- y orientations. [0016] In some embodiments, four orientations (0, 1 , 2, and 3) are defined for the 4-state logic memory element such that orientations '0' and ' 1 ' are separated by 90 degrees, orientations ' 1 ' and '3' are separated by 90 degrees, orientations '3' and '2' are separated by 90 degrees, orientations '0' and '3' are separated by 180 degrees, and orientations T and '2' are separated by 180 degrees. In some embodiments, with reference to a four quadrant two dimensional (2D) vector space, magnetic orientation facing +x direction (e.g., East) is orientation Ό'; magnetic orientation facing +y direction (e.g., North) is orientation ' 1 ', magnetic orientation facing -x direction (e.g., West) is orientation '3', and magnetic orientation facing -y direction (e.g., South) is orientation '2'.

[0017] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0018] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0019] Throughout the specification, and in the claims, the term "connected" means a direct physical, electrical, or wireless connection between the things that are connected, without any intermediary devices. The term "coupled" means either a direct electrical or wireless connection between the things that are connected or an indirect electrical or wireless connection through one or more passive or active intermediary devices. The term "circuit" means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" means at least one current signal, voltage signal, magnetic signal, electromagnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0020] The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 10% of a target value (unless specifically specified). Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0021] Unless otherwise specified the use of the ordinal adjectives "first," "second," and

"third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0022] For the purposes of the present disclosure, phrases "A and/or B" and "A or B" mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). The terms "left," "right," "front," "back," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.

[0023] Fig. 1 illustrates plot 101 showing magnetic crystalline energy of a four state magnet and corresponding 4-state magnet used for forming a 4-state spin logic device, in accordance with some embodiments of the disclosure. Here, the x-axis is angle in degrees, and the y-axis is Energy in kT (where 'k' is Boltzmann constant and 'T' is temperature). Plot 101 illustrates two waveforms— 102 and 103. Waveform 102 illustrates the thermal energy separation or barrier between four magnetic orientations of 4-state magnet 104. In some embodiments, 4-state magnet 104 is formed of a material such that the four magnetic orientations are separated by 40kT of thermal energy barrier as illustrated by waveform 102. Waveform 103 is similar to waveform 102 except the thermal energy separation between the four magnetic orientations is 60kT.

[0024] In some embodiments, the four orientations are defined for the 4-state logic memory element such that orientations '0' and ' Γ are separated by 90 degrees, orientations ' 1 ' and '3' are separated by 90 degrees, orientations '3' and '2' are separated by 90 degrees, orientations Ό' and '3' are separated by 180 degrees, and orientations T and '2' are separated by 180 degrees. In some embodiments, with reference to a four quadrant 2D vector space, magnetic orientation facing +x direction (e.g., East) is orientation 'Ο'; magnetic orientation facing +y direction (e.g., North) is orientation ' Γ, magnetic orientation facing -x direction (e.g., West) is orientation '3', and magnetic orientation facing -y direction (e.g., South) is orientation '2'.

[0025] In some embodiments, 4-state magnet 104 is formed using cubic magnetic crystalline anisotropy magnets. In some embodiments, 4-state magnet 104 is formed by combining shape and exchange coupling to create two equal easy axes for nanomagnets. In some embodiments, 4-state magnet 104 is formed of a material selected from a group consisting of: Fe, Ni, Co and their alloys, magnetic insulators, and Heusler alloys of the form X ₂ YZ. In some embodiments, the magnetic insulators are formed of a material selected from a group consisting of: magnetite FesO, and Y3AI5O12. In some embodiments, the Heusler alloys is one of: Co ₂ FeSi and Mn ₂ Ga.

[0026] In some embodiments, 4-state magnet 104 is formed with high spin polarization materials. Heusler alloys are an example of high spin polarization materials. Heusler alloys are ferromagnetic metal alloys based on Heusler phase. Heusler phases are intermetallics with particular composition and face-centered cubic crystal structure. Heusler alloys are

ferromagnetic because of double-exchange mechanism between neighboring magnetic ions. The neighboring magnetic ions are usually manganese ions, which sit at the body centers of the cubic structure and carry most of the magnetic moment of the alloy.

[0027] In some embodiments, 4-state magnet 104 is formed with a sufficiently high anisotropy (Hk) and sufficiently low magnetic saturation (M _s ) to increase injection of spin currents. For example, Heusler alloys of high Hk and low Ms are used to form 4-state magnet 104.

[0028] Magnetic saturation M _s is generally the state reached when an increase in applied external magnetic field H cannot increase the magnetization of the material (i.e., total magnetic flux density B substantially levels off). Here, sufficiently low Ms refers to Ms less than 200 kA/m (kilo-Amperes per meter). Anisotropy Hk generally refers to the material property which is directionally dependent. Materials with Hk are materials with material properties that are highly directionally dependent. Here, sufficiently high Hk in context of Heusler alloys is considered to be greater than 2000 Oe (Oersted). For example, a half metal that does not have bandgap in spin up states but does have bandgap in spin down states (e.g., at the energies within the bandgap, the material has 100% spin up electrons). If the Fermi level of the material is in the bandgap, injected electrons will be close to 100% spin polarized. In this context, "spin up" generally refers to the positive direction of magnetization, and "spin down" generally refers to the negative direction of magnetization. Variations of the magnetization direction (e.g. due to thermal fluctuations) result in mixing of spin polarizations.

[0029] In some embodiments, Heusler alloys such as Co ₂ FeAl and Co ₂ FeGeGa are used for forming 4-state magnet 104. Other examples of Heusler alloys include: Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb, Ni ₂ MnGa, Co ₂ MnAl, Co ₂ MnSi, Co ₂ MnGa, Co ₂ MnGe, Pd ₂ MnAl, Pd ₂ MnIn, Pd ₂ MnSn, Pd ₂ MnSb, Co ₂ FeSi, Fe ₂ Val, Mn ₂ VGa, Co ₂ FeGe, etc.

[0030] Fig. 2 illustrates cross-section 200 of spin logic device with stacking of a 4-State magnet above or below a spin channel and with matched spacer, in accordance with some embodiments of the disclosure. Fig. 2 also illustrates top view 220 of the spin logic device. It is pointed out that those elements of Fig. 2 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Here, cross-section 200 of spin logic device is also referred to as spin logic device 200 or device 200.

[0031] In some embodiments, device 200 comprises a first metal layer 201a, First 4-State

Magnet 203a, Second 4-State Magnet 203b, Oxide 205a between First and Second 4-State Magnets 203a/b, Spin Channel 206 a/b/c, Oxide layer 205b over Spin Channel 206a/b/c, Via 207, and second metal layer 201 b. Here, Power and Ground metal layers 201a and 201 b, respectively, may be collectively referred to as metal layers 201 ; First and Second 4-State Magnets 203a and 203b, respectively, may be collectively referred to as 4-State Magnets 203; Oxide layers 205a and 205b may be collectively referred to as oxide 205; and Spin Channel 206a/b/c may be collectively referred to as Spin Channel 206.

[0032] In some embodiments, the material(s) used for forming metal layers 201 , Via 207, and Spin Channel 206 is/are the same. For example, Copper (Cu) can be used for forming metal layers 201 , Via 207, and Spin Channel 206. In other embodiments, material(s) used for forming metal layers 201 , Via 207, and Spin Channel 206 are different. For example, metal layers 201 may be formed of Cu while Via 207 may be formed of Tungsten (W). Any suitable metal or combination of metals can be used for forming metal layers 201 , Via 207, and Spin Channel 206. For example, Spin Channel 206 can be formed of Silver (Ag), Aluminum (Al), Graphene, and other 2D conducting materials.

[0033] In some embodiments, First and Second 4-State Magnets 203a/b are formed using cubic magnetic crystalline anisotropy magnets. In some embodiments, First and Second 4-State Magnets 203a/b are formed by combining shape and exchange coupling to create two equal easy axes for a nanomagnets. First and Second 4-State Magnets 203a/b may be formed of the same materials as described with reference to 4-State magnet 104.

[0034] In some embodiments, Spin Channel 206 is partitioned into segments or regions

206a, 206b, and 206c such that Oxide 205b forms a barrier between the channel segments. One purpose of the barrier is to control the transfer of spin to charge. In some embodiments, the gap between First and Second Magnets 203a/b, provided by Oxide 205b, is chosen to be sufficient to permit isolation of the two magnets 203a/b. In some embodiments, a layer of oxide 205b is deposited before the Spin Channel 206 and then a via hole is etched for Via 207. In some embodiments, Via 207 couples Channel segment 206b to Ground supply layer 201 b which is formed over Oxide layer 205b.

[0035] In some embodiments, spin device 200 of Fig. 2 is inverted. For example, magnetic contacts 203 of device 200 are placed below Spin Channel 206. As such, magnetic contacts 203 are closer to the bottom than the top as opposed to placing the magnets of device closer to the top than the bottom. Top view 220 shows the top view of the cross-section XX of cross-section 200, in accordance with some embodiments. Here, the four orientations of the four states of First and Second 4-State Magnets 203a/b are shown. In some embodiments, First and Second 4-State Magnets 203a/b are cube (or square) shaped. As such, each magnetic state of First and Second 4-State Magnets 203a/b is separated by the same barrier energy (e.g., 40kT).

[0036] In some embodiments, First 4-State Magnet 203a dictates the flow of the spin current in channel 206b. This is realized by the asymmetry of First 4-State Magnet 203a overlap with channel 206b. Here, First 4-State Magnet 203a overlaps more with channel 206b than Second 4-State Magnet 203b. This asymmetry in the overlap sets the direction of spin through channel 206b, in accordance with some embodiments.

[0037] Fig. 3 illustrates spin logic device 300 (or cross-section 300) with stacking of a 4-

State magnet above or below a spin channel, with matched spacer leaving recessed metal region, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Fig. 3 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. So as not to obscure the embodiments, differences between spin logic devices of Fig. 3 and Fig. 2 are described.

[0038] In some embodiments, spin logic device 300 comprises first filter layer 301a and second filter layer 301 b. In some embodiments, first filter layer 301 a is formed between First 4- State Magnet 203a and the portions of channel regions (or segments) 206a and 206b. As such, unlike First 4-State Magnet 203a being directly coupled or adjacent to the portions of channel regions (or segments) 206a and 206b as described with reference to Fig. 2, here First 4-State Magnet 203a is coupled or adjacent to first filter layer 301 a. In some embodiments, second filter layer 301 b is formed between Second 4-State Magnet 203b and the portions of channel regions (or segments) 206c and 206b. As such, unlike Second 4-State Magnet 203a being directly coupled or adjacent to the portions of channel regions (or segments) 206a and 206b, here Second 4-State Magnet 203b is coupled or adjacent to second filter layer 301 b.

[0039] In some embodiments, first and second filter layers 301a/b are formed of a material selected from a group consisting of: MgO, AI2O3, BN, MgAl ₂ 0 ₄ , ZnAb0 ₄ , SiMg204, and SiZn ₂ 0 ₄ , and NiFeO. One purpose of the filter layers is to provide high tunneling magnetoresistance.

[0040] In some embodiments, First 4-State magnet 203a and the first filter layer 301 a overlap the spin channel region 206b more than Second 4-state magnet 203b and second filter layer 301 b overlap the second spin channel region. This asymmetry in the overlap sets the direction of spin through channel 206b, in accordance with some embodiments.

[0041] Fig. 4 illustrates spin logic device 400 with stacking of a 4-State magnet including a filtering layer above or below a spin channel and with matched spacer, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Fig. 4 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0042] Fig. 4 is similar to Fig. 2 except that Oxide barriers 205b are not complete barriers between segments of Spin Channel 206. As such, Spin Channel 401 has sections of metal above Oxide barriers 205b for coupling the channel segments. One reason for having recessed metal region under Oxide barriers 205b is to control the rate of exchange of spin between channel segments. In some embodiments, the height or thickness of the recessed metal region controls the rate of exchange of spin. For example, the thicker the recessed metal region (i.e., lesser the metal recession) the higher the rate of exchange of spin. The embodiment of Fig. 4 provides an alternative way of connecting spin devices. In some embodiments, spin logic devices 200/300/400 are integrated to form majority gate spin logic devices.

[0043] Fig. 5 illustrates spin logic device 500 with stacking of a 4-State magnet including engineered interfaces coupled to the spin channel, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Fig. 5 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0044] In some embodiments, engineered interfaces (i.e., first and second interfaces

504a/b and 502, respectively) are formed between the magnets (i.e., First and Second 4-State Magnets 203a/b) and metal layers (e.g., Ground 201 b and Spin Channel 206a). In some embodiments, the dimensions (width, length, and height/thickness) of Ground 201 b is chosen to optimize (e.g., reduce) the energy-delay of spin device 200. In some embodiments, first and second interfaces 504a/b and 502, respectively, are formed of non-magnetic material(s) such that the interface layers and the magnets together have sufficiently matched atomistic crystalline layers. For example, the non-magnetic material has a crystal periodicity which is matched through rotation or by mixing of elements.

[0045] Here, sufficiently matched atomistic crystalline layers refer to matching of the lattice constant 'a' within a threshold level above which atoms exhibit dislocation which is harmful to the device (i.e., the number and character of dislocations lead to a significant (e.g., greater than 10%) probability of spin flip while an electron traverses the interface layer). For example, the threshold level is within 5% (i.e., threshold levels in the range of 0% to 5% of the relative difference of the lattice constants). As the matching improves (e.g., matching gets closer to perfect matching), spin injection efficiency from spin transfer from 4-State magnets 203 to Spin Channel 206 increases. Poor matching (e.g., matching worse than 5%) implies dislocation of atoms that is harmful for the device. In some embodiments, the non-magnetic material is Ag with a crystal lattice constant a=4.05A which is matched to Heusler alloys CFA (i.e., Co ₂ FeAl) and CFGG (i.e., Co ₂ FeGeGa with a=5.737A) provided the direction of the crystal axes is turned by 45 degrees. Then the projection of the lattice constant is expressed as:

e/V2 » 5.737_4/1.414 * 4.057_4

As such, the magnetic structure stack (e.g., stack of 203a and 504a) allows for interfacial matching of Heusler alloys interfaces with the spin channel. In some embodiments, the stack also allows for templating of the bottom surface of the Heusler alloy.

[0046] In some embodiments, interface layer 502 (e.g., Ag) provides electrical contact to magnets 203. As such, a template is provided with the right crystal orientation to seed the formation of the Heusler alloy (which forms 4-State magnets 203). In some embodiments, the directionality of spin logic may be set by the geometric asymmetry in spin device 200. In some embodiments, the area of overlap of First 4-State magnet 203a (e.g., the input magnet) with Spin Channel 206b is larger than the area of overlap of Second 4-State magnet 203b (e.g., the output magnet) causing asymmetric spin in channel 206b.

[0047] One technical effect of the engineered interface layers 504a/b (e.g., Ag) between

Heusler alloy based magnets 203a/b and Spin Channel 206 is that it provides for higher mechanical barrier to stop or inhibit the inter-diffusion of magnetic species with Spin Channel 206. In some embodiments, the engineered interface layers 504a/b maintain high spin injection at the interface between Spin Channel 206 and magnets 203. As such, engineered interface layers 504a/b improve the performance of spin device 200.

[0048] In some embodiments, the fabrication of Heusler alloy and the matching layer is via the use of an in situ processing flow. Here, in situ processing flow refers to a fabricating processing flow that does not break vacuum. As such, oxidation on interface 504 are avoided resulting in smooth surfaces at interface 504.

[0049] In some embodiments, First 4-State magnet 203a and the first interface layer 504a overlap the spin channel region 206b more than Second 4-state magnet 203b and second interface layer 504b overlap the second spin channel region. This asymmetry in the overlap sets the direction of spin through channel 206b, in accordance with some embodiments.

[0050] Figs. 6A-B illustrate proposed stacks 600 and 620, respectively, for spin logic devices showing atomic templating of Heusler alloys for generating atomistic crystalline matched layers, according to some embodiments of the disclosure. It is pointed out that those elements of Figs. 6A-B having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0051] Stacks 600 and 620 illustrate a naturally templated magnet using the magnetic structure of some embodiments. A characteristic of templated stacks is that the crystalline growth of a layer is not adversely affected by the crystal symmetry of the underlying layer. Stacks 600 and 620 are a stack of interface layer 502 (e.g., Ag), magnet layer 203a/b, and interface layer 504a/b (e.g., Ag). Stack 600 shows matching of Ag with Co ₂ FeAl while stack 620 shows matching of Ag with Co ₂ FeGeGa. Here, there is a 2% difference in crystal periodicity which makes the interface between Ag with Co2FeAl, and Ag with Co ₂ FeGeGa, well matched (e.g., Ag has a crystal periodicity which is matched well with the magnet through in- plane rotation).

[0052] In some embodiments, the direction of the injected spins is reverse of the magnet polarity for inverter. The direction of spins in the channel below the two magnets can be the same. For inverter, the spins under the injection magnet is opposite of the injector while for a buffer, the direction is identical, in accordance with some embodiments.

[0053] Fig. 7 illustrates a 4-state non-inverting spin gate or buffer 700 injecting spins in

+x direction and receiving spins in +x direction, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Fig. 7 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0054] In some embodiments, the spin injection from the 4-State magnets is setup to produce a spin population in the spin interconnect such that a spin current is generated that flows along the channel. Here, spin current in the +x direction is in channel region 206a under the First 4-State Magnet 203a. This spin current is also referred to as the injected spin current (e.g., injected in channel region 206a). The dominant spin current is shown by spin direction 701 in the +x direction while some minority spin 702 in channel 206a points in the -x direction.

[0055] In some embodiments, when a negative voltage (e.g., -Vdd) is applied to metal layer 201 a and ground is applied to metal layer 201 b, then device 200 behaves as a buffer. In this case, if the magnetic orientation of First 4-State Magnet 203a (i.e., the input magnet) is in +x direction (i.e., M=+x), it causes the majority of spins to traverse through channel 206b towards Second 4-State Magnet 203b (i.e., the output magnet). The spins (majority and minority) in channel region 206b are shown by the arrows channel 206b. The magnetic orientation of Second 4-State Magnet 203b is switched to the +x direction (i.e., M=+x) due to spin torque from the received spin current 703 in the +x direction. Spin current 703 is the spin current in channel region 206c under Second 4-State Magnet 206b. As such, the 4-state magnets allow the injected +x direction spin current 701 to be received as spin current 703 in the same direction (i.e., +x direction) at the receiving channel 206c.

[0056] In some embodiments, the input magnet 203a dictates the flow of the spin current in channel 206b. This is realized by the asymmetry of First 4-State Magnet 203a overlap with channel 206c. Here, First 4-State Magnet 203a overlaps more with channel 206b than Second 4- State Magnet 203b. In some embodiments, when -Vdd voltage is applied to metal layer 201 a, the direction of the spin current in channel 206b is the same as the direction of the spins of First 4-State Magnet 203a. As such, a flow of spin current from First 4-State Magnet 203a to Second 4-State Magnet 203b occurs comprising of spins with the polarity of First 4-State Magnet 203a. For the buffer (or non-inverting gate of Fig. 7), the spins under the input magnet 203a is identical to the spins under the output magnet 203b, in accordance with some embodiments.

[0057] Fig. 8 illustrates a 4-state non-inverting spin gate or buffer 800 injecting spins in

+y direction and receiving spins in +y direction, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Fig. 8 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0058] Here, spin current in the +y direction is in channel region 206a under the First 4-

State Magnet 203a. This spin current is also referred to as the injected spin current (e.g., injected in channel region 206a). The dominant spin current is shown by spin direction 801 in the +y direction while minority spin 802 in channel 206a points in the -y direction.

[0059] In some embodiments, when a negative voltage (e.g., -Vdd) is applied to metal layer 201 a and ground is applied to metal layer 201b, then device 200 behaves as a buffer. In this case, the magnetic orientation of First 4-State Magnet 203a (i.e., input magnet) in +y direction (i.e., M=+y pointing out of the figure) influences the majority of spins in +y direction to traverse through channel 206b towards Second 4-State Magnet 203a (i.e., the output magnet). The magnetic orientation of Second 4-State Magnet 203b is switched to the +y direction (i.e., M=+y pointing out of the figure) due to spin torque produced by the received spin current 803 in the +y direction. As such, the 4-state magnets allow the injected +y direction spin current 801 to be received in the same direction (i.e., +y direction) at the receiving channel 206c.

[0060] In some embodiments, the input magnet 203a dictates the flow of the spin current in channel 206b. This is realized by the asymmetry of First 4-State Magnet 203a overlap with channel 206c. Here, First 4-State Magnet 203a overlaps more with channel 206b than Second 4- State Magnet 203b. In some embodiments, when -Vdd voltage is applied to metal layer 201 a, the direction of the spin current in channel 206b is the same as the direction of the spins of First 4-State Magnet 203a. As such, a flow of spin current from First 4-State Magnet 203a to Second 4-State Magnet 203b occurs comprising of spins with polarity of First 4-State Magnet 203a. In this example, the prevalence of majority spin current relative to minority spin current decreases along the channel (i.e., decreases from channel region 206a to channel region 206c). For the buffer (or non-inverting gate of Fig. 8), the spins under the input magnet 203a is identical to the spins under the output magnet 203b, in accordance with some embodiments.

[0061] Fig. 9 illustrates a 4-state inverting spin gate 900 injecting spins in -x direction and receiving spins in -x direction, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Fig. 9 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0062] Here, spin current in the -x direction is injected in channel region 206a. Note, here input magnet 203a is magnetized +x (i.e., M=+x), the spin under input magnet 203a is in the -x direction, and the spin under channel region 206b is in the -x direction. The dominant spin current is shown by spin direction 901 in the -x direction while some minority spin 902 in channel 206a points in the +x direction. The propagation of the spin current through device 900 depends on the magnetization of First and Second 4-State Magnets 203a/b. The spin current received in channel region 206c is in the -x direction. The prevalence of majority spin current relative to minority spin current decreases along the channel (i.e., decreases from channel region 206a to channel region 206c).

[0063] In some embodiments, when a positive voltage (e.g., +Vdd) is applied to metal layer 201 a and ground is applied to metal layer 201 b, then device 900 behaves as an inverter. In this case, the magnetic orientation of First 4-State Magnet 203a (i.e., the input magnet) is in +x direction causing the majority of spins to traverse through channel 206b towards Second 4-State Magnet 203a (i.e., the output magnet). In some embodiments, the input magnet (203a) dictates the flow of the spin current in channel 206b. This is realized by the asymmetry of the magnet overlap with the channel. For example, First 4-State Magnet 203a overlaps more with channel 206b than Second 4-State Magnet 203a.

[0064] In some embodiments, a flow of spin current from First 4-State Magnet 203a to

Second 4-State Magnet 203b occurs comprising of spins with opposite polarity of First 4-State Magnet 203a (e.g., the ratio of majority spin current relative to minority spin current decreases along the channel from channel region 206a to channel region 206c). In some embodiments, for an inverter, the direction of the injected spins is reverse of the magnet polarity for inverter. For example, the direction of majority spins 901 is in the -x direction while the direction of magnetization of Second Magnet 203b is in the +x direction. In some embodiments, the direction of spins in channel region 206b below the two magnets can be the same for an inverter.

[0065] Fig. 10 illustrates a 4-state inverting spin gate 1000 injecting spins in -y (input magnet 203a is magnetized with +y (i.e., M=+y), spin under input magnet 203a and in channel region 206b is -y) direction and receiving spins in -y direction, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Fig. 10 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0066] Here, spin current in the -y direction is injected in channel region 206a. The dominant spin current is shown by spin direction 1001 in the -y direction while some minority spin 1002 in channel 206a points in the +y direction. The propagation of the spin current through device 1000 depends on the magnetization of First and Second 4-State Magnets 203a/b.

[0067] In some embodiments, when a positive voltage (e.g., +Vdd) is applied to metal layer 201 a and ground is applied to metal layer 201b, then device 1000 behaves as an inverter. In this case, the magnetic orientation of First 4-State Magnet 203a (i.e., input magnet) is in +y direction (i.e., M=+y) causing the majority of spins to traverse through channel 206b towards Second 4-State Magnet 203b (i.e., output magnet). In some embodiments, the input magnet 203a dictates the flow of the spin current in channel 206b. This is realized by the asymmetry of the magnet overlap with the channel. For example, First 4-State Magnet 203a overlaps more with channel 206b than Second 4-State Magnet 203b. [0068] In some embodiments, flow of spin current from First 4-State Magnet 203a to

Second 4-State Magnet 203b occurs comprising of spins with opposite polarity of First 4-State Magnet 203a. In some embodiments, for an inverter, the direction of the injected spins is reverse of the magnet polarity for inverter. For example, the direction of majority spins in channel region 206c is in the -y direction while the direction of magnetization of First Magnet 203a is in the +y direction. In some embodiments, the direction of spins in channel region 206b below the two magnets can be the same for an inverter.

[0069] The 4-state inverter operation can be described with reference to Table 1. In

Table 1, the power supply to metal layer 201 a is a positive supply +Vdd.

Table 1

[0070] The 4-state buffer operation can be described with reference to Table 2. In Table

2, the power supply to metal layer 201 a is a negative supply -Vdd.

Table 2

[0071] Fig. 11A illustrates spin logic device 1 100 with 4-state magnet, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 11A having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Spin logic device 1 100 is similar to spin logic device 500 except that an interface templating layer 522 (e.g., Ag) is deposited over metal layer 201 a.

[0072] Fig. 11B illustrates flowchart 1 120 of a method for fabricating a spin logic device with 4-state magnet (e.g., a non-exact upside down version of spin logic device 200 which is illustrated as spin logic device 1 120), according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 11B having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0073] Although the blocks in the flowchart with reference to Fig. 11B are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions/blocks may be performed in parallel. Some of the blocks and/or operations listed in Fig. 11B are optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur.

Additionally, operations from the various flows may be utilized in a variety of combinations.

[0074] At block 1 121 , first metal layer 201a is deposited. In some embodiments, first metal layer 201 a is coupled to supply (either Vdd or -Vdd). At block 1 122, a first interface layer 522 is deposited over first metal layer 201 a. In some embodiments, first interface layer 522 is formed of a non-magnetic material (e.g., Ag). At block 1 123, a 4-State magnet layer 203 (e.g., before being etched to form input and output magnets 203a/b) is deposited over first interface layer 522. In some embodiments, 4-State magnet layer 203 is formed of a material with a sufficiently high anisotropy and sufficiently low magnetic saturation to increase injection of spin currents.

[0075] At block 1 124, a second interface layer 504 (before being etched to form first and second interface layers 504a/b) is deposited over 4-State magnet layer 203 such that 4-State magnet layer 203 is sandwiched between the first and second interface layers. In some embodiments, the first and second interface layers 522 and 504, respectively, are formed of nonmagnetic material such that the interface layers and magnet layers 203 together have sufficiently matched atomistic crystalline layers.

[0076] In some embodiments, the processes of blocks 1 121 , 1 122, 1 123, and 1 124 are perform in situ (i.e., the fabrication processes do not break vacuum). As such oxidization between interfaces of the layers 201 , 522, 203, and 504 is avoided (i.e., smooth interface surfaces are achieved). Smooth interface surfaces of the layers 201 , 522, 203, and 504 allow for higher spin injection efficiency, according to some embodiments.

[0077] In some embodiments, 4-State magnet layer 203 is patterned to form First and

Second 4-State Magnets 203a and 203b. This process breaks vacuum. For example, a photoresist material is deposited over second interface layer 504 and then etched for forming a patterned photo-resist layer, where the pattern indicates future locations of First and Second 4- State Magnets 203a/b. At block 1 125, second interface layer 204 and 4-State magnet layer 203 are selectively etched using the patterned photo-resist to form first and second portions 204a/b of second interface layer 204. As such, First and Second 4-State Magnets 203a/b are also formed. The photo-resist material is then removed.

[0078] At block 1 126, Spin Channel 206 (e.g., metal layer) is deposited over first and second portions 204a/b of second interface layer 504. In some embodiments, Spin Channel 206 is patterned into segments 206a/b/c by photo-resist deposition and patterning of the photo-resist material. At block 1 127, portions of Spin Channel 206 are etched to form segments of Spin Channel 206/a/b/c. In some embodiments, the depth of etching of Spin Channel 206 is adjusted as discussed with reference to Fig. 4. At block 1 128, portions of Spin Channel 206 are etched above the first and second 4-state magnets.

[0079] In some embodiments, at block 1 129 the etched portions are filled with an insulator (e.g., Oxide 205b). In some embodiments, Oxide 205b is etched to form a via hole which is then filled with a metal to form Via 207 such that it couples Spin Channel 206b at one end of Via 207 as illustrated by block 1 130. At block 1 131 , a second metal layer 201 b is deposited over Oxide 205b to make contact with the other end of Via 207. In some

embodiments, second metal layer 201b is coupled to a Power supply.

[0080] Fig. 12 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with a spin logic device with 4-state magnet, according to some embodiments of the disclosure. Spin logic devices (e.g., 200-500) can be used for making high density embedded memory to improve performance of computer system. Spin logic devices (e.g., 200-500) an also be used to form non-volatile logic components to enable improved power and performance optimization. As such, battery life for the smart device of computer system can improve (i.e., last longer). It is pointed out that those elements of Fig. 12 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0081] Fig. 12 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart- phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600.

[0082] For purposes of the embodiments, the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors, which include drain, source, gate, and bulk terminals. The transistors also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors— BJT PNP/NPN, BiCMOS, CMOS, eFET, etc., may be used without departing from the scope of the disclosure.

[0083] In some embodiments, computing device 1600 includes first processor 1610 with a spin logic device (e.g., 200/300/400/500/1 100) with stacking of magnets below a spin channel and with matched spacer for improved spin injection, according to some embodiments discussed. Other blocks of the computing device 1600 may also include a spin logic device with stacking of magnets below a spin channel and with matched spacer for improved spin injection, according to some embodiments. The various embodiments of the present disclosure may also comprise a network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

[0084] In some embodiments, processor 1610 (and/or processor 1690) can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

[0085] In some embodiments, computing device 1600 includes audio subsystem 1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610.

[0086] In some embodiments, computing device 1600 comprises display subsystem

1630. Display subsystem 1630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600. Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.

[0087] In some embodiments, computing device 1600 comprises I/O controller 1640.

I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I/O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

[0088] As mentioned above, I/O controller 1640 can interact with audio subsystem 1620 and/or display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640. [0089] In some embodiments, I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[0090] In some embodiments, computing device 1600 includes power management 1650 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 1660 includes memory devices for storing information in computing device 1600. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600.

[0091] Elements of embodiments are also provided as a machine-readable medium (e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[0092] In some embodiments, computing device 1600 comprises connectivity 1670.

Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices. The computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices. [0093] Connectivity 1670 can include multiple different types of connectivity. To generalize, the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674. Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile

communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

[0094] In some embodiments, computing device 1600 comprises peripheral connections

1680. Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from" 1684) connected to it. The computing device 1600 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600. Additionally, a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems.

[0095] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[0096] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or

characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an

embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

|0097] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0098] While the disclosure has been described in conjunction with specific

embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[0099] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[00100] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process. [00101] For example, an apparatus is provided which comprises: a 4-state input magnet; a first spin channel region adjacent to the 4-state input magnet; a 4-state output magnet; a second spin channel region adjacent to the 4-state input and output magnets; and a third spin channel region adjacent to the 4-state output magnet. In some embodiments, the 4-state input and output magnets are formed of a material selected from a group consisting of: Fe, Ni, Co and their alloys, magnetic insulators, and Heusler alloys of the form X2YZ. In some embodiments, the magnetic insulators are formed of a material selected from a group consisting of: magnetite Fe ₃ 0, and Y3AI5O12. In some embodiments, the Heusler alloys is one of: Co:FeSi and MrnGa.

[00102] In some embodiments, the first, second, and third spin channel regions are formed of a material selected from a group consisting of: Cu, Ag, Al, and 2D conducting materials. In some embodiments, the 2D conducting materials is graphene. In some embodiments, the apparatus comprises a first oxide region separating at least a portion of the first spin channel region from the second spin channel region. In some embodiments, the apparatus comprises a second oxide region separating at least a portion the second spin channel region from the third spin channel region.

[00103] In some embodiments, a portion of the first spin channel region is adjacent to a portion of the second spin channel region, and wherein a portion of the second spin channel region is adjacent to a portion of the third spin channel region. In some embodiments, the apparatus comprises a third oxide region separating the 4-state input magnet from the 4-state output magnet. In some embodiments, the apparatus comprises a non-magnetic metal adjacent to the 4-state input magnet from the 4-state output magnet. In some embodiments, the nonmagnetic metal is coupled to a positive supply to configure the apparatus as a buffer.

[00104] In some embodiments, the non-magnetic metal is coupled to a negative supply to configure the apparatus as an inverter. In some embodiments, the apparatus comprises a via adjacent to the second spin channel region. In some embodiments, the apparatus comprises a non-magnetic metal adjacent to via. In some embodiments, the 4-state input and output magnets have cubic magnetic crystalline anisotropy. In some embodiments, the 4-state input magnet overlaps the second spin channel region more than 4-state output magnet overlaps the second spin channel region.

[00105] In another example, a system is provided which comprises: a memory; a processor coupled to the memory, the processor including an apparatus according tot eh apparatus described above; and a wireless interface for allowing the processor to communicate with another device.

[00106] In another example, an apparatus is provided which comprises: a 4-state input magnet; a first filter layer adjacent to the 4-state input magnet; a first spin channel region adjacent to the first filter layer; a 4-state output magnet; a second filter layer adjacent to the 4- state output magnet; a second spin channel region adjacent to the first and second filter layers; and a third spin channel region adjacent to the second filter layer. In some embodiments, the 4- state input and output magnets are formed of a material selected from a group consisting of: Fe, Ni, Co and their alloys, magnetic insulators, and Heusler alloys of the form X ₂ YZ.

[00107] In some embodiments, the magnetic insulators are formed of a material selected from a group consisting of: magnetite F&OA and Υ3ΑΙ5ΟΠ. In some embodiments, the Heusler alloys is one of: Co ₂ FeSi and Mn ₂ Ga. In some embodiments, the first, second, and third spin channel regions are formed of a material selected from a group consisting of: Cu, Ag, Al, and 2D conducting materials. In some embodiments, the 2D conducting materials include graphene. In some embodiments, the first and second filter layers are formed of a material selected from a group consisting of: MgO, AI2O3, BN, MgAhCM, ZnAkC , SiMg204, and SiZ C , and NiFeO. In some embodiments, the 4-state input magnet and the first filter layer overlap the second spin channel region more than 4-state output magnet and second filter layer overlap the second spin channel region.

[00108] In another example, a system is provided which comprises: a memory; a processor coupled to the memory, the processor including an apparatus according tot eh apparatus described above; and a wireless interface for allowing the processor to communicate with another device.

[00109] In another example, an apparatus is provided which comprises: a 4-state input magnet; and a first interface layer adjacent to the 4-state input magnet, wherein the first interface layer is formed of a non-magnetic material such that the first interface layer and the input magnet together have sufficiently matched atomistic crystalline layers. In some embodiments, the apparatus comprises: a first spin channel region partially adjacent to the first interface layer.

[00110] In some embodiments, the apparatus comprises: a 4-state output magnet; and a second interface layer adjacent to the 4-state output magnet, wherein the second interface layer is formed of a non-magnetic material such that the second interface layer and the output magnet together have sufficiently matched atomistic crystalline layers. In some embodiments, the apparatus comprises: a second spin channel region partially adjacent to the first and second interface layers; and a third spin channel region partially adjacent to the second interface layer.

[00111] In some embodiments, the 4-state input magnet and the second interface layer overlap the second spin channel region more than 4-state output magnet and second interface layer overlap the second spin channel region. In some embodiments, the sufficiently matched atomistic crystalline layers are matched within a threshold percentage which is low enough to not cause lattice mismatch. In some embodiments, the non-magnetic material of the first and second interface layers is formed of a material selected from a group consisting of: Ag and Ag-like material. In some embodiments, the apparatus comprises: a via adjacent to the second spin channel region; a third interface layer adjacent to via; and a non-magnetic metal adjacent to the third interface layer.

[00112] In another example, a system is provided which comprises: a memory; a processor coupled to the memory, the processor including an apparatus according tot eh apparatus described above; and a wireless interface for allowing the processor to communicate with another device.

[00113] In another example, a method is provided which comprises: depositing a first metal layer; depositing a first interface layer on the first metal layer, the first interface layer formed of a non-magnetic material; depositing a 4-state magnet layer over the first interface layer; and depositing a second interface layer over the 4-state magnet layer, wherein depositing of the first metal layer, first interface layer, 4-state magnet layer, and second interface layer is performed in situ. In some embodiments, the method comprises: depositing a photo-resist material over the second interface layer to pattern first and second 4-state magnets; and etching, after depositing the photo-resist, the second interface layer and the magnet layer to form first and second portions of the second interface layer over the first and second 4-state magnets, respectively.

[00114] In some embodiments, the method comprises depositing a spin channel over the first and second portions of second interface layer. In some embodiments, the method comprises etching portions of the spin channel above the first and second 4-state magnets. In some embodiments, the method comprises filing the etched portions with an insulator to provide barriers between portions of the spin channel. In some embodiments, the method comprises: forming a via such that it is adjacent to the spin channel at one end of the via; and depositing a second metal layer over the via at the other end of the via.

[00115] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.