FIELD OF THE INVENTION

[0001] The present invention relates generally to photodetectors and more particularly to multi-mode infrared photodetectors.

BACKGROUND

[0002] Photodetectors detect radiation and output current based on the detected radiation. Photodetectors are typically configured to operate in active and passive imaging modes for various imaging applications that are utilized in security, machine vision, and the like. To operate in the active imaging mode, the photodetector includes a light source for imaging whereas to operate in the passive imaging mode, the photodetector relies on ambient light and does not include the light source for imaging. It is known in the art that operating a single photodetector in multiple active and passive imaging modes results in trade-offs. For example, to operate in the passive imaging mode (such as in a low noise imaging mode), a photodetector is designed to have minimal photodiode dark currents and limited signal chain noise, resulting in a low speed of operation. When the same photodetector is operated in the active imaging mode that requires a high speed of operation, the slow timing response of the photodetector affects the performance. Further, a photodetector designed to operate in the passive imaging mode typically uses photodiodes that have zero internal gain. Hence, for operating such a photodetector in the active imaging mode, a high gain front-stage is required in the photodetector to achieve reasonable signal-to-noise ratio. In addition, a photodetector that has a high gain front-stage, has a slow response time and is hence unsuitable for active imaging. Due to the aforementioned trade-offs, when the photodetector is configured to operate in one mode, its efficiency of operating in other active and passive imaging modes is compromised.

[0003] Thus, it would be advantageous to have a photodetector that is optimized for operating in both the active and passive imaging modes.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The following detailed description of the preferred embodiments of the present invention will be better understood when read in conjunction with the appended drawings. The present invention is illustrated by way of example, and not limited by the accompanying figures, in which like references indicate similar elements.

[0005] FIG. 1 is a block diagram of a photodetector in accordance with an embodiment of the present invention;

[0006] FIG. 2 is a block diagram of a readout integrated circuit (ROIC) of the photodetector of FIG. 1 in accordance with an embodiment of the present invention;

[0007] FIG. 3 is a block diagram of a system of an ROIC and an image processing SoC of the photodetector of FIG. 1 in accordance with another embodiment of the present invention;

[0008] FIG. 4 is a block diagram of a first input cell of the ROIC of FIG. 2 in accordance with an embodiment of the present invention;

[0009] FIG. 5 is a block diagram of a first capacitor bank of the first input cell of FIG. 4 in accordance with an embodiment of the present invention;

[0010] FIG. 6 is a block diagram that illustrates an operation of the first input cell of FIG. 4 in a low-noise imaging mode and a first high dynamic range (HDR) imaging mode in accordance with an embodiment of the present invention;

[0011] FIG. 7 is a block diagram that illustrates an operation of the first input cell of FIG. 4 in a second HDR imaging mode in accordance with an embodiment of the present invention;

[0012] FIG. 8 is a block diagram that illustrates an operation of the first input cell of FIG. 4 in low-light anti-blooming and laser-detection modes in accordance with an embodiment of the present invention;

[0013] FIG. 9 is a timing diagram that illustrates an operation of the first input cell of FIG. 4 during a detection of a low-power and short duration laser beam in the laser-detection mode in a low ambient illumination in accordance with an embodiment of the present invention;

[0014] FIG. 10 is a block diagram that illustrates an operation of the first input cell of FIG. 4 in a time-gated imaging mode in accordance with an embodiment of the present invention;

[0015] FIG. 11 A illustrates a structure of a first photodiode of a photodiode array of the photodetector of FIG. 1 in accordance with an embodiment of the present invention;

[0016] FIG. 11B illustrates a structure of the first photodiode in accordance with another embodiment of the present invention; [0017] FIG. 12A illustrates a passive imaging mode operation of the first photodiode of FIG. 11 A in accordance with an embodiment of the present invention;

[0018] FIG. 12B illustrates an active imaging mode operation of the first photodiode of FIG. 11 A in accordance with an embodiment of the present invention;

[0019] FIG. 13A illustrates the passive imaging mode operation of the first photodiode of FIG. 11B in accordance with another embodiment of the present invention;

[0020] FIG. 13B illustrates the active imaging mode operation of the first photodiode of FIG. 11B in accordance with another embodiment of the present invention;

[0021] FIG. 14A illustrates a top view of a type-l test structure in accordance with an embodiment of the present invention;

[0022] FIG. 14B illustrates a top view of a type-2 test structure in accordance with an embodiment of the present invention;

[0023] FIG. 14C illustrates a top view of a type-3 test structure in accordance with an embodiment of the present invention; and

[0024] FIG. 14D illustrates a top view of a type-4 test structure in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION

[0025] The detailed description of the appended drawings is intended as a description of the currently preferred embodiments of the present invention, and is not intended to represent the only form in which the present invention may be practiced. It is to be understood that the same or equivalent functions may be accomplished by different embodiments that are intended to be encompassed within the spirit and scope of the present invention.

[0026] In one embodiment, the present invention provides a photodiode. The photodiode includes a bottom layer that has a first conductivity type. The photodiode further includes a set of absorber layers that is formed on top of the bottom layer. At least a thickness and a doping concentration of each absorber layer of the set of absorber layers is based on a total dark current of the photodiode. The photodiode further includes a top layer that has one of a second conductivity type that is different from the first conductivity type, or the first conductivity type such that the top layer further includes a diffused region or an implanted region of the second conductivity type. Further, the top layer is formed on top of the set of absorber layers. The photodiode is configured to operate in active and passive imaging modes for receiving an infrared radiation and generating an output current based on the received infrared radiation. [0027] In another embodiment, the present invention provides a photodetector. The photodetector includes a photodiode array that generates a set of output currents. A first photodiode of the photodiode array includes a bottom layer that has a first conductivity type. The first photodiode further includes a set of absorber layers that is formed on top of the bottom layer. At least a thickness and a doping concentration of each absorber layer of the set of absorber layers is based on a total dark current of the first photodiode. The first photodiode further includes a top layer that has one of a second conductivity type that is different from the first conductivity type, or the first conductivity type such that the top layer further includes a diffused region or an implanted region of the second conductivity type. Further, the top layer is formed on top of the set of absorber layers. The second conductivity type is different from the first conductivity type. The first photodiode is configured to operate in active and passive imaging modes for receiving an infrared radiation and generating a first output current of the set of output currents based on the received infrared radiation. The photodetector further includes a readout integrated circuit. The readout integrated circuit is connected to the photodiode array for receiving the set of output currents and generating a set of voltage signals based on the set of output currents, respectively.

[0028] Various embodiments of the present invention provide a photodiode and a photodetector that includes the photodiode and a readout integrated circuit (ROIC). The photodiode receives an infrared radiation and generates an output current based on the received infrared radiation. The ROIC receives the output current and generates a voltage signal based on the output current. The photodiode includes top and bottom layers and a set of absorber layers formed in between the top and bottom layers. At least a thickness and a doping concentration of each absorber layer of the set of absorber layers is based on a total dark current of the photodiode. Further, a first space charge region (SCR) of the photodiode is formed within the top layer and one or more absorber layers of the set of absorber layers such that the first SCR has a first depth in the passive imaging mode. In an active imaging mode, due to the thickness and doping concentration of each absorber layer and an application of a low reverse voltage across the photodiode, a second SCR of the photodiode is formed within the top layer and one or more absorber layers of the set of absorber layers such that the second SCR has a second depth. The second depth is larger than the first depth. Thus, a capacitance of the photodiode and a response time of the photodetector is reduced, and responsivity of the photodiode is improved as compared to conventional photodiodes.

[0029] As the thickness and doping concentration of each absorber layer is based on the total dark current, the photodiode has less dark current in the passive imaging mode than the dark current in conventional photodiodes. Further, the doping concentration and thickness of each absorber layer and the applied low reverse voltage ensure that a capacitance of the photodiode is less in the active imaging mode than the passive imaging mode. Thus, the photodetector has a lower response time and a higher signal-to-noise ratio than the response time and signal-to-noise ratio of conventional photodetectors.

[0030] FIG. 1 is a block diagram of a photodetector 100 in accordance with an embodiment of the present invention. The photodetector 100 includes a photodiode array 102 and a readout integrated circuit (ROIC) 104. The photodetector 100 is configured to operate in both active and passive imaging modes. In the passive imaging mode, the photodetector 100 is configured to operate in one of a low-noise imaging mode, first and second high dynamic range (HDR) imaging modes, a laser-detection mode, and a low-light anti-blooming mode. In the active imaging mode, the photodetector 100 is configured to operate in a time gated imaging mode. Each of the low-noise imaging and first HDR imaging, second HDR imaging, laser-detection and low-light anti-blooming, and time-gated imaging modes are explained in FIGS. 6, 7, 8 and 9, and 10, respectively.

[0031] The photodiode array 102 includes a set of photodiodes of which first through sixth photodiodes D1-D6 are shown. In the presently preferred embodiment, the set of photodiodes is arranged in a two-dimensional array. In another embodiment, the set of photodiodes is arranged in a one-dimensional array.

[0032] The photodiode array 102 receives infrared radiation IR and generates a set of output currents [Ii, H, ...] based on the received infrared radiation IR. Thus, the first through sixth photodiodes D1-D6 receive the infrared radiation IR and generate first through sixth output currents I i-L·,. respectively. The first through sixth photodiodes D1-D6 are optimized to operate in the active and passive imaging modes and are structurally and functionally similar. A structure of the first photodiode Di is explained in conjunction with FIGS. 11A-11B, 12A- 12B, and 13A-13B. The structure of the first photodiode Di is based on a total dark current of the first photodiode Di. The total dark current is generated by the first photodiode Di when the infrared radiation IR is absent or present. The dark current components of the total dark current are identified from multiple test structures (illustrated in FIGS. 14A-14D).

[0033] The ROIC 104 is connected to the photodiode array 102 for receiving the set of output currents [Ii, I2, ...]. In one embodiment, the ROIC 104 and the photodiode array 102 are connected by way of a flip-chip bonding. In another embodiment, the ROIC 104 and the photodiode array 102 are connected by way of wire-bonds. The ROIC 104 operates in at least one of a global shutter mode or a rolling shutter mode. In the global shutter mode, each photodiode of the photodiode array 102 is exposed to the infrared radiation IR

simultaneously. In the rolling shutter mode, the photodiode array 102 is exposed to the infrared radiation IR such that a subset of photodiodes is exposed at a time. The subset of photodiodes may correspond to photodiodes that are arranged in a row or a column or a single photodiode. Based on requirements of video parameters (such as frame rate) of the ROIC 104, the ROIC 104 may be configured to operate in an integrate-then-read (ITR) mode, an integrate-while-read (IWR) mode, or a non-destructive readout (NDR) mode.

[0034] The ROIC 104 processes the set of output currents [Ii, B, ...] and generates a set of voltage signals [Vi, V2, ...], respectively. Thus, the ROIC 104 generates first through sixth voltage signals V1-V6 based on the first through sixth output currents I i-L·,. respectively. The set of voltage signals [Vi, V2, ...] is digital. In other implementations of the ROIC 104, the set of voltage signals [Vi, V2, ...] may be analog. Further, the set of voltage signals [Vi, V2,

... ] is provided to a signal correction and processing circuitry (not shown) or a computer system (not shown) for further processing. Although it is shown that the photodetector 100 includes the photodiode array 102 and the ROIC 104, it will be understood by a person ordinarily skilled in the art that the present invention is not limited to it, and the photodetector 100 may further include the analog and digital signal correction and processing circuitry. Further, the ROIC 104 may be connected with multiple photodiode arrays (not shown) other than the photodiode array 102.

[0035] FIG. 2 is a block diagram of the ROIC 104 in accordance with an embodiment of the present invention. The ROIC of FIG. 2 is hereinafter referred to as“the ROIC1 200”. The ROIC1 200 includes an input cell array 202, a signal processing circuitry 204, a first ADC 206, a digital output driver 208, and a first configuration logic and clock and timing controller (CLCTC) 210 that drives the input cell array 202, the signal processing circuitry 204, the first ADC 206, and the digital output driver 208. The ROIC1 200 may further include a supply voltage circuitry (not shown), a reference voltage circuitry (not shown), array decoders (not shown), and the like.

[0036] The input cell array 202 includes a set of input cells, of which first through sixth input cells 202a-202f, are shown. The set of input cells is arranged in a set of rows and a set of columns, of which first through third rows and first and second columns are shown. Thus, the set of input cells is arranged in a two-dimensional array. The first row includes the first and second input cells 202a and 202b, the second row includes the third and fourth input cells 202c and 202d, and the third row includes the fifth and sixth input cells 202e and 202f. The first column includes the first, third, and fifth input cells 202a, 202c, and 202e, respectively, and the second column includes the second, fourth, and sixth input cells 202b, 202d, and 202f, respectively. The first through sixth input cells 202a-202f are structurally and functionally similar. In another embodiment of the present invention, the set of input cells may be arranged in a one -dimensional array.

[0037] The input cell array 202 is connected to the photodiode array 102 for receiving the set of output currents [Ii, I2, ...] and generating a set of sampled voltage signals [V _sampi , V _Samp 2, ... ] . Thus, the first input cell 202a is connected to the first photodiode D 1 for receiving the first output current Ii and generating first and second sampled voltage signals V _sampi and V _samp 2. The first input cell 202a is explained in detail in conjunction with FIGS. 4-10.

[0038] The signal processing circuitry 204 is connected to the input cell array 202 for receiving the set of sampled voltage signals [V _sampi , V _samp 2, ...] . Further, the signal processing circuitry 204 processes the set of sampled voltage signals [V _sampi , V _Samp 2, ...] and generates and provides a set of processed voltage signals [V _pi , V _P 2, ...] to the first ADC 206 for digitization. The signal processing circuitry 204 and the first ADC 206 may be column- based, output-based, or a combination thereof. The first ADC 206 digitizes the set of processed voltage signals [V _pi , V _P 2, ...] to generate a set of digital output signals [V _di , V _d 2,

... ] . The digital output driver 208 is connected to the first ADC 206 for receiving the set of digital output signals [V _di , V _d 2, ... ] . In one embodiment, when the first ADC 206 is column- based, the digital output driver 208 time-multiplexes the set of digital output signals [V _di ,

V _d 2, ...] from the first ADC 206 and generates each voltage signal of the set of voltage signals [V 1, V2, ... ] one at a time. In another embodiment, when the first ADC 206 is output- based, the digital output driver 208 simultaneously generates each voltage signal of the set of voltage signals [Vi, V2, ... ] . It will be apparent to a person skilled in the art that the ROIC 1 200 may include more than one output-based ADCs and digital output drivers.

[0039] The first CLCTC 210 is connected to the input cell array 202, the signal processing circuitry 204, the first ADC 206, and the digital output driver 208 for

configuration of the ROIC1 200 in different active and passive imaging modes explained in conjunction with FIGS. 4-10.

[0040] The first CLCTC 210 further generates and provides clock signals [Clkl, Clk2,

... ] and timing control signals [TS 1 , TS2, ... ] to the input cell array 202, the signal processing circuitry 204, the first ADC 206, and the digital output driver 208. Further, the first CLCTC 210 communicates with an external light source (not shown) for the time-gated imaging mode. In one embodiment, the first CLCTC 210 includes a phase-locked-loop (not shown) for generating the clock and timing control signals [Clkl, Clk2... .] and [TS1, TS2,

[0041] FIG. 3 is a block diagram of a system 300 of an ROIC2 302 and an image processing SoC 304 in accordance with another embodiment of the present invention. The ROIC2 302 consumes low power as compared to the ROIC1 200, since few power consuming circuit blocks of the ROIC1 200 such as the supply and reference voltage circuitries, the first ADC 206, and the like are implemented on the image processing SoC 304. In one embodiment, the system 300 is included in the photodetector 100. In another embodiment, the ROIC2 302 is included in the photodetector 100, and the image processing SoC 304 is externally connected to the ROIC2 302.

[0042] The ROIC2 302 includes the input cell array 202, the signal processing circuitry 204, a second CLCTC 306, and an analog output driver 308. The second CLCTC 306 is functionally similar to the first CLCTC 210. The second CLCTC 306 generates the timing control signals [TS1, TS2, ...]. The second CLCTC 306 further generates configuration signals (not shown) for configuring the input cell array 202, the signal processing circuitry 204, and the analog output driver 308. The image processing SoC 304 includes a second ADC 310, a digital image signal processor 312, a system controller 314, and a memory 316. The image processing SoC 304 may further include the supply and reference voltage circuitries (not shown), a clock generator (not shown) for generating the clock signals [Clkl, Clk2, ... ], and the like for the ROIC2 302 and the image processing SoC 304.

[0043] The signal processing circuitry 204 is connected to the input cell array 202 and the second CLCTC 306 for receiving the set of sampled voltage signals [Vsampi, Vsamp2, . . . ] and the timing control signals [TS1, TS2, ...], respectively. The signal processing circuitry 204 processes the set of sampled voltage signals [Vsampi, Vsamp2, . .. ] to generate the set of processed voltage signals [V _p i, V _P 2, ...] that are analog. Post analog signal processing, the signal processing circuitry 204 provides the set of processed voltage signals [V _p i, V _P 2, ...] to the analog output driver 308. The analog output driver 308 may be configured to amplify the set of processed voltage signals [V _p i, V _P 2, ...] to generate a set of amplified and buffered output signals [V _a i, Va2, ...] . The signal processing circuitry 204 and the analog output driver 308 are column-based, output-based, or a combination thereof. It will be apparent to a person skilled in the art that the ROIC2 302 may include more than one analog output driver.

[0044] The second ADC 310 is connected to the analog output driver 308 for receiving the set of amplified and buffered output signals [V _a i, V _a 2, ...]. The second ADC 310 digitizes the set of amplified and buffered output signals [V _a i, V _a 2, ...] to generate the set of digital output signals [V _di , V _d 2, ... ] which are provided to the digital image signal processor 312. In one embodiment, the second ADC 310 receives each amplified and buffered output signal one at a time and generates each digital output signal one at a time. It will be apparent to a person skilled in the art that the system 300 may include multiple analog drivers and ADCs such that each ADC digitizes an output received from a corresponding analog driver.

[0045] The digital image signal processor 312 is connected to the second ADC 310 for receiving the set of digital output signals [V _di , V _d 2, ...]. The digital image signal processor 312 generates the set of voltage signals [V V2, For generating the set of voltage signals [Vi, V2, ...], the digital image signal processor 312 may further execute various image processing operations such as, but not limited to, pixel offset and gain correction, bad-pixel- replacement, histogram equalization, automatic gain control, and image filtering and sharpening. In one embodiment, the digital image signal processor 312 is a digital infrared image signal processor (IR-ISP).

[0046] The system controller 314 is connected to the second ADC 310 and the digital image signal processor 312 for synchronizing the generation of the set of digital output signals [V _di , V _d 2, ... ] and the set of processed digital output signals (/. e. , the set of voltage signals [Vi, V2, ... ]). Further, the system controller 314 controls the second CLCTC 306 for controlling different operations of the ROIC2 302 (such as generation and transfer of the set of amplified and buffered output signals [V _ai , V _a 2, ...] from the analog output driver 308 to the second ADC 310).

[0047] The memory 316 stores instructions to be executed by the system controller 314 and/or the digital image signal processor 312. The memory 316 further stores data needed for configuration by the second CLCTC 306 and digital signal correction and processing by the digital image signal processor 312. Further, the memory 316 stores data, if generated, by the digital image signal processor 312 during the various image processing operations.

[0048] The image processing SoC 304 may further include one or more output devices (not shown) to process the set of voltage signals [V 1, V2, ... ] and provide media output in video and image formats. Further, the image processing SoC 304 may include devices (not shown) that receive the media output, and enable cognitive learning and generate artificially intelligent media information such as, but not limited to, videos and images.

[0049] For the sake of ongoing discussion, an operation of the photodetector 100 is explained with the ROIC1 200 without deviating from the scope of the present invention.

[0050] FIG. 4 is a block diagram of the first input cell 202a in accordance with an embodiment of the present invention. The first input cell 202a is connected to the first photodiode Dl for receiving the first output current Ii. The first input cell 202a includes a first switch Sl, a capacitive transimpedance amplifier (CTIA) integrator 402, a direct injection (DI) integrator 404, a buffer 406, a second switch S2, and a comparator 408. The first input cell 202a receives a control voltage signal CV for controlling the DI integrator 404 from an on-chip or an off-chip supply and reference block (not shown).

[0051] The first switch Sl is connected to the first photodiode Di. The CTIA integrator 402 is connected to the first switch S 1 and receives the first output current Ii by way of the first switch S 1. Thus, the first switch S 1 connects or disconnects the CTIA integrator 402 with the first photodiode Di. In another embodiment, the first switch S l is absent in the first input cell 202a, and the CTIA integrator 402 is connected or disconnected from the first photodiode Di by way of a power-down signal (not shown) generated by the first CLCTC 210. The CTIA integrator 402 integrates the first output current Ii and generates the first sampled voltage signal Vsampi . The CTIA integrator 402 integrates the first output current Ii with a high linearity and a high signal-to-noise ratio.

[0052] The CTIA integrator 402 includes an output transconductance amplifier (OTA) 410, a series arrangement SA, a first sample -and-hold arrangement SHi, and a third switch S3. The OTA 410 is connected to the first switch Sl . The series arrangement SA is connected across the OTA 410 to form a first feedback loop. Due to the first feedback loop, the CTIA integrator 402 provides a stable bias voltage (i.e.. an anode voltage V _a ) to the first photodiode Di through the first switch S l (i.e.. in the low-noise imaging, first HDR imaging, low-light anti-blooming, and laser-detection modes). The OTA 410 has a first transconductance gnipassive in the passive imaging mode and a second transconductance gm _ac tive in the active imaging mode. The second transconductance gm _ac tive is greater than the first transconductance gnipassive.

[0053] The series arrangement SA receives the first output current Ii and generate a first intermediate voltage signal Vmti based on a current-to-voltage conversion gain of the CTIA integrator 402. The series arrangement SA includes a first capacitor Cl in series with a fourth switch S4. The current-to-voltage conversion gain of the CTIA integrator 402 is based on a capacitance of the first capacitor C 1.

[0054] The first capacitor C 1 is a gain control and feedback capacitor and is part of a first capacitor bank 500 (shown in FIG. 5). The first capacitor Cl has a variable capacitance, in the range of 0.01-0.3 pico farad (pF). For operating the first input cell 202a in the low- noise passive and active imaging modes, the first capacitor Cl is configured with a low capacitance value, and for operating the first input cell 202a in other passive imaging modes, such as the first HDR imaging mode, the first capacitor Cl is configured with a high capacitance value.

[0055] The fourth switch S4 connects or disconnects the first capacitor Cl to the OTA 410. The first capacitor Cl is configured by the first CLCTC 210. The third switch S3 is connected across the OTA 410 and the series arrangement SA. When the third switch S3 is activated, the CTIA integrator 402 is reset. In one example, the first through fourth switches S1-S4 are metal-oxide -semiconductor (MOS) transistors and are activated and deactivated by the timing control signals [TS1, TS2, ...] .

[0056] The first sample -and-hold arrangement SHi is connected to the OTA 410 and the series arrangement SA for receiving the first intermediate voltage signal Vmti . The first sample-and-hold arrangement SHi samples the first intermediate voltage signal Vmti to generate the first sampled voltage signal Vsampi . The first sample-and-hold arrangement SHi includes a second capacitor C2 and a fifth switch S5. The fifth switch S5 is connected to the OTA 410 and connects or disconnects the second capacitor C2 to/from the OTA 410. The first sample-and-hold arrangement SHi is further connected to ground.

[0057] The second capacitor C2 is a sampling capacitor and is a part of the first capacitor bank 500. Further, the second capacitor C2 has variable capacitance that is configured by the first CLCTC 210. In one example, the fifth switch S5 is a MOS transistor and is activated and deactivated by the timing control signals [TS1, TS2, ...]. In another embodiment of the present invention, the CTIA integrator 402 includes multiple sample-and-hold arrangements that are structurally and functionally similar to the first sample-and-hold arrangement SHi, and execute a correlated multi-sampling operation at different time-instants during the integration of the first output current L.

[0058] The DI integrator 404 is connected to the first photodiode D i for receiving the first output current L. The DI integrator 404 integrates the first output current L and generates the second sampled voltage signal V _S amp2.

[0059] The DI integrator 404 includes a first transistor Tl, a second sample-and-hold arrangement STL, and a sixth switch S6. The first transistor Tl has a drain terminal connected to the first photodiode Di for receiving the first output current L and a gate terminal connected to the second switch S2 for receiving the first intermediate voltage signal Vmti as an operational gate voltage V _g . The gate terminal is further connected to a seventh switch S7 for receiving the control voltage signal CV as the operational gate voltage V _g . The first transistor Tl further has a source terminal that generates a second intermediate voltage signal Vi _n and is connected to the second sample-and-hold arrangement SH2. In one embodiment, the first transistor Tl is a p-type MOS transistor operating in a common-gate configuration.

[0060] The second sample-and-hold arrangement SFh includes a third capacitor C3 that is connected in series with an eighth switch S8 and further connected to the source terminal of the first transistor Tl for generating the second intermediate voltage signal Vi _nt 2. The third capacitor C3 has a variable capacitance which is configured by the first CLCTC 210. The third capacitor C3 acts as an integration as well as a sampling capacitor of the DI integrator 404 and is a part of the first capacitor bank 500. When the DI integrator 404 is enabled, the second sample-and-hold arrangement SFh integrates the first output current Ii based on the third capacitor C3 and generates the second intermediate voltage signal V _mt 2. Further, the second sample-and-hold arrangement SFh samples the second intermediate voltage signal Vine to generate the second sampled voltage signal V _Samp 2. In one example, the sixth through eighth switches S6-S8 are MOS transistors and are activated and deactivated by the timing control signals [TS1, TS2, ...] .

[0061] The second sample-and-hold arrangement SFh is further connected to ground.

The sixth switch S6 is connected to the second sample-and-hold arrangement SFh and the source terminal of the first transistor Tl . The sixth switch S6 is further connected to one of ground and an intermediate node Nm _t for resetting the DI integrator 404. The sixth switch S6 is connected or disconnected to ground in the second HDR imaging and low -light anti blooming modes, and to the intermediate node N _mt in the laser-detection mode. The intermediate node Nm _t has a configurable intermediate voltage level that is higher than ground. When the DI integrator 404 is reset, the third capacitor C3 is charged to one of ground and the intermediate voltage level. In one example, the sixth switch S6 is a single pole double throw switch implemented by way of MOS transistors and is activated and deactivated by the timing control signals [TS 1, TS2, ...].

[0062] The buffer 406 is connected to the CTIA and DI integrators 402 and 404 for receiving the first and second sampled voltage signals V _sampi and V _Samp 2, respectively. The buffer 406 provides the first and second sampled voltage signals V _sampi and V _samp 2 to the signal processing circuitry 204, the first ADC 206, and the digital output driver 208 for generation of the first voltage signal Vi.

[0063] The second switch S2 is connected to the CTIA and DI integrators 402 and 404 to form a second feedback loop. Due to the second feedback loop, the first input cell 202a prevents a blooming phenomenon in the low-light anti-blooming and laser-detection modes (explained in FIG. 8). [0064] The comparator 408 has first and second input terminals connected to the CTIA integrator 402 and the source terminal of the first transistor Tl for receiving the first and second intermediate voltage signals Vmti and V,m2. respectively. The comparator 408 compares the first and second intermediate voltage signals Vmti and V _{l lU} 2. The comparator 408 further has an output terminal for generating a comparison signal V _¥ mp based on a comparison of the first and second intermediate voltage signals Vmti and Vmti in the low-light anti-blooming and laser-detection modes (as explained in FIG. 8). In one embodiment, the comparator 408 is a low -power asymmetric comparator. The first input cell 202a may further include bandwidth limiting capacitors (not shown) for controlling bandwidths of noise generating analog circuits (such as the CTIA integrator 402).

[0065] FIG. 5 is a block diagram of the first capacitor bank 500 in accordance with an embodiment of the present invention. The first capacitor bank 500 includes a set of capacitors 502 and a switching matrix 504. The set of capacitors 502 includes fixed capacitors, variable capacitors, and/or a combination thereof. The variable capacitors are configured by the first CLCTC 210 based on the active and passive imaging modes. Any number of fixed and variable capacitors may be grouped to achieve desired capacitances for feedback, gain control, sampling, or bandwidth limiting capacitors, including the first through third capacitors C1-C3.

[0066] The switching matrix 504 includes a set of switches (not shown) that enables configuration of capacitance values via grouping/un-grouping of fixed or variable capacitors of the set of capacitors 502. The switching matrix 504 is configured by the first CLCTC 210 based on the active and passive imaging modes.

[0067] FIG. 6 is a block diagram that illustrates an operation of the first input cell 202a in the low-noise and first HDR imaging modes in accordance with an embodiment of the present invention. In the low-noise and first HDR imaging modes, the seventh switch S7 is activated to supply the control voltage signal CV to deactivate the first transistor Tl. Further, the second switch S2 is deactivated and the DI integrator 404 is deactivated (shown by dotted lines). As the first switch Sl is activated, the CTIA integrator 402 is activated (shown by solid lines). Further, the fourth switch S4 is activated to connect the first capacitor Cl to the OTA 410.

[0068] In the low noise imaging mode, the first capacitor Cl is configured to have a low capacitance value. Further, the second capacitor C2 is configured through the first capacitor bank 500 for having a large capacitance to limit the bandwidth of the CTIA integrator 402. The CTIA integrator 402 thus operates with a high linearity to generate the first sampled voltage signal Vsampi . The buffer 406 receives the first sampled voltage signal Vsampi and provides the first sampled voltage signal Vsampi to the signal processing circuitry 204.

[0069] In the first HDR imaging mode, the first capacitor Cl is configured by the first CLCTC 210 based on an optimum balance of a dynamic range (DR) and a signal -to-noise ratio. For example, when a high DR is required, the first capacitor Cl is configured to have a high capacitance (i.e.. to have a high full well capacity (FWC)). Further, the second capacitor C2 and the bandwidth limiting capacitors are configured such that the optimum balance of the DR and signal-to-noise ratio is obtained in the first HDR imaging mode. The first input cell 202a is typically operated in the first HDR imaging mode when an ambient illumination is high.

[0070] FIG. 7 is a block diagram that illustrates an operation of the first input cell 202a in the second HDR imaging mode in accordance with an embodiment of the present invention. In the second HDR imaging mode, the control voltage signal CV activates the first transistor Tl by the way of the seventh switch S7. Thus, the DI integrator 404 is activated (shown by solid lines). Further, the first and second switches Sl and S2 are deactivated by the first CLCTC 210, thereby deactivating the CTIA integrator 402 (shown by dotted lines).

[0071] The eighth switch S8 is activated and deactivated to connect and disconnect the third capacitor C3 to the source terminal of the first transistor Tl for generating the second intermediate and sampled voltage signals V _{l lU} 2 and V _S amp2. Further, the third capacitor C3 is configured to have a high capacitance. The high capacitance enables the DI integrator 404 to achieve a high DR for generating the second sampled voltage signal V _S amp2. The first input cell 202a typically operates in the second HDR imaging mode when an ambient illumination is moderate to high. The first input cell 202a consumes low power in the second HDR imaging mode as compared to the first HDR imaging mode.

[0072] FIG. 8 is a block diagram that illustrates an operation of the first input cell 202a in the low-light anti-blooming and laser-detection modes in accordance with an embodiment of the present invention. As the first switch S 1 is activated, the CTIA integrator 402 is activated. The first capacitor Cl is configured to have a high capacitance. Further, the seventh switch S7 is deactivated. The third capacitor C3 is configured to have a low capacitance such that a current-to-voltage conversion gain of the DI integrator 404 is high. The sixth switch S6 is configured to connect the source terminal of the first transistor Tl to ground for resetting the first input cell 202a. For detecting a low power laser beam of short duration, the sixth switch S6 is configured to connect the source terminal of the first transistor Tl to the intermediate node N _mt for resetting the first input cell 202a (illustrated in FIG. 9). [0073] The second switch S2 is activated to connect the CTIA and DI integrators 402 and 404 to form the second feedback loop. Due to the second feedback loop, the DI integrator 404 provides a low impedance path to the first output current Ii and integrates the first output current Ii to generate the second sampled voltage signal V _sa mp2 that is received by the buffer 406.

[0074] In a low-light environment (such as during night time), the first photodiode D i may receive a high infrared radiation IR (e.g., due to headlights of vehicles). Similarly, the first photodiode Di may receive a laser beam (that emits a high infrared radiation IR). Due to the high infrared radiation IR, a charge storage capacity of the third capacitor C3 is reached and the DI integrator 404 is saturated. The first transistor Tl is deactivated when the DI integrator 404 is saturated, thereby deactivating the DI integrator 404. Thus, the DI integrator 404 integrates the first output current Ii till a charge storage capacity of the third capacitor C3 is reached. After saturation, the DI integrator 404 provides a high impedance path to the first output current Ii. The CTIA integrator 402 then integrates the first output current Ii and generates the first sampled voltage signal Vsampi that is received by the buffer 406. Since the first capacitor Cl has a high FWC (due to the high capacitance), the CTIA integrator 402 remains unsaturated even under high illumination. Thus, due to the second feedback loop, the blooming phenomenon is prevented. In the blooming phenomenon, on receiving the high infrared radiation IR, the first photodiode Di leaks the first output current Ii into nearby photodiodes, thereby saturating corresponding DI integrators (not shown).

[0075] To identify a magnitude of the high infrared radiation IR, the signal processing circuitry 204, the first ADC 206, and the digital output driver 208 receive and accumulate the first and second sampled voltage signals Vsampi and V _S amp2 to generate the first voltage signal V i . The first voltage signal V i is thus directly proportional to the high infrared radiation IR.

[0076] To indicate the saturation of the DI integrator 404 in the low-light anti-blooming mode and the detection of the laser beam in the laser-detection mode, the comparator 408 receives the first and second intermediate voltage signals Vinti and Vint2 (that are sampled for generating the first and second sampled voltage signals Vsampi and V _sa mp2, respectively). The comparator 408 generates the comparison signal V _CO mp. A voltage level of the comparison signal Vcomp indicates the saturation of the DI integrator 404 in the low-light anti-blooming mode and the detection of the laser beam in the laser-detection mode. In one embodiment, when the first and second intermediate voltage signals Vinti and Vmt2 are approximately equal, the comparison signal Vcomp is high to indicate the saturation and detection. In another embodiment, when the first and second intermediate voltage signals Vinti and Vmt2 are approximately equal, the comparison signal Vcomp is low to indicate the saturation and detection.

[0077] FIG. 9 is a timing diagram that illustrates an operation of the first input cell 202a during a detection of a low-power and short duration laser beam in the laser-detection mode in low ambient illumination in accordance with an embodiment of the present invention. To reduce a time required for the DI integrator 404 to saturate, i.e., saturation time, the third capacitor C3 is discharged to the intermediate voltage level. The intermediate voltage level is configured to be close to a reset value of the first intermediate voltage signal Vmti (i.e., a voltage level of the first intermediate voltage signal Vmti when the CTIA integrator 402 is reset). A reset signal is provided by the first CLCTC 210 to the sixth switch S6 for resetting the DI integrator 404. In one embodiment, the DI integrator 404 is reset when the reset signal goes low.

[0078] For the sake of ongoing discussion, it is assumed that, during time period to-ti, the

DI integrator 404 is saturated and the CTIA integrator 402 integrates the first output current Ii. The first and second intermediate voltage signals Vmti and V,m2 are indicated by solid and dotted lines, respectively. Further, as the reset signal is high, the DI integrator 404 is active. At time ti, the reset signal is driven low by the first CLCTC 210 and thus, the DI integrator 404 is reset. The third capacitor C3 is discharged to the intermediate voltage level. As the first switch Sl is activated, the reset signal further resets the CTIA integrator 402. During time period ti-t ₂ , the CTIA and DI integrators 402 and 404 remain reset.

[0079] At time 12, the reset signal goes high, thereby activating the DI integrator 404.

Further, a low power laser beam of short duration is detected by the first photodiode D 1 which generates the first output current L. The DI integrator 404 provides a low impedance to the first output current Ii and initiates integration of the first output current Ii. During time period ti-L. the first output current L is integrated and the second intermediate voltage signal Vi m2 is generated. The CTIA integrator 402 remains reset.

[0080] At time t3, the DI integrator 404 is saturated and provides a high impedance path to the first output current L. Thus, the CTIA integrator 402 initiates integration of the first output current L. During time period Ϊ3-Ϊ4, the DI integrator 404 is saturated, and the first output current Ii is integrated by the CTIA integrator 402 and the first intermediate voltage signal Vinti is generated. The time period ti-L may be adjusted based on the ambient illumination, a value of the third capacitor C3, and the intermediate voltage level, to detect the low-power laser beam. It will be understood by a person skilled in the art that the photodetector 100 detects a laser beam during time period t ₄ -t ₇ in a similar manner as detection of a laser beam during the time period ti-fi, respectively.

[0081] FIG. 10 is a block diagram that illustrates an operation of the first input cell 202a in the time-gated imaging mode in accordance with an embodiment of the present invention. For the time-gated imaging mode, the photodetector 100 is integrated with the external a light source as a source of the infrared radiation IR. The light source emits the infrared radiation IR onto objects that are to be detected. In one embodiment, the light source is a laser source. Due to the laser source, the objects are detected reliably and a signal-to-noise ratio corresponding to the first output current Ii (generated based on an infrared radiation IR reflected from the objects) is increased, as compared to signal-to-noise ratios from other light sources.

[0082] In the time-gated imaging mode, the control voltage signal CV deactivates the first transistor Tl by the way of the seventh switch S7. Further, the second switch S2 is deactivated. Thus, the DI integrator 404 is deactivated (shown by dotted lines). The first switch Sl is activated, thereby activating the CTIA integrator 402 (shown by solid lines). The fourth switch S4 is activated to connect the first capacitor Cl to the OTA 410. The first capacitor Cl is configured to have a low capacitance to provide a high current-to-voltage conversion gain. As the first photodiode Di operates at a low exposure time (i.e. , a time duration for which the first photodiode Di is exposed to the infrared radiation IR is low) in the time-gated imaging, the second capacitor C2 is configured to have a low capacitance. Due to the low capacitance, the first sample -and-hold arrangement SHi samples the first intermediate voltage signal V _mti reliably when the first photodiode Di operates at the low exposure time. Further, the first transconductance gm _pas sive of the OTA 410 is increased to the second transconductance gm _ac tive. Due to the increased transconductance, a response time of the CTIA integrator 402 (i.e.. a time required for the CTIA integrator 402 to integrate the first output current Ii and generate the first sampled voltage signal V _sampi ) is reduced.

[0083] For increasing the first transconductance gm _passiVe to the second transconductance gm _active , a bias current of the OTA 410 is increased from a first current value to a second current value. Due to the increased transconductance in the active imaging mode, the response time of the CTIA integrator 402 is reduced. As a result, power consumption of the first input cell 202a is increased in the active imaging mode as compared to the passive imaging mode. In order to reduce the power consumption, a value of a supply voltage signal (now shown) is reduced in the active imaging mode as compared to the passive imaging mode. The on-chip or off-chip supply block provides the supply voltage signal in the passive imaging mode and reduces a value of the supply voltage signal in the active imaging mode. Due to the reduced response time and power consumption in the active imaging mode, the photodetector 100 is useful for applications such as missile or projectile detection, detection, testing, and the like.

[0084] FIG. 11A illustrates a structure of the first photodiode Di in accordance with an embodiment of the present invention. In one example, the first photodiode D i is used in a photodetector for back-side imaging. The first photodiode Di of FIG. 12A is implemented as a single absorber layer (SAL) photodiode Di _a . The SAL photodiode Di _a includes a bottom layer 1102, a first set of absorber layers 1104 that includes a first absorber layer 1106, and a top layer 1108. The bottom layer 1102 has a first conductivity type. In one embodiment, the top layer 1108 has a second conductivity type that is different from the first conductivity type. In another embodiment, the top layer 1108 has the first conductivity type. In such an embodiment, an additional impurity material having the second conductivity type is diffused or implanted through the top layer 1108 to form an island 1110 of a diffused region or an implanted region of the second conductivity type. The island 1110 is hereinafter referred to as “diffusion/implanted region 1110”.

[0085] The first absorber layer 1106 is formed on top of the bottom layer 1102. The first absorber layer 1106 may be of intrinsic type or of the first conductivity. For the sake of ongoing discussion and without limiting the scope of the present invention, it is assumed that the first conductivity type is n-type and the second conductivity type is p-type. In one example, the first set of absorber layers 1104 is of intrinsic (i.e.. undoped) type, thereby resulting in a positive-intrinsic-negative (p-i-n) type structure of the first photodiode Di. In another example, the first set of absorber layers 1104 is of first conductivity type having the first doping concentration, thereby resulting in a p-n type structure of the first photodiode D i.

[0086] The bottom layer 1102 is a substrate layer. In one embodiment, when the first photodiode Di is an indium -gallium-arsenide (InGaAs) based photodiode for absorbing shortwave IR (i.e. , having a wavelength of 1-2.5 micrometers), the bottom layer 1102 is formed with indium phosphide (InP). In another embodiment, the bottom layer 1102 is formed with one of cadmium telluride (CdTe), cadmium zinc telluride (CdZnTe), silicon (Si), and indium antimonide (InSb) based on absorption of the shortwave IR, midwave IR (i.e., having a wavelength of 3-5 micrometers), and longwave IR (i.e. , having a wavelength of 8-12 micrometers). The bottom layer 1102 may also include other layers (not shown) of the first conductivity type, with each layer having different doping levels and thicknesses. The first absorber layer 1106, and the top layer 1108 are epi-grown by way of one of a metal organic chemical vapor deposition (MOCVD) and a molecular beam epitaxy (MBE).

[0087] The first absorber layer 1106 is formed with one of InGaAs, Si, HgCdTe, and indium antimonide (InSb). The first absorber layer 1106 has a first thickness and a first doping concentration. Values of the first thickness and the first doping concentration are such that a minimum value of a total dark current of the SAL photodiode Di _a is obtained. The total dark current is identified from the test structures as illustrated in FIGS. 14A-14D. The total dark current includes a generation-recombination (GR) current component ( /. e.. a current generated by recombination of holes and electrons), a surface current component (i.e., a current generated at surfaces of a semiconductor layer), and a diffusion current component (i.e., a current generated by diffusion of holes and electrons).

[0088] The top layer 1108 is formed on top of the first set of absorber layers 1104. In one embodiment, when the first absorber layer 1106 is formed with InGaAs layer, the top layer 1108 is epi-grown on an InP substrate of the first conductivity type. The top layer 1108 is diffused with zinc (Zn) impurity to form the diffiisi on/implanted region 1110 of the second conductivity type. In another embodiment, when the first absorber layer 1106 is formed with HgCdTe, the top layer 1108 is formed with HgCdTe of the first conductivity type. In such embodiments, the top layer 1108 is implanted with arsenic (As) to form the

diffiision/implanted region 1110. The diffiision/implanted region 1110 forms an anode of the SAL photodiode Di _a .

[0089] The SAL photodiode Di _a further includes an etchstop layer 1112 and a microlens 1114. The etchstop layer 1112 allows thinning of the bottom layer 1102 for reducing an optical path of the infrared radiation IR to the first set of absorber layers 1104 and for imaging in light wavelengths that are absorbed in the bottom layer 1102. The microlens 1114 improves reception of the infrared radiation IR. The improved reception of the infrared radiation IR enables the SAL photodiode Di _a to operate efficiently in the low-light anti blooming mode in which ambient light is dim, and the time-gated imaging mode in which an exposure time is less.

[0090] FIG. 11B illustrates a structure of the first photodiode Di in accordance with another embodiment of the present invention. The first photodiode Di of FIG. 11B is implemented as a dual absorber layer (DAL) photodiode Di _b . The DAL photodiode D¾ includes the bottom layer 1102, the top layer 1108, the diffiision/implanted region 1110, the etchstop layer 1112, the microlens 1114, and a second set of absorber layers 1116. [0091] The second set of absorber layers 1116 includes second and third absorber layers 1118 and 1120 such that the second absorber layer 1118 is formed on top of the bottom layer 1102, and the third absorber layer 1120 is formed on top of the second absorber layer 1118. Similar to the first absorber layer 1106, the second and third absorber layers 1118 and 1120 are formed with one of the InGaAs, Si, HgCdTe, and InSb. Further, the second and third absorber layers 1118 and 1120 absorb one of the shortwave, midwave, and longwave IR. The second and third absorber layers 1118 and 1120 have second and third thicknesses and doping concentrations, respectively. The second doping concentration is less than the third doping concentration. Values of the second and third thicknesses and the second and third doping concentrations are such that a total dark current and a capacitance of the DAL photodiode Di _b are minimized, when a low reverse voltage is applied across the DAL photodiode Di _b .

[0092] FIG. 12A illustrates the passive imaging mode operation of the first photodiode Di (7.t\ . the SAL photodiode Di _a ) in accordance with an embodiment of the present invention. In the passive imaging mode, the SAL photodiode D i _a is operated in a zero bias or a negligible reverse bias < 0. IV. Thus, a first space charge region (SCR) 1202 having a first depth di is formed within the first absorber and top layers 1106 and 1108. The first depth di is based on the first doping concentration (i.e.. for a high value of the first depth di, the first doping concentration has a low value, and vice versa). An exposure time (i.e.. a time duration for which the SAL photodiode Di _a is exposed to the infrared radiation IR) is long in the passive imaging mode. Due to the long exposure time, a minimum dark current is required during the passive imaging mode. Since the first thickness and doping concentration are based on the identification and minimization of the total dark current, the SAL photodiode Di _a has minimal dark current and a high capacitance in the passive imaging mode.

[0093] FIG. 12B illustrates the active imaging mode operation of the first photodiode Di (i.e.. the SAL photodiode Di _a ) in accordance with an embodiment of the present invention. In the active imaging mode, the SAL photodiode Di _a is operated in a photoconductive mode. An exposure time is short (typically in the order of nano seconds) in the active imaging mode. Due to the short exposure time, a high capacitance, and a low responsivity of the SAL photodiode Di _a (i.e.. a low efficiency of the SAL photodiode Di _a to generate the first output current L based on the received infrared radiation) result in high power consumption in the first input cell 202a and low signal -to-noise ratio. During the integration of the first output current L by the CTIA integrator 402 in the time-gated imaging mode, a readout noise is proportional to a capacitance (which is high) of the SAL photodiode Di _a . This results in further degradation in the signal-to-noise ratio. To reduce the capacitance, increase the responsivity, and reduce readout noise, a large reverse voltage (typically greater than 5 volts) is applied across the SAL photodiode Di _a . Due to the application of the large reverse voltage, a second SCR 1204 having a second depth di is formed within the first absorber and top layers 1106 and 1108. The second depth di is larger the first depth di due to the application of the large reverse voltage. Due to the second SCR 1204, a capacitance of the SAL photodiode Di _a is reduced and the responsivity of the SAL photodiode Di _a is increased, resulting in low- power and high signal-to-noise in the active imaging mode.

[0094] The SAL photodiode Di _a operates in the passive imaging mode to generate the first output current L with the minimal dark current, and in the active imaging mode to generate the first output current L with increased responsivity and lower capacitance as compared to the passive imaging mode. Thus, the SAL photodiode Di _a has optimum performance in both the active and passive imaging modes.

[0095] FIG. 13A illustrates the passive imaging mode operation of the first photodiode Di (i.e.. the DAL photodiode Di _b ) in accordance with another embodiment of the present invention. The DAL photodiode D» is operated with an application of negligible reverse bias in the passive imaging mode. The second and third doping concentrations are such that a third SCR 1302 having a third depth d3 is formed within the top and third absorber layers 1108 and 1120 such that the third SCR 1302 almost touches an interface between the second and third absorber layers 1118 and 1120. The third SCR 1302 ensures that the DAL photodiode Du has a low dark current, and as a result, a high capacitance in the passive imaging mode.

[0096] FIG. 13B illustrates the active imaging mode operation of the first photodiode Di (i.e.. the DAL photodiode Di _b ) in accordance with another embodiment of the present invention. The DAL photodiode Di _b is operated in the photoconductive mode in the active imaging mode. The second and third doping concentrations and an application of a low reverse voltage (less than 5 volts) ensure that a fourth SCR 1304 having a fourth depth d ₄ is formed within the top and second and third absorber layers 1108 and 1118 and 1120, respectively. Thus, due to the application of the low reverse voltage, the fourth depth d ₄ is larger than the third depth d ₃ and hence a capacitance of the DAL photodiode Du is reduced and a responsivity of the DAL photodiode Di _b is increased in the active imaging mode.

[0097] The DAL photodiode Di _b operates in the passive imaging mode to generate the first output current L with minimum dark current, and in the active imaging mode to generate the first output current L with increased responsivity and lower capacitance based on the application of the low reverse voltage, than the passive imaging mode. Thus, the DAL photodiode Di _b has optimum performance in both the active and passive imaging modes.

[0098] Although the SAL and DAL photodiodes Di _a and D¾ are disclosed, the present invention is not limited to it. It will be apparent to a person skilled in the art that the first photodiode Di may further be implemented as a multiple absorber layer photodiode, i.e., a set of absorber layers of the first photodiode Di may include more than two absorber layers.

[0099] FIG. 14A illustrates a top view of a type-l test structure 1400 in accordance with an embodiment of the present invention. The type-l test structure 1400 includes a first set of test photodiodes of which first and second test photodiodes Tn and T n are shown.

[0100] The first test photodiode T 1 1 includes a first active region (/. e. , an SCR region) l402a, a first guard ring l402b, a first neutral region (i.e., a non-SCR region) l404a, and a second neutral region l404b. The first active region l402a has a first volume, a first area, and a first perimeter. Similarly, the second test photodiode Tn includes a second active region l406a, a second guard ring l406b, a third neutral region l408a, and a fourth neutral region l408b. The second active region l406a has a second volume, a second area, and a second perimeter. In one embodiment, the first and second perimeters are equal, and the second volume is greater than the first volume. Further, when depths (not shown) of the first and second active regions l402a and l406a are equal, the second area is greater than the first area. In another embodiment, the first and second perimeters are equal, and the second volume is less than the first volume. Due to the type-l test structure 1400, the dark current components of the dark current are mainly the a) GR and b) surface current components. The GR dark current densities vary with the first and second volumes, or first and second areas when the depths are equal, while the surface current densities remain approximately constant.

[0101] FIG. 14B illustrates a top view of a type-2 test structure 1410 in accordance with an embodiment of the present invention. The type-2 test structure 1410 includes a second set of test photodiodes of which third and fourth test photodiodes T21 and T22 are shown.

[0102] The third test photodiode T21 includes a third active region 1412 and a fifth neutral region 1414. The third active region 1412 has a third volume, a third area, and a third perimeter. Similarly, the fourth test photodiode T22 includes a fourth active region 1416 and a sixth neutral region 1418. The fourth active region 1416 has a fourth volume, a fourth area, and a fourth perimeter. In one embodiment, the third and fourth perimeters are equal, and the third volume is greater than the fourth volume. Further, when depths (not shown) of the third and fourth active regions 1412 and 1416 are equal, the third area is greater than the fourth area. In another embodiment, the third and fourth perimeters are equal, and the third volume is less than the fourth volume. Due to the type-2 test structure 1410 without any guard rings, the dark current components of the dark current are mainly the a) GR and diffusion current components, and b) the surface current components. The GR and diffusion current densities vary with the third and fourth volumes or the third and fourth areas when the depths are equal, while the surface current densities remain approximately constant.

[0103] FIG. 14C illustrates a top view of a type-3 test structure 1420 in accordance with an embodiment of the present invention. The type-3 test structure 1420 includes a first set of test photodiode arrays of which first and second test photodiode arrays T ₃₁ and T ₃₂ are shown.

[0104] The first test photodiode array T31 includes the first test photodiode Tn. Each photodiode of the first test photodiode array T ₃₁ has equal volume and perimeter of the active region (such as the first active region l402a). The anode of each photodiode of the first test photodiode array T31 are shorted together to give a first common anode, and the cathode of each photodiode of the first test photodiode array T ₃₁ are shorted together to give a first common cathode. The dark current of the first test photodiode array T ₃₁ is measured across the first common anode and the first common cathode. The second test photodiode array T3 ₂ includes the second test photodiode T ₁₂ . Each photodiode of the second test photodiode array T ₃₂ has equal volume and perimeter of the active region (such as the second active region l406a). The anode of each photodiode of the second test photodiode array T3 ₂ are shorted together to give a second common anode, and the cathode of each photodiode of the second test photodiode array T ₃₂ are shorted together to give a second common cathode. The dark current of the second test photodiode array T3 ₂ is measured across the second common anode and the second common cathode. The dark current components in the type-3 test structure 1420 are identified from mainly the GR and surface current components for a photodiode array, such as the first or second test photodiode array T31 or T3 ₂ , as compared to the identification of the dark current components from a single photodiode in the type-l test structure 1400. The GR dark current densities vary with the first and second volumes of the first and second test photodiodes Tn and T1 ₂ , respectively, or the first and second areas when the depths are equal, while the surface current densities remain approximately constant. Any additional dark current component is attributed to fabrication issues arising during the formation of the first set of test photodiode arrays.

[0105] FIG. 14D illustrates a top view of a type-4 test structure 1422 in accordance with an embodiment of the present invention. The type-4 test structure 1422 includes a second set of test photodiode arrays of which third and fourth test photodiode arrays T41 and T42 are shown. [0106] The third test photodiode array T _4i includes the third test photodiode T ₂₁ . Each photodiode of the third test photodiode array T ₄₁ has equal volume and perimeter of the active region (such as the third active region 1412). The anode of each photodiode of the third test photodiode array T ₄₁ are shorted together to give a third common anode, and the cathode of each photodiode of the third test photodiode array T ₄₁ are shorted together to give a third common cathode. The dark current of the third test photodiode array T41 is measured across the third common anode and the third common cathode. The fourth test photodiode array T ₄₂ includes the fourth test photodiode T ₂₂ . Each photodiode in the fourth test photodiode array T4 ₂ has equal volume and perimeter of the active region (such as the fourth active region 1416). The anode of each photodiode of the fourth test photodiode array T ₄₂ are shorted together to give a fourth common anode, and the cathode of each photodiode of the fourth test photodiode array T4 ₂ are shorted together to give a fourth common cathode. The dark current of the fourth test photodiode array T ₄₂ is measured across the fourth common anode and the fourth common cathode. The dark current components in the type -4 test structure 1422 are identified from the GR, diffusion, and surface current components for a photodiode array as compared to the identification of the dark current components from a single photodiode in the type -2 test structure 1410. The GR and diffusion dark current densities vary with the third and fourth volumes of the third and fourth test photodiodes T ₂₁ and T ₂₂ , respectively, while the surface current densities remain approximately constant. Any additional dark current component is attributed to fabrication issues arising during the formation of the second set of test photodiode arrays.

[0107] For determining the first thickness and doping concentration (i.e.. for manufacturing the SAL photodiode Di _a ), a set of manufacturing runs is performed for fabricating each of the type-l through type-4 test structures 1400-1422. In one example, in a set of‘N’ manufacturing runs, each test photodiode of the type-l through type-4 test structures 1400-1422 is fabricated such that each test photodiode is a single absorber layer photodiode and a first absorber layer of each test photodiode has a fourth, fifth, sixth, ...., (N ^th + 3) thicknesses and a fourth, fifth, sixth, ... ., (N ^th + 3) doping concentrations, respectively. After the set of manufacturing runs, a suitable current measuring and processing circuitry (not shown) determines the dark current components as well as the total dark current for all N runs. The SAL photodiode Di _a is manufactured such that the first thickness and doping concentration are equal to the thickness and doping concentration of the run which gives minimum total dark current. The minimum total dark current is the desired optimized dark current. [0108] For determining the second and third thicknesses and doping concentrations ( i. e.. for manufacturing the DAL photodiode Di _b ), another set of manufacturing runs is performed for fabricating each of the type-l through type-4 test structures 1400-1422. In one example, in a set of M manufacturing runs, each test photodiode of the type- 1 through type-4 test structures 1400-1422 is fabricated such that each test photodiode is a dual absorber layer photodiode and has second and third absorber layers having (N ^th + 4), (N ^th + 5), ... , (2*M ^th + N ^th + 3) thicknesses and (N ^th + 4), (N ^th + 5), ... , (2*M ^th + N ^th + 3) doping concentrations, respectively. After the set of manufacturing runs, a suitable current and capacitance measuring and processing circuitry (not shown) determines the dark current components and the total dark current under negligible reverse bias, and a photodiode capacitance under a low reverse bias for all M runs. The DAL photodiode D» is manufactured such that the second and third thicknesses and doping concentrations are equal to the thicknesses and doping concentrations of the run which gives minimum total dark current and test photodiode capacitance, respectively.

[0109] As the first through third thicknesses and doping concentrations are based on the optimized dark current of the type-l, type-2, type-3, and type-4 test structures 1400, 1410, 1420, and 1422, respectively, the dark current of the first photodiode Di (i.e., the SAL and DAL photodiodes Di _a and Di _b ) in the passive imaging mode is less. Further, in the active imaging mode, due to the second and third doping concentrations and the application of the low reverse voltage across the first photodiode Di (i.e., the DAL photodiode Di _b ), the capacitance and responsivity of the first photodiode Di are reduced and increased, respectively, as compared to the capacitance and responsivity of conventional photodiodes. Thus, the photodetector 100 has a reduced response time, an increased photon detection efficiency by way of the increased responsivity, and a lower readout noise as compared to conventional photodetectors in which a capacitance and a responsivity of a photodiode is unchanged in the active and passive imaging modes. The photodetector 100 hence has an optimum performance in both the active and passive imaging modes. Further, due to the reduced capacitance and increased responsivity in the active imaging mode, the photodiode array 102 is suitable to be bonded with a current-mode ROIC (not shown) having resistive transimpedance amplifier (TIA) and threshold comparator based input cells for laser detection and ranging (LADAR).

[0110] While various embodiments of the present invention have been illustrated and described, it will be clear that the present invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the present invention, as described in the claims.