MULTI-PHASE CLOCK DIVIDER CIRCUIT - PANASONIC CORPORATION

Title:

MULTI-PHASE CLOCK DIVIDER CIRCUIT

Document Type and Number:

WIPO Patent Application WO/2010/004747

Kind Code:

A1

Abstract:

Provided is a divider circuit for a multi-phase clock signal which can assure a sufficient data latch time even for a multi-phase clock signal having a high frequency. For example, the divider circuit includes: a main latch circuit (10) which generates an inverse data signal by using two clock signals out of the 8-phase clock signals; and a sub latch circuit (20) which acquires the inverse data signal as a common data signal by using the 8-phase clock signals as a trigger.

Inventors:

YAMAHIRA, Seiji (())

Application Number:

JP2009/003191

Publication Date:

January 14, 2010

Filing Date:

July 08, 2009

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Assignee:

PANASONIC CORPORATION (1006, Oaza Kadoma Kadoma-sh, Osaka 01, 〒5718501, JP)
パナソニック株式会社 (〒01 大阪府門真市大字門真１００６番地 Osaka, 〒5718501, JP)

International Classes:

H03K23/54; G06F1/06; G06F1/12; H03K5/15; H03K23/42

Attorney, Agent or Firm:

MAEDA, Hiroshi et al. (Osaka-Marubeni Bldg, 5-7Hommachi 2-chome, Chuo-ku, Osaka-sh, Osaka 53, 〒5410053, JP)

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