Title:
MULTI-STAGE LOGIC RECONFIGURATION DEVICE AND RECONFIGURATION METHOD, LOGIC CIRCUIT CORRECTION DEVICE, AND RECONFIGURABLE MULTI-STAGE LOGIC CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2007/113964
Kind Code:
A1
Abstract:
Provided is a multi-stage logic circuit reconfiguration device capable of easily reconfiguring
a multi-stage logic circuit which can perform logic modification and requires
a small mounting area and a low power consumption. For example, when reconfiguring
a multi-stage logic circuit accompanying a logic modification for deleting
an output vector F(b) of a target logic function F(X) for an input vector (b), uncorrected
pq elements are successively selected starting with the pq element (EG)
nearest to the output side. Here, among the pq elements of input side as compared
to the pq elements which have been selected previously, those elements having
an output value for the input vector (b) equal to the output value for the input
variable (X) other than the input vector (b) are all considered to have been corrected
and not selected. The output value for the selected input vector (b) is rewritten
into an invalid value.
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Inventors:
SASAO TSUTOMU (JP)
Application Number:
PCT/JP2007/054100
Publication Date:
October 11, 2007
Filing Date:
March 02, 2007
Export Citation:
Assignee:
KYUSHU INST TECHNOLOGY (JP)
SASAO TSUTOMU (JP)
SASAO TSUTOMU (JP)
International Classes:
G06F7/00
Foreign References:
| JPH064266A | 1994-01-14 | |||
| JPH09297776A | 1997-11-18 |
Other References:
QIN H. ET AL.: "Implementation of LPM address generators on FPGAs", RECONFIGURABLE COMPUTING: ARCHITECTURE AND APPLICATIONS. SECOND INTERNATIONAL WORKSHOP, ARC 2006. (LECTURE NOTES IN COMPUTER SCIENCE), vol. 3985, 3 March 2006 (2006-03-03), pages 170 - 181, XP019037601
SASAO T.: "Design Methods for Multiple-Valued Input Address Generators", 36TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL'06), May 2006 (2006-05-01), pages 1 - 10, XP010917777
NAKAHARA H. ET AL.: "LUT Cascade o Mochiita CAM Emulator ni tsuite", IEICE TECHNICAL REPORT, vol. 106, no. 548 VLD2006-134, March 2007 (2007-03-01), pages 91 - 96, XP003017794
NAKAHARA H. ET AL.: "A CAM Emulator Using Look-UP Table Cascades", 14TH RECONFIGURABLE ARCHITECTURE WORKSHOP RAW 2007, March 2007 (2007-03-01), pages RAW-9-PAPER-2, XP003017795
SASAO T.: "Design Methods for Multiple-Valued Input Address Generators", 36TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL'06), May 2006 (2006-05-01), pages 1 - 10, XP010917777
NAKAHARA H. ET AL.: "LUT Cascade o Mochiita CAM Emulator ni tsuite", IEICE TECHNICAL REPORT, vol. 106, no. 548 VLD2006-134, March 2007 (2007-03-01), pages 91 - 96, XP003017794
NAKAHARA H. ET AL.: "A CAM Emulator Using Look-UP Table Cascades", 14TH RECONFIGURABLE ARCHITECTURE WORKSHOP RAW 2007, March 2007 (2007-03-01), pages RAW-9-PAPER-2, XP003017795
Attorney, Agent or Firm:
ISHIDA, Kazuto (Kitakyushu Science and Research Park Collaboration Center 2-1, Hibikino, Wakamatsu-ku,Kitakyushu-sh, Fukuoka 35, JP)
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