CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application claims priority to U.S. Provisional Patent Application Serial No. 62/195,776 filed July 22, 2015, titled, "MULTI- VOLTAGE TO ISOLATED LOGIC LEVEL TRIGGER," the disclosure of which is fully incorporated herein by reference for all purposes. DESCRIPTION OF THE INVENTION

Field Of the Invention:

[0002] Various systems may benefit from interfaces for handling multiple types of inputs. For example, a device with a trigger input from an external device may benefit from an isolated logic level trigger that is capable of addressing multiple types and values of voltage.

Background of the Invention:

[0003] Some products have a need for input signals to activate, deactivate, or otherwise trigger certain features. For example, a secure solid state drive (SSD) may support an external trigger input that is configured to trigger a full drive erase function, a sanitize function, or a key erase function.

[0004] In certain cases, the SSD may use 3.3V or 1.8V logic. However, the external trigger signal provided by an associated device, such as a computer, may not be compatible with the 3.3V or 1.8V logic of the SSD. Moreover, there are a wide variety of different incompatible approaches.

SUMMARY OF THE INVENTION

[0005] According to certain embodiments, an apparatus can include an input configured to receive an external trigger input signal having a trigger input voltage. The apparatus can also include circuitry configured to automatically adjust the trigger input voltage to a value configured to be compatible with a provided attached system. A working range of the trigger input voltage can exceed a compatible working range of the provided attached system.

[0006] In certain embodiments, an apparatus can include means for receiving an external trigger input signal having a trigger input voltage. The apparatus can also include means for automatically adjusting the trigger input voltage to a value configured to be compatible with a provided attached system. A working range of the trigger input voltage can exceed a compatible working range of the provided attached system.

[0007] A method, according to certain embodiments, can include receiving, in a hardware device, an external trigger input signal having a trigger input voltage. The method can also include automatically adjusting, by the hardware device, the trigger input voltage to a value configured to be compatible with a provided attached system. A working range of the trigger input voltage can exceed a compatible working range of the provided attached system.

BRIEF DESCRIPTION OF THE DRAWINGS:

[0008] For proper understanding of the invention, reference should be made to the accompanying drawings, wherein:

[0009] Figure 1 illustrates a circuit diagram of an apparatus according to certain embodiments.

[0010] Figure 2 illustrates a method according to certain embodiments.

[0011] Figure 3 illustrates a circuit diagram of an apparatus in several variations according to certain embodiments.

[0012] Figure 4 illustrates an alternative for an external ground trigger selection section, according to certain embodiments.

[0013] Figure 5 illustrates a voltage translation circuit according to certain embodiments. DETAILED DESCRIPTION:

[0014] Certain embodiments can provide voltage translation from an external trigger input to an input suitable for a device, such as a solid state drive (SSD). Certain embodiments can provide such voltage without advance knowledge of the voltage characteristics of the external trigger input. For example, in different situations a different type or amount of translation may be needed.

[0015] Thus, in general, certain embodiments may translate an unknown externally applied positive or negative voltage to a value that an attached system can sense and react to without worries about over-voltage damage or voltage adjustment. Furthermore, certain embodiments may provide a robust method to translate a wide ranging input signal to a second voltage or logic level.

[0016] Figure 1 illustrates a circuit diagram of an apparatus according to certain embodiments. As shown in Figure 1, an apparatus can include an input INI, IN2 configured to receive an external trigger input signal having a trigger input voltage VT. The apparatus can also include circuitry configured to automatically adjust the trigger input voltage to a value configured to be compatible with an attached system. The attached system can be any desired attached system, such as an SSD, attached to the right of the circuit.

[0017] The circuitry can include a rectification section 110. The rectification section 1 10 can be configured to adjust, for the trigger input voltage, at least one of a polarity or a current type. In some cases, the rectification section 110 can address both the polarity, such as negative or positive, and the type, such as alternating current or direct current. The rectification section 110 of the circuitry can include a full wave bridge rectifier, which can be made of diodes D1, D2, D3, D4. [0018] The full wave bridge can adjust the input signal by selectively routing the input signals INI and IN2 so that the + point on the circuit diagram is always positive with respect to the - input on the circuit diagram. For example, the bridge can reverse the destination of the INI and IN2 signals so that the + point is always of the same polarity and the - point is always of the same polarity. The current can be routed as well by whichever pair of diodes in the bridge conduct, and routing may always present a positive voltage at the + point on the circuit diagram with respect to the - point on the circuit diagram. Thus, adjusting current can be accomplished by steering INI or IN2 to the same points regardless of the polarity of the voltage on INI or IN2.

[0019] Similarly, the full wave bridge can adjust the current type by rectifying alternating current into direct current. Optionally, a capacitor or other circuit element can be added to ensure that an output of the full wave bridge more closely approximates DC, although such approximation is not needed in certain embodiments.

[0020] The external trigger input signal can exhibit a trigger input voltage VT of any voltage from, for example, -50 V to +50 V. The external trigger input signal may exhibit a trigger input voltage VT as little as, for example, +/- 2.5 V. The minimum may depend on diode drop in the rectification section 1 10, as well as on other aspects of the circuit design. Thus, in a particular example, Dl, D2, D3, and D4 can form a low drop small signal full wave bridge to allow trigger input voltage VT from about +/- 2.5 V to about +/- 50 V (or any other desired voltage) to generate a trigger signal.

[0021] The circuitry can optionally include an external ground trigger selection section 130 arranged to enable generation of an output trigger signal responsive to grounding of either input INI or IN2, whenever an active external ground trigger selection signal is received, as will be further explained below. For example, the external ground trigger selection section 130 can include a switch Ql configured to enable the output trigger signal responsive to grounding of either input INI or IN2 whenever the external ground trigger selection signal is low.

[0022] A purpose of the external ground trigger selection section 130 may be to allow either input INI or IN2 to cause a trigger if grounded. Low true signals may be desired. Thus, the external ground trigger selection section 130 may allow both INI or IN2 to cause a trigger signal if one or the other is grounded.

[0023] The external ground trigger selection signal can go to a low level with respect to VCC2 to turn on a PFET Ql . When Ql turns on, Ql can apply VCC2 to a current limiting diode D6 via a diode D5. When D6 is forward biased, current can flow through an LED in PMl and then out Dl or D3 to INI or IN2 or both depending on which is low. If neither INI nor IN2 is at a low level, then there will be no current in the LED of PMl, and because there is no current flowing, the trigger signal will not occur. Thus, current may flow through the LED in PMl to generate a trigger signal.

[0024] Ql could also be replaced by an inverter, or other digital logic, or a buffer. A FET, however, uses no power when the external ground trigger selection signal is in a high state, but an inverter or buffer would always burn a small amount of power.

[0025] In summary, the state of the external ground trigger selection signal can change the operation of the circuit to allow the user to use low true logic, grounding of INI or IN2, at INI or IN2 or even both grounded at the same time. This principle can also allow the generation of a trigger signal from an external source that has two different conditions that may be needed in alternative configurations to generate the trigger signal.

[0026] VCC1 for PMl can be different from VCC2 for Ql . VCC1 for PMl may be the desired VCC that the logic on the right side, fed by the trigger signal, can use for its main supply voltage. VCC2 for Ql could be any value. If VCC2 for Ql is too high, then the logic that generates the external ground trigger selection signal may need translation to be able to turn on and turn off FET Ql . FET Ql is a P channel FET in this particular example, but could be an N channel FET or a logic buffer or a logic buffer with an open collector/drain output. Ql can be provided as a way to generate the current needed to turn on the LED in PM1 whenever INI or IN2 are grounded.

[0027] As shown in Figure 1, the external ground trigger selection section 130 may receive the external ground trigger selection signal across a resistor R3, and at the gate of a switch Ql . Resistor R3 may keep the external ground trigger selection signal low if the external ground trigger selection signal is left floating, and thus in the absence of a trigger selection signal connected thereto creates a default condition allowing the user to use low true logic, i.e. grounding of INI or IN2, to initiate the trigger signal. In an alternative embodiment, resistor R3 may be connected to VCC2 of switch Ql resulting in default of requiring an active signal on INI or IN2 to initiate the trigger signal. Switch Ql can be a p-channel field-effect transistor (P- FET) switch for the external ground trigger selection option. VCC2 can be the digital supply used in the digital system. Diode D5 can prevent reverse current from entering the body diode of Ql, when trigger input voltage VT is actively provided.

[0028] The external ground trigger selection signal may provide a nonisolated external ground trigger option. A one or high signal may indicate that the option is off. A zero or low signal may indicate the option is on, and may enable the output trigger signal responsive to grounding of either input INI or IN2, when selected.

[0029] The circuit can have at least two modes of operation. In one mode, D5 and Ql may not be needed. In this mode, a high level on INI in relation to IN2, or vice versa, can generate a trigger signal. For example, in this mode, INI can be 2.5V or greater and IN2 can be ground to generate a trigger signal. Alternatively, IN2 could be 2.5V or greater and INI can be grounded to generate a trigger signal.

[0030] In a second mode of operation, the circuit can allow the user to ground either INI or IN2 to cause the trigger signal. In the second mode of operation, the current needed to turn on the LED inside relay PMl can come from D5 and Ql, responsive to the external ground trigger selection signal, or from another circuit (see, for example, Figures 3 and 4).

[0031] Driving the external ground trigger selection signal to a high level can enable the first mode. Alternatively, driving the external ground trigger selection signal to a low level, or leaving the trigger selection signal floating, can enable the second mode.

[0032] In the second mode of operation, the external ground trigger selection signal can be driven low to turn on the Ql P-channel FET. When Ql is on, Ql can supply a current to PMl, but only when either INI, or IN2, or both are grounded. If both INI and IN2 are floating or at a higher voltage potential than VCC2, PMl will not trigger because current will not flow through the LED in PMl .

[0033] In the second mode of operation, ground may be the same on both sides of isolation section 120, as shown. There are alternatives to this use of the same ground if, for example, another relay PM2 were used to supply VCC2 to D6, as shown in Figure 4. In this fashion, PM2 would interface the external ground trigger selection signal so that it can use an isolated VCC2.

[0034] An alternative approach would be to eliminate Ql and R3 and let the external ground trigger selection signal directly drive D5. Other approaches or embodiments are also permitted.

[0035] The circuitry can also include an isolation section 120 configured to isolate the trigger input voltage VT from the attached system. The isolation section 120 can include a relay PMl configured to selectively provide the output trigger signal in response to an output of the rectification section 1 10. [0036] Relay PM1 can be a solid state relay, such as a photoMOS relay. This device can be a single device that may include an LED that illuminates a pair of photo sensitive/triggered MOSFETs. The two MOSFETs in PM1 can form the switch shown in the circuit. A photo diode can similarly work for PM1 if a light emitting diode (LED) is supplied to illuminate the photo- diode. For example, PM1 could also be constructed with individual photo FETs and/or photodiodes and an LED to turn on the photo FETs or photodiode. Other implementations are also permitted.

[0037] Thus, relay PM1 can be a photoMOS relay which advantageously acts to optically isolate and filter the VT trigger input signal. PM1 can receive VCCl via resistor Rl at a first output lead, where resistor Rl can be an optional current limit for the output trigger signal provided at the second output lead of relay PM1. VCCl is the voltage compatible with the attached device, preferably provided from the attached device. Furthermore, the second output lead of relay PM1 can be attached to a first end resistor R2, with the second end of resistor R2 connected to a common potential or ground of the attached device, which can keep the output trigger signal low until a valid external trigger input signal is detected. There is no requirement that the common potential of the attached device be the same as the common potential of external ground trigger selection signal, and the common potentials may be totally isolated from each other without exceeding the scope. The output trigger signal can provide an isolated and translated logic level trigger signal. For example, a 0 or low output trigger signal can indicate that no VT trigger input is detected. Alternatively, a 1 or high signal can indicate that the output trigger signal is generated. Advantageously, the high signal is voltage compatible with the attached device, since VCCl of the attached device is utilized for the generation of the output trigger signal.

[0038] The circuitry can also include a current limiting diode D6 between the rectification section 1 10 and the isolation section 120. D6 can be a current limiting diode selected to limit current into PM1 under all trigger input voltage conditions.

[0039] In view of the above, the isolation section 120 can include a first side (shown to the left of PM1) electrically connected to the rectification section 110 and a second side (shown to the right of PM1) electrically connected to the attached system, in which the first side can be electrically isolated from the second side. In the embodiment shown a first lead of the first side of PM1 is coupled to the positive output of the rectification section 110, optionally via current limiting diode D6, and a second lead of the first side of PM1 is coupled to the return of the rectification section 1 10.

[0040] In view of the above, certain embodiments can provide circuitry configured to automatically adjust a trigger input voltage to a value configured to be compatible with a provided attached system. This circuitry can include the isolation section 120 as well as optionally the rectification section 1 10 and further optionally the current limiting diode D6. This circuitry can optionally further include Rl and R2, as explained above.

[0041] Figure 2 illustrates a method according to certain embodiments.

[0042] As shown in Figure 2, a method can include, at 210, receiving an external trigger input signal having a trigger input voltage. The method can also include, at 220, automatically adjusting the trigger input voltage to a value configured to be compatible with an attached system. For example, the automatic adjustment can include adjusting, for the trigger input voltage, at least one of a polarity or a current type. The current type may be, for example, DC or AC. This adjustment can be in addition to adjusting a voltage level of the trigger input voltage.

[0043] The automatic adjusting can include, at 222, full wave rectifying. The method can also include, at 230, selectively enabling an external ground trigger. [0044] The method can also include, at 224, isolating the trigger input voltage from the attached system. The method can further include, at 226, providing a compatible input signal in response to an output of circuitry for performing the adjusting at 220. The compatible input signal may be compatible, for example, in terms of having an appropriate voltage, current type, polarity, or the like to be used by the attached system. For example, if the attached system requires a 3.3 V or l .8 V voltage level, circuitry can be configured to supply the compatible input signal respectively at a 3.3 V or 1.8 V voltage level.

[0045] The method can include, at 223, limiting current between the adjusting and the isolating. The isolating can involve providing a first side electrically connected to circuitry for performing the adjusting at 220 and a second side electrically connected to the attached system, wherein the first side is electrically isolated from the second side.

[0046] Various embodiments may have a variety of features. For example, the voltage for the external trigger input signal (VT) can be any voltage from +/- (2.5 V to 50 V) or any other desired voltage. The circuit can adjust to the trigger input voltage automatically and can translate the input voltage to a value determined by the VCC of the attached system.

[0047] In certain embodiments, the polarity of the external trigger input can be automatically adjusted by a full wave bridge, such as a small signal full wave bridge. Thus, the trigger input signal VT, can be positive, negative, DC or AC.

[0048] In certain embodiments, the bridge can be created from small diodes, as opposed to big bulky rectifier diodes. The diodes in the bridge can, alternatively, be replaced with the body/drain diode of a MOSFET in an ideal diode type circuit. This would allow another circuit to turn on the associated FET to eliminate the drop of the diode. This may effectively lower the minimum operation voltage from +/- 2.5V to near 0 V. [0049] The relay PMl can provide opto-isolation. Thus, the trigger input signal need not share the same ground reference as the logic in the attached device.

[0050] The trigger input signal may not require current limiting. The circuit can include a constant current diode that automatically limits the input current to a pre-selected maximum limit. The constant current diode can permit the circuit to operate over a very wide voltage range.

[0051] Certain embodiments may eliminate the chance of accidental triggering of the circuit by floating pins or noise bursts. The relay PMl may be configured to require a current to flow for a period of time before the LED will illuminate and generate the output trigger signal.

[0052] The photoMOS relay PMl can provide automatic filtering of the trigger input signal VT to account for possible bouncing contacts. The filtering can come from the amount of time that the trigger input signal needs to remain applied before the LED in the photoMOS relay builds up enough charge to turn on the FET inside the photomos relay. The filtering time can be adjusted to longer or shorter durations by selecting a current limiting diode D6 with a higher or lower pass current or by selecting a different IR LED/photo-detector device.

[0053] In certain embodiments, the circuit may have an option to generate the trigger signal by externally grounding either or both INI or IN2 inputs. It is not necessary to ground both INI or IN2 inputs. For example, it may be adequate that they are sufficiently low in relation to VCC2.

[0054] There can be various implementations of certain embodiments. For example, the current limiting diode can be made using a junction gate field- effect transistor (JFET) with an appropriately selected gate/source short current (I _D ss)- The gate and source of the JFET can be connected together to create a current limiting diode. The photoMOS relay PMl can be made from an infrared (IR) light emitting diode (LED) and a high speed photo detector/switch.

[0055] Figure 3 illustrates a circuit diagram of an apparatus in several variations according to certain embodiments. As shown in Figure 3, the circuit can include a rectification section 110, an isolation section 120, and an external ground trigger selection section 130, as shown in Figure 1. Other similar parts can also be provided, as shown in Figure 1. Figure 3 also shows several further options.

[0056] For example, as shown at the left of Figure 3, there can be multiple options for the input voltage VT. The input voltage can, from left to right, be an alternating current source, a DC source with INI grounded, or a DC source with IN2 grounded. As shown in Figure 3, the bridge in rectification section 1 10 can route INI to the + terminal of the bridge when INI is greater than IN2 and can route IN2 to the + terminal of the bridge when IN2 is greater than INI .

[0057] Additionally, as shown at the top of Figure 3, there can be multiple options for the external ground trigger selection section 130. The bottom option shown in Figure 3 is the same as shown in Figure 1. The middle option omits Ql and instead provides an amplifier Bl arranged to amplify and/or buffer the external ground trigger selection signal. In this case, diode D5 can prevent reverse current from entering the output of amplifier B l when VT is driving the trigger input voltage.

[0058] The top option can omit Ql and Bl and instead the external ground trigger selection signal can be directly applied through D5. In this case, diode D5 can prevent reverse current from flowing into the external ground trigger selection signal source when VT is driving the trigger input voltage.

[0059] In the bottom and middle options, VCC2 does not need to be the same as VCC1, although they can be the same, if desired. VCC1 can be the digital supply used in the attached digital system. VCC2 can be used as a source of LED current to turn on the LED in PM1 when in the second mode of operation, as described above.

[0060] The ground reference for the side of the circuit toward the attached system can be independent from the ground reference for the side of the circuit toward the external ground trigger selection signal. Thus, the ground references can be different on either side of PM1. Additionally, while the ground reference for R3 is shown as the same as being the same as the ground reference for R2, in certain embodiments these two right side ground references can be different from one another. For example, in certain embodiments the ground reference for R3 can be the same as the left side ground reference or may also be different from the left side ground reference.

[0061] The external ground trigger selection signal can be configured such that low or zero value of the external ground trigger selection signal provides that the option is on, whereas one or high value of the external ground trigger selection signal indicates that the external ground trigger selection option is disabled. Alternatively, the external ground trigger selection signal can be configured such that low or zero value of the external ground trigger selection signal provides that the option is disabled, whereas one or high value of the external ground trigger selection signal indicates that the external ground trigger selection option is enabled.

[0062] Figure 4 illustrates an alternative for an external ground trigger selection section 130, according to certain embodiments. As shown in Figure 4, an external ground trigger selection section 130 can be designed to increase isolation between the left and right sides of the circuit. For example, another photoMOS relay PM2 can be provided, for example, to avoid electrical interaction between the left and right sides of the circuit. Relay PM2 can be configured to provide VCC2 to D5 when the external ground trigger selection signal goes sufficiently below VCCl, such as when the external ground trigger selection signal is brought to a right side ground value. In this embodiment, D5 can prevent reverse current from affecting PM2. In certain embodiments, D5 can be omitted.

[0063] Figure 5 illustrates a voltage translation circuit according to certain embodiments. As shown in Figure 5, an input voltage INI can be applied to an input of current-limiting diode Dl . Diode Dl can limit the current to maximum current II . Resistor Rl provided between diode Dl and ground can provide a translated voltage Vt, where the value in volts of voltage Vt is determined by the value in amps of the maximum current II and the value in ohms of resistor Rl . Thus, the output of the current limiting diode Dl can be configured to provide voltage Vt, which is controlled by the maximum current II of the current limiting diode Dl and the resistance of the resistor Rl . The translated voltage Vt can be provided to an attached system.

[0064] In Figures 1 and 3-5, various part numbers are shown. These part numbers are merely illustrative of a particular example, and should not be taken as limiting the scope of the invention. Additionally, the input voltage in certain embodiments is described as a trigger voltage. Nevertheless, other embodiments may apply to voltages that have other functions than triggering. Consequently, the above-described circuits may be broadly applied to many voltage translation or voltage conditioning scenarios without being limited to the examples set forth above. Other input voltages may be digital logic levels, sensors outputs, a line configured to drive a motor or similar equipment, or the like.

[0065] Certain embodiments may have various benefits and/or advantages. For example, in certain embodiments a device may be constructed from a small number of physical components, which may permit ease of manufacture.

[0066] One having ordinary skill in the art will readily understand that the invention, as discussed above, may be practiced with steps in a different order, and/or with hardware elements in configurations which are different than those which are disclosed. Therefore, although the invention has been described based upon these disclosed embodiments, it would be apparent to those of skill in the art that certain modifications, variations, and alternative constructions would be apparent, while remaining within the spirit and scope of the invention. In order to determine the metes and bounds of the invention, therefore, reference should be made to the appended claims.