TECHNICAL FIELD

Embodiments presented herein relate to a method, a digital pre-distorter, a computer program, and a computer program product for operating the digital pre-distorter for an access node.

BACKGROUND

For a wideband High-Power Amplifier (HPA) with Instantaneous Bandwidth (IBW) of, e.g., l Gigahertz (GHz) or above, it has been observed that traditional Lookup Table (LUT) based methods for linearization are excessively costly because of higher sample rate requirements. It has been observed that even with higher sample rates, LUT based methods for linearization are unable to reach the desired Adjacent Channel Leakage Ratio (ACLR) performance. Separate Digital Predistortion (S-DPD), which is also known as frequency selective Digital Predistortion (DPD), treats each linearization region separately. S-DPD not only offers low sample rate operations but also can reach desired ACLR performance levels.

The basic idea of S-DPD is to formulate a multivariate Generalized Memory Polynomial (GMP) or just Memory Polynomial (MP) for each linearization region and estimate corresponding coefficients independently. Typically, each linearization region covers a transmission frequency band. As such, the terms linearization region and frequency band are used interchangeably herein. After estimating the coefficients for the linearization regions, a portion of each of the S-DPD polynomials can be quantized to a multidimensional LUT. This is usually done by forming either a uniform or non-uniform multidimensional grid of points over the range of inputs, followed by evaluation of the S-DPD polynomials at the grid points. These evaluated points are stored as LUT outputs for each combination of inputs. Using the multidimensional LUT for the S-DPD actuator (or DPD forward calculation) makes it much faster and economical compared to evaluating the polynomial. This approach is known as hybrid LUTs (hereinafter denoted H-LUTs) and has proven a cost-effective solution for multiband implementation (see, e.g., Christophe Quindroit, Naveen Naraharisetti, Patrick Roblin, Shahin Gheitanchi, Volker Mauer, Mike Fitton, “FPGA Implementation of Orthogonal 2D Digital Predistortion System for Concurrent Dual- Band Power Amplifiers Based on Time-Division Multiplexing”, IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 6l, NO. 12, December 2013, p. 4591-4599). For instance, a triple band system will have a 3- dimensional H-LUT for each of its bands.

As the number of bands increases beyond two, there is an inherent problem with the above-mentioned H-LUTs. The memory requirements grow exponentially and make implementation costly. For B bands with M memory taps and K bins per band case, for each separate DPD the total memory requirements in the H-LUT would be M ^. K ^B . Previous attempts to replace all multivariate monomials with powers of additive terms to reduce a multidimensional problem to a single dimension one and significantly reduced memory requirements, however, suffer from performance degradation.

Hence, there is still a need for an improved multiband wideband DPD.

SUMMARY

An object of embodiments herein is to address the above issues and provide a DPD for an access node that does not suffer from the above issues, or at least where the above issues are reduced or mitigated.

According to a first aspect there is presented a method for operating a DPD for an access node. The method comprises receiving a plurality of input signals, each from a respective frequency band, wherein each signal is of memory order M. The method comprises, for each frequency band l = 1, ... , B of the frequency bands, generating a plurality of pre-distorted signals for the frequency band l based on the plurality of input signals coming from all the B frequency bands and using LUTs, according to which there is one LUT structure with LUT-based transforms per each combination of frequency band l = 1 , ... ,B and memory order m = 0, ... , M, wherein each of the LUT structures comprises combinations of LUTs of at most dimension B — q, where 1 < q < B. The method comprises, for each frequency band l = 1, . ., B of the frequency bands, combining the plurality of pre-distorted signals for the frequency band to provide a combined pre-distorted signal for the frequency band.

According to a second aspect there is presented a DPD for an access node. The DPD comprises processing circuitry. The processing circuitry being is to cause the DPD to receive a plurality of input signals, each from a respective frequency band, wherein each signal is of memory order M. The processing circuitry being is to cause the DPD to, for each frequency band l = 1, ... , B of the frequency bands, generate a plurality of pre-distorted signals for the frequency band l based on the plurality of input signals coming from all the B frequency bands and using LUTs, according to which there is one LUT structure with LUT-based transforms per each combination of frequency band l = 1 and memory order m = 0, ... , M, wherein each of the LUT structures comprises combinations of LUTs of at most dimension B — q, where 1 < q < B. The processing circuitry being is to cause the DPD to, for each frequency band l = 1, ... , B of the frequency bands, combine the plurality of pre-distorted signals for the frequency band to provide a combined pre-distorted signal for the frequency band.

According to a third aspect there is presented a DPD for an access node. The DPD comprises a receive module configured to receive a plurality of input signals, each from a respective frequency band, wherein each signal is of memory order M. The DPD comprises a generate module configured to, for each frequency band l = 1 , . . ,B of the frequency bands, generate a plurality of pre-distorted signals for the frequency band l based on the plurality of input signals coming from all the B frequency bands and using Look-Up Tables, LUTs, according to which there is one LUT structure with LUT-based transforms per each combination of frequency band l = 1, ... , B and memory order m = 0, ... , M, wherein each of the LUT structures comprises combinations of LUTs of at most dimension B — q, where 1 < q < B. The DPD comprises a combine module configured to, for each frequency band l = 1, ... , B of the frequency bands, combine the plurality of pre-distorted signals for the frequency band to provide a combined pre-distorted signal for the frequency band. According to a fourth aspect there is presented a computer program for operating a DPD for an access node, the computer program comprising computer program code which, when run on a DPD, causes the DPD to perform a method according to the first aspect.

According to a fifth aspect there is presented a computer program product comprising a computer program according to the fourth aspect and a computer readable storage medium on which the computer program is stored. The computer readable storage medium could be a non-transitory computer readable storage medium. Advantageously, these aspects enable the multidimensional problem to be reduced to a single dimension one and enables a significant reduction in memory requirements, without suffering from performance degradation. Advantageously, these aspects minimize the memory requirement associated with multi-dimensional H-LUTs whilst keeping the performance the same as for multidimensional H-LUTs. Other objectives, features and advantages of the enclosed embodiments will be apparent from the following detailed disclosure, from the attached dependent claims as well as from the drawings. Generally, all terms used in the claims are to be interpreted according to their ordinary meaning in the technical field, unless explicitly defined otherwise herein. All references to "a/an/the element, apparatus, component, means, module, step, etc." are to be interpreted openly as referring to at least one instance of the element, apparatus, component, means, module, step, etc., unless explicitly stated otherwise. The steps of any method disclosed herein do not have to be performed in the exact order disclosed, unless explicitly stated. BRIEF DESCRIPTION OF THE DRAWINGS The inventive concept is now described, by way of example, with reference to the accompanying drawings, in which: Fig.1 illustrates a radio node that includes a typical S-DPD; Fig.2 illustrates an exemplary H -LUT based on a memory polynomial architecture for the S-DPD of Fig.1; Fig.3 illustrates an example of the H-LUT of Fig.2 in which there is a single H-LUT for a triple band case without memory taps; Figs.4 and 5 are flowcharts of methods for constructing a new basis function ^^ according to an embodiment; Figs.6, 7, 8, and 15 illustrate a radio node that includes DPDs in accordance with embodiments of the present disclosure; Figs.9 and 13 illustrate H-LUT structures and corresponding S-DPD actuator architectures in accordance with embodiments of the present disclosure; Figs.10, 11, 12, and 14 illustrate the structure of H-LUTs in accordance with embodiments of the present disclosure; Fig.16 is a flowchart of methods according to embodiments; Fig.17 is a schematic diagram showing functional units of a DPD according to an embodiment; Fig.18 is a schematic diagram showing functional modules of a DPD according to an embodiment; and Fig.19 shows one example of a computer program product comprising computer readable storage medium according to an embodiment. DETAILED DESCRIPTION The inventive concept will now be described more fully hereinafter with reference to the accompanying drawings, in which certain embodiments of the inventive concept are shown. This inventive concept may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. Like numbers refer to like elements throughout the description. Any step or feature illustrated by dashed lines should be regarded as optional. As noted above there is still a need for an improved multiband wideband DPD. The embodiments disclosed herein therefore relate to mechanisms for operating a DPD for an access node. In order to obtain such mechanisms there is provided a DPD, a method performed by the DPD, a computer program product comprising code, for example in the form of a computer program, that when run on a DPD, causes the DPD to perform the method.

Typical DPD architectures require fi-dimension LUTs to support B frequency bands. Instead of B -dimension LUTs, one proposed DPD architecture utilizes several (B — q)-dimension LUTs, where q > 1. One goal of the herein disclosed embodiments is to construct a mathematical equivalent of the multi-dimensional DPD architectures using a change of basis technique that supports ( B — q)-dimension LUTs. As a result, the proposed DPD architectures perform the same as the multi-dimensional DPD architectures whilst reducing the dimension requirements of the DPD, resulting in lower memory requirements of the DPD. Additionally, each of the ( B — q) -dimension LUTs is independent from one another and hence can be implemented in parallel. One proposed DPD architecture reduces the dimension even further and only uses several one-dimensional LUTs.

Before describing embodiments of the present disclosure, it is beneficial to first describe an S-DPD. In this regard, Fig. 1 illustrates a radio node 100 that includes a DPD system 102 that uses an S-DPD architecture. As illustrated, the DPD system 102 includes multiple S-DPD actuators 104-1 through 104-B for B respective frequency bands (bi, ..., bB), where B is greater than or equal to 2. As discussed below in detail, each S-DPD actuator 104-I (for the 1-th frequency band) receives input signals (x1, ..., XB) (i.e., complex baseband input signals) for the B frequency bands and generates a predistorted signal for the 1-th frequency band based on the received input signals (x1, ..., XB) and a S-DPD actuator mechanism (e.g., memory polynomial or LUT scheme). In this example, the predistorted signals for the B frequency bands are processed by a radio unit 106 of the radio unit 100 to provide a radio frequency (RF) signal for transmission. Specifically, in this example, the predistorted signals for the B frequency bands are digitally upconverted by a digital upconverter 108, converted to analog by an RF digital-to-analog converter (DAC) 110, and amplified by a power amplifier (PA) 112.

As will be appreciated by those of skill in the art, the S-DPD actuators 104-1 through 104-B are trained by a DPD adaptor 114 based on the input signals (x1, ..., XB) and feedback signals for the B frequency bands received via a radio transmit observation receiver (TOR) 116. In this example, the TOR 116 includes an RF analog-to-digital converter (ADC) 118 coupled to an output of the PA 112 via a coupler 120 and a bandpass filter bank 122 that filters the output of the RF ADC 118 to provide the feedback signals (i.e., complex baseband feedback signals) for the B frequency bands. Note that both the radio front end 106 and the TOR 116 may include additional or alternative component that are not illustrated in Figure 1, as will be appreciated by those of ordinary skill in the art.

The operation of the S-DPD actuators 104-1 through 104-B is described below in terms of a memory polynomial (MP); however, one can easily extend the formulation for different variants of Volterra series such as a Generalized Memory Polynomial (GMP). Let us use x ₁ (n) to represent input signals (i.e., input samples), where l e (1, B ) represents the frequency band index. The output signal (i.e., output samples) from the l -th S-DPD 104-I is denoted by z _l (n). Note that n refers to a time-index. The maximum non-linear order of the S-DPD 104-I is denoted by P. Memory taps are denoted by the set with Q The cardinality of Q is M + 1. The output from the S-DPD actuator 104-I can be written as in Equation (1).

Here, refers to the S-DPD coefficients and , with the restriction and Equation (1) captures that the non-linear modelling of the inverse of the PA 112 (i.e., the predistortion) can be performed by considering the current and past samples. Past samples are included because of memory effects inherent in electronic devices. The nonlinearity of the PA 112 creates intermodulation frequencies and that is modelled by the B multiplicative terms and exponents p _b in Equation (1). When memory and non-linearities are both absent, Equation (1) becomes simpler i.e., Please note that there are B S-DPD actuators 104-1 through 104-B, and the description of the 1-th S-DPD actuator 104-I is applicable of the S-DPD actuators 104-1 through 104-B. It is also possible to use generalized memory polynomial as presented in Equation (1a) where epresents the cross-memory taps and ^ When ^ Equation (1a) is a memory polynomial. The herein disclosed embodiments are applicable also for different variants of the Volterra series and the herein disclosed embodiments can be extended to other variants of the Volterra series. Therefore, the herein disclosed embodiments will be described using only the memory polynomial to improve readability. As known to those of ordinary skill in the art, the DPD adaptor 114 can use the least square or other adaptive methods to identify S-DPD coefficients. In the S-DPD actuators 104-1 through 104-B, one can use either polynomial based approach as in Equation (1) or use variants of a LUT based approach as in Equation (1a) or as described below. There are several LUT based approaches that can be possible. One option is to use a traditional LUT both in both the DPD adaptor 114 and the S-DPD actuators 104-1 through 104-B. This technique is referred to as a multi-dimensional LUT based approach. However, this technique is cumbersome when there are more than two frequency bands (i.e., when B>2), especially in the S-DPD actuators 104-1 through 104-B because of the excessive amount of memory required for storing multi- dimensional LUTs. Here, a H-LUT approach is considered, which is best suitable for the multiband case. The H-LUT architecture for the S-DPD actuator 104-l is illustrated at 200 in Fig. 2. As can be seen from Fig.2, Equation (1) is precomputed at various points of the complete range of input signals and the results are stored in the dynamic memory of the hardware; hence, the S-DPD actuator 104-l requires a lower number of computations at runtime. As shown in Fig. 2, at 200 there are M+1 H-LUTs for the S-DPD actuator 104-I, each considering B -inputs that are and assuming the range of is divided into K parts. The division can be done taking statistical distribution of into consideration, like using usual companding methods such as, e.g., A-law or Mu- law used to compress a large dynamic range to more practical limits, or can be done uniformly in which case the size of each interval would b The size of each H-LUT is K ^B , and there are M + 1 H-LUTs corresponding to the memory taps for each Z-th band. Fig. 3 at 300 illustrates an example of the H-LUT architecture of Fig- 2 in which there is a single H-LUT 310 for a triple band case without memory taps (i.e., M=o).

Proposed S-DPD architectures

Next will be disclosed proposed modifications to the S-DPD architecture. As noted above, B dimension H-LUTs are needed to support B frequency bands. One goal of the proposed modification is to reduce the dimension of the H-LUT without causing any performance degradation. Specifically, with reference again to Fig. 2, part of the basis function, S, is to be restructured in such a way so that a new basis function, denoted S, operates on lower dimension input address entries.

Two non-limiting illustrative examples are provided to how such a lower dimension basis function can be constructed. As the skilled person would appreciate, these examples can be extended to multiband cases by induction. The examples assume a dual frequency band case where x1 and x2 are input signals. Here, x1 and x2 are column vectors with length If the length is less than this value, the system will be underdetermined.

Example 1: Without memory and for P = 3, the S-DPD output for the l:th band can be expressed as in Equation (Cia).

Here z1 is the S-DPD output (column vector) for frequency band 1 and vector length L. According to quarter square method, multiplication of two real number can be written as:

Therefore, the S-DPD output can be rewritten substituting Equation (Cib) in Equation (Cia) as follows: it follows that where refers to a column vector of length L where all the entries are one. The new lower dimension basis function can then be expressed as: which is mathematically equivalent to S

Example 2: When P = 4, the S-DPD output for the 1-th band can be expressed (using Equation (l)) as:

Using the same analogy as above: In Equations (C2b) and (C2c) two different types of replacement for | and were used so that these two terms are distinguishable during the adaptation and do not face ill condition problems. Therefore, the new lower dimension basis function can be expressed as:

In the above two examples, operates on one-dimension inputs (that is, either or linear combination of them) whilst S operates on two-dimension inputs (e.g., the product of |x ₁ | and |x ₂ |)· Using the above-mentioned examples it is possible to show that lower dimension basis functions can be constructed for B frequency bands and non-linear order P.

Design criteria for lower dimension basis function

One goal of the herein disclosed embodiments is to structure the generation of the new lower dimension basis functions in a way so that the memory requirement of the DPD is reduced when implemented with LUTs. Using the second example, the new lower basis function can be rewritten as follows:

The S-DPD outpu where β represents a new set of S-DPD coefficients for the new basis function, and where S Further: where With reference to the above two examples, design criteria for the DPD can be set as follows.

For the same power terms, such as two different types of the new terms are needed to adapt them correctly and yield unique solutions. A different set of weights can be used with ( to compensate and ₅ where can be any real number. For example, in the case of the Example 2, it is possible to use to compensate U whereas it is possible to use compensate | So, for B frequency bands, to replace p power terms, a different set of weights can be used and use to replace corresponding terms.

The same address entry terms can be stored together to reduce memory requirements. As an example, the terms can be stored in the same H-LUT. Therefore, when designing different terms, the number of possible weight sets could be restricted.

Following the above criteria, higher dimension terms can be traded with lower dimension terms. Next it will be demonstrated that the lower dimension basis function does not face divergence during the adaptation. Assume therefore that the new basis function is a linear transformation of the original basis function i.e., S = SR, where R is a relationship matrix and where (. ) ^_1 refers to inverse or pseudoinverse. R is also known as the change of basis matrix or transition matrix in the literature. If R is a full rank matrix then with the goal to minimize . Two conditions need to be fulfilled: Firstly, that R is a full rank matrix i.e., the determinant of R is not zero, det(i?) ¹ 0. This condition ensures that the new basis function S consists of linear independent terms. Secondly, that satisfies a threshold, or tolerance, limit. By selecting a correct tolerance limit it can be ensured that the new basis function S does not create ill condition problems in the adaptation.

One example of how the new basis function S can be constructed is illustrated in the flowcharts 400 and 500 of Fig. 4 and Fig. 5. The calculation of the weights starts with the generation of random test vectors of length L and for each of B frequency bands with This is referred to as Step l in Fig. 4. In Step 2 of

Fig. 4 these test vectors are used to construct the original basis function matrix S. The number of terms used in the basis function S depends on the maximum non-linear order and memory taps of the DPD and those terms can be identified using Equation (1). Step 3 of Fig. 4 is elaborated in Fig. 5 which provides new basis function S. In Step 4 of Fig. 4 it is checked whether the new basis function S satisfies the two conditions disclosed above. Finally, the new basis function S is stored.

There are four steps in Fig. 5. In Step 1 random weight vectors for B frequency bands are generated. A maximum of U ^. B weights are needed, where it can be shown that

U Here, U represents the number of terms with order P — 1 in the S-

DPD equation. Since the same weights are reused to replace terms from order 2 to P — 2, the maximum number of weights to replace terms is needed only for order P — 1. In Step 2 terms in S that are to be replaced are identified. The terms that were identified to be replaced are ordered according to the order of those terms. For example, for the triple-band case the order 4 group consists of the terms | in 5 that are to be replaced. In Step 3 the same group multiplicative terms are converted with their weighted summation magnitude. Weights generated in Step 2 of Fig. 5 are used. For example, the terms is replaced by Similarly, the term is replaced Different weights i.e., are used for Usage of different weights ensures that the new basis function S satisfies the condition that is a full rank matrix. Additionally or alternatively, the weights might be assigned different preconditions to avoid an ill-conditioned optimization problem.

Steps 2 and 3 of Fig. 5 are then repeated again but for order 5. Terms with order 5 e.g., are replaced for the triple-band example. According to one design goal, the same weighted summation of magnitude should be used as many times as possible. Therefore, weights are to be used again and the term is replaced by the term · Reusing the same weights enables the number of LUTs to be reduced. Again, the term will be replaced by the term ( and so on. The term requires three-dimension LUTs whereas the new generated term needs one-dimension LUTs. Steps 2 and 3 of Fig. 5 are then repeated again until all the terms that are to be replaced by their weighted summation magnitude. All the new terms are stored in the new basis function S.

Proposed architectures for DPDs using H-LUTs

Once the new basis function is constructed according to the above, the new basis function can be used to set up the LUTs in the S-DPD architecture. As mentioned earlier, the terms in the new basis function determine address entries in the LUTs and hence one LUT is needed for all the terms with the same address entry. For example, one LUT can be used to represent both the term and the term since both terms have the same address entry, which is Setting the LUTs is an offline mechanism and a design parameter. Therefore, the whole procedure presented above is outside the scope of the actual S-DPD architecture.

Three S-DPD architectures are proposed using H-LUTs. In all three architectures, the S-DPD actuator remains the same, whereas the S-DPD adaptor functionality is different in the three architectures. In the S-DPD architecture 600 of Fig. 6, the S- DPD adaptor uses new constructed basis function S, as determined as part of the basis function construction illustrated at reference numeral 610, and estimates the S- DPD coefficients b which are used in the S-DPD actuator as disclosed below. This architecture uses lower dimension basis functions in the adaptation. The actuator uses H-LUTs derived from the lower dimension basis functions. The working mechanism of the H-LUTs will be disclosed below. In the S-DPD architecture 700 of

Fig. 7, the S-DPD adaptor 114 uses the basis function S which is passed through the relationship matrix R as determined as part of the basis function construction illustrated at reference numeral 710. As a result, the S-DPD adaptor of the architecture in Fig. 7 still estimates the S-DPD coefficients b and the rest remains the same as in Fig. 6. This architecture uses a H-LUT actuator derived from the lower dimension basis functions. The adaptor uses the original higher dimension basis functions. In the S-DPD architecture 800 of Fig. 8, the S-DPD adaptor uses the basis function S and the S-DPD adaptor estimates the DPD coefficients α. These coefficients are passed through the relationship matrix R and b are used in the S- DPD actuator where b = Rα, as illustrated at reference numeral 820. In Fig. 8 the S- DPD actuator and the S-DPD adaptor are the same as in Fig. 7, and the basis function construction is illustrated at reference numeral 810. Nevertheless, in Fig. 8 the S- DPD coefficients are estimated first using the original higher dimension basis functions. Later they are modified using the relationship matrix.

Proposed modifications to actuator One purpose of the proposed S-DPD architectures is to use lower dimension H-LUTs in the actuator. Next will be disclosed two H-LUT architectures considering the new basis functions. First is disclosed how (B — q) -dimension H-LUTs can be constructed and used. Then it is disclosed how one-dimension H-LUT can be constructed and used. (B — q) -dimension H-LUTs and S-DPD architectures

One goal of the proposed S-DPD architectures is to reduce the size, or number of address entries, of the H-LUT. For B frequency bands the proposed actuator comprises LUTs which require maximum B — q address entries, where q > 1. In general terms, there are three main components in the H-LUT architecture. Below these components are also called a first set of LUTs, a second set of LUTs, and a third set of LUTs.

As shown above, it is possible to express S-DPD output as: which comprises several lower dimension H-LUTs. Here H-LUT address entry determines the dimension of the H- LUT. For instance, needs one-dimension H-LUTs whilst needs two-dimension H-LUTs.

Several H-LUTs with maximum B — q dimensional input address entry, q =

(1, 2, ... , B — 2} are to be used. When q = B — 1 there will only be one-dimension H- LUTs which is disclosed separately. The proposed B — q dimension H-LUTs and corresponding S-DPD actuator is shown in Fig. 9. In Fig. 9 is illustrated at 900 a proposed B — q dimension H-LUT structure and corresponding S-DPD actuator architecture, and where the first and the last H-LUTs are illustrated at reference numerals 910-1 and 910-2, respectively. Circles with “+” denote addition and circles with “x” denote multiplication. Here H-LUT for m = 0 only considers current input signals coming from B frequency bands. Similarly, H-LUT for m = M considers the M: th previous input signals coming from B frequency bands. The skilled person understands how Fig. 9 can be extended with several cross-memory taps for generalized memory polynomial as mentioned earlier. One advantage of this approach compared is that the output from the H-LUTs are added instead of being multiplied. As such, the proposed H-LUTs and corresponding S-DPD architectures significantly reduce the computational cost in the actuator.

H-LUTs for individual frequency bands

The first components (i.e., the first set of LUTs) are hereinafter denoted H-LUT individual frequency bands. These H-LUTs only consider one frequency band input at a time. The superscript (i) is used to denote “individual” frequency band. There are B numbers of LUTs for each memory tap in this case. The output from the HLUT_individual frequency band for the Z:th frequency band can be expressed as:

Equation (2) only considers one frequency band input when constructing the H-LUT which is further illustrated in Fig. 10. It is noted tha is included in the l:th LUT. Fig. 10 illustrates at 1000 the structure of the HLUT_individual frequency band where B numbers of LUTs, one of which is illustrated at reference numeral 1010, are needed for each memory taps. For example, for 3 frequency bands, there are three individual band H-LUTs, i.e., when the DPD does not have any memory taps. H-LUTs for (B — r) frequency bands

The second components (i.e., the second set of LUTs) are hereinafter denoted HLUT_(B-q) frequency bands to HLUT_2 frequency bands. In HLUT_(B-q) frequency bands the LUTs consider input coming from ( B — q) frequency bands out of the B frequency bands. Similarly, in HLUT_(B-q-i) frequency bands the LUTs consider input coming from (B — q — 1) frequency bands out of the B frequency bands, and so on. In this case, there are several H-LUTs from all the possible combinations of ( B — q) frequency bands out of the B frequency bands. Some of the combinations can be removed from the H-LUTs through empirical analysis.

There are r = {q, q + 1, ... , B - 2} H-LUTs in this case. One goal of the H-LUTs is to pick a subset of frequency bands to construct the basis functions. Let refer to the set of all frequency band indices. Let denote the superset containing sets of all the combinations of B — r frequency bands, or in other words a set ½ is drawn from Έ choosing B — r elements or For instance, when there are three bands, B = 3, q = l,r = 1 and B — r = 2 then

{{1, 2}, (1, 3}, {2, 3}}. When B = 4, q = i, r = l, then

{{1, 2}{1, 3}, (1, 4}, {2, 3}, {2, 4}, (3, 4}}. Using the defined set notation, the output from the B — r H-LUTs can be expressed as:

Fig. 11 illustrates at 1100 the structure of the H-LUTs for an example of triple bands, i.e., when B = 3, q = 1 and r = 1, schematically illustrating H-LUTs at reference numerals 1110-1, 1110-2, 1110-3. In this case, ( _B ^B _ _r ) numbers of LUTs for each memory tap are needed. There are thus ( _B ^B _ _r ) numbers of H-LUTs for each of B — r frequency bands H-LUTs. Each of the H-LUTs can take maximum B — q dimension input signals, hence referred to as (B — q) -dimension H-LUTs. Some of the H-LUTs can be removed through empirical analysis.

H-LUTs for weighted summation of magnitude frequency bands

The third components (i.e., the third set of LUTs) are hereinafter denoted HLUT_wsm_i to HLUT_wsm_T. Here “wsm” is short for weighted summation of magnitude. This is where dimension has been reduced. In other words, the state-of- the-art architecture uses B -dimension H-LUTs to represent these components whereas here, one-dimension H-LUT address entries using weighted summation of magnitude of the input signals are used. The number of H-LUTs and address entries depends on the DPD. These H-LUTs operate on one-dimension input signals by linearly combining all the input signals from the B frequency bands. Several HLUT_wsm blocks are used. Each of these HLUT_wsm is constructed from the weighted summation of the magnitude from all the frequency bands. The number of H-LUTs depends on the maximum non-linear order and the number of frequency bands. Assume there is T number of H-LUTs that use weighted summation of the magnitude. As disclosed above, different sets of weights are needed to adapt all the terms correctly, which leads to different types of HLUT. Let refer to the weight that is to be used for the l:th frequency band signal for the t: th H-LUT, where the weights can take any real number value. The construction of is described in Fig. 12. The output from the t: th H-LUT that uses weighted summation of magnitude can be expressed as: The structure of the wsm H-LUT is illustrated at 1200 in Fig. 12 which shows that the wsm H-LUTs, one of which is illustrated at reference numeral 1210, operate on one-dimension input signals. The resolution of the H-LUT is shown to be the same as before i.e. K, however, this can be different for different H-LUTs. Some of the H- LUTs can be removed through empirical analysis. One-dimension H-LUTs and corresponding S-DPD architectures

Next will be disclosed details of one-dimensional H-LUTs and a corresponding S- DPD actuator. The details are similar to the above disclosed ( B — q) -dimension LUTs, but with changes made to the second component, i.e., the H-LUT_(B-q) frequency bands to H-LUT_2 frequency bands. Since both the H-LUTs for individual frequency bands and the H-LUTs for weighted summation of the magnitude of all frequency bands as disclosed above operate on one-dimension input signals, these will remain unchanged in this proposed one-dimension H-LUTs. As above, these second components require ( B — q) -dimension H-LUTs and in this case the actuator contains only one-dimension H-LUTs. The details of the one-dimension LUTs are disclosed below. To capture the dependency of different frequency bands the weighted summation of the magnitude of B — r frequency bands is used. As such, each H-LUT operates on one-dimension input signals. Fig. 13 at 1300 illustrates the one-dimension H-LUTs and corresponding S-DPD actuator architecture, and where the first and the last H-LUTs are illustrated at reference numerals 1310-1 and 1310-2, respectively. Circles with “+” denote addition and circles with “x” denote multiplication. The expression for follow Equation (2) and Equation (4), respectively. In Fig. 13 the H-LUTs for m = 0 only consider the current input signals coming from B frequency bands. Similarly, the H-LUTs for m = M consider the M: th previous input signals coming from B frequency bands. The skilled person understands how Fig. 13 can be extended with several cross-memory taps for generalized memory polynomial as mentioned earlier. The expression for B — r frequency bands weighted summation of magnitude can be formulated as:

Here, the definitions of are the same as described above. The H-LUT structure for an example case of triple-band is illustrated at 1400 in Fig. 14. In this example, ( _B ^B _ _r ) numbers of H-LUTs are needed for each of B — r frequency bands H- LUTs. Fig. 14 illustrates an example where B = 3, q = 1 and r = 1, where the H-LUTs are schematically illustrated at reference numerals 1410-1, 1410-2, 1410-3. As shown in Fig. 14, each of the H-LUTs takes a maximum of one-dimension input signals. Some of the H-LUTs can be removed through empirical analysis.

Experimental results using Wideband Power Amplifier

To validate our proposed S-DPD architectures and modified basis functions, experiments were conducted using a wideband power amplifier. Three non — contiguous frequency bands were used; LTE band 3 (B3), LTE band 1 (Bi), and LTE band 7 (B7), where each frequency band has one 20MHz carrier. It is here noted that the proposed DPD architectures can support any number of frequency bands and any combination of carriers. The proposed DPD architectures were tested with 2 and 1 dimension basis functions, where 2 dimensions correspond to ( B — q)-dimension S- DPD architecture with (B = 3, q = 1; B — q = 2). For benchmark comparison, a 3- dimension S-DPD architecture which corresponds to a b-dimension problem was used. One goal of the experiments is to validate the generation of the lower dimension basis functions as mentioned above and Equations (i)-(s) were used. For all experiments, P = 6 and 5 memory taps were used. The experimental results are summarized in Table I. It can be seen that the proposed DPD architectures provide the same performance compared to the b-dimension S-DPD architecture.

Advantages and extensions From the above follows that the number of H-LUTs depends on the number of frequency bands B and the non-linear order P, and it can be shown that the that the required number of H-LUTs is for the same dimension reduction result as with a traditional S-DPD. For triple frequency bands when P = 6, 21 one-dimension H-LUTs are needed using the above proposed DPD architectures. However, the number of H-LUTs can be reduced by supporting higher dimension H-LUTs. For instance, for the same use case, it is possible to use 9 one-dimension H-LUTs or 3 two-dimension H-LUTs. Therefore, the proposed ( B — q) -dimension H-LUTs and one-dimension H-LUTs provide flexibility in the actuator design.

The operations performed by one H-LUT does not depend on operations performed by another H-LUT. Hence, the H-LUTs can be implemented in parallel. As a result, parallel computing can be taken advantage of in the actuator implementation. Due to the parallel implementation in the H-LUTs, it is also possible to make a tradeoff between the number of H-LUTs and performance. For instance, for the use case where 21 one-dimension H-LUTs are required it is possible to remove some of the H- LUTs corresponding to the higher-order terms and test the overall performance. Using empirical analysis it is possible to identify the optimal number of LUTs for the DPD which provides satisfactory performance with lower implementation cost. In this way, the number of H-LUTs can be considered as a design parameter. The herein disclosed DPD architectures can be extended to direct adaptation. For example, for a dual-band system P = 3, with M memory taps, and resolution K, direct adaptation can be realized using the following expression: where each of the tables is defined as:

Generally, where, for a LUT with K bins the tables are defined as:

The LUTs denoted by are vectors of gridpoint weights The argument of can also be considered as an index to the LUT and is a weighted summation of magnitudes of input signals.

Using the proposed generation of basis functions it is possible to set up all the required LUTs for a given number of frequency bands and given non-linear order and number of memory taps. In this case the adaptor also uses LUTs and the proposed DPD architecture is illustrated in Fig. 15. In the DPD architecture 1500 of Fig. 15 both the actuator and the adaptor use lower dimension LUTs. In Fig. 15 g refers to the grid point weights and the adaptor directly identifies those weights, and the basis function construction is illustrated at reference numeral 1510. Embodiments of methods for operating DPDs as disclosed above

Fig. 16 is a flowchart 1600 illustrating embodiments of methods for operating a DPD for an access node. The methods are performed by the DPDs as disclosed above. The methods are advantageously provided as computer programs 1920.

S102: The DPD receives a plurality of input signals. Each input signal is received from a respective frequency band. Each signal is of memory order M.

The DPD for each frequency band l = 1, ... , B of the frequency bands performs actions S104-Z and S106-Z:

S104-Z: The DPD generates a plurality of pre-distorted signals for the frequency band l based on the plurality of input signals coming from all the B frequency bands and using LUTs. According to the LUTs there is one LUT structure with LUT-based transforms per each combination of frequency band l = 1 and memory order m = 0, ... , M. Each of the LUT structures comprises combinations of LUTs of at most dimension B — q, where 1 < q < B.

S106-Z: The DPD combines the plurality of pre-distorted signals for the frequency band to provide a combined pre-distorted signal for the frequency band.

Embodiments relating to further details of operating a DPD 1700 for an access node as performed by the DPD 1700 will now be disclosed.

In some embodiments, q = B — 1.

As above, in some embodiments, the LUT-based transforms have adapted DPD coefficients b. As above, in some embodiments, the adapted DPD coefficients b are determined through training of the DPD with reference signals. In some embodiments, the grid points of the LUTs are, through training of the reference signals, adapated instead of the DPD coefficients b. In the later case the LUT structures for the DPD actuator and the adaptor are the same.

Each dimension represents a respective address entry to the LUTs. Each dimension has at least one LUT and possibly several LUTs. In particular, in some embodiments, each dimension represents a respective address entry to the LUTs.

As above, in some aspects, the transforms acts as filters that are used to filter the input signal. In particular, in some embodiments, the DPD is configured to perform action Si04a-Z as part of generating the plurality of pre-distorted signals:

Si04a-Z: The DPD transforms the plurality of input signals coming from all the B frequency bands using the LUT-based transforms. Which of the LUT-based transforms to use for transforming the plurality of input signals are determined by using the plurality of input signals as input to the LUTs.

As above, in some aspects, the LUT structures comprises a first set of LUTs, a second set of LUTs, and a third set of LUTs. Details of the first set of LUTs will now be disclosed.

In some embodiments, the LUT structures for frequency band l and memory order m comprises a first set of LUTs adapted to use as input a one-dimensional input formed by the plurality of input signals from a respective individual frequency band of the B frequency bands. As above, the LUT-based transforms of the LUTs in the first set of LUTs for frequency band l at time index n for transforming input signal x are denoted and might thus be defined as:

Details of the second set of LUTs will now be disclosed.

In some embodiments, the LUT structures for frequency band l and memory order m comprises a second set of LUTs adapted to use as input B — q down to 2 -dimensional input formed by combinations of B — q of the frequency bands down to 2 of the frequency bands, where q > B — 1. As above, the LUT-based transforms of the LUTs in the second set of LUTs for frequency band B — r, where r = {q, q + 1, ... , B — 2}, at time index n for transforming input signal x are denoted and might thus be defined as:

Details of the third set of LUTs will now be disclosed.

In some embodiments, the LUT structures for frequency band l and memory order m comprises a third set of LUTs adapted to use as input a one-dimensional input formed by weighted linear combinations of the plurality of input signals from all B frequency bands. As above, the LUT-based transforms of the t: th LUT in the third set of LUTs when q > B — 1 at time index n for transforming input signal x are denoted might thus be defined as:

As above, alternatively, the LUT-based transforms of the LUTs in the third set of LUTs for frequency band B — r at time index n for transforming input signal x when q = B — 1 are denoted and might thus be defined as:

The weighted linear combinations of the plurality of input signals might be weighted using weights As disclosed above, each set of weights might be iteratively determined. When the weights are iteratively determined, each set of weights initially comprises randomly selected real number values.

As disclosed above, it is possible to identify the optimal number of LUTs for the DPD which provides satisfactory performance with lower implementation cost using empirical analysis. Hence, in some embodiments, only a subset of all available LUTs are used when generating the plurality of pre-distorted signals, and which LUTs to be included in the subset of LUTs is determined by empirical analysis. As disclosed above, the herein disclosed DPD architectures can be extended to direct adaptation. Hence, in some embodiments, the LUTs have adapted grid points, where the grid points are identified using parameter estimation. Here both the DPD actuator and the adaptor use the same LUT structures. Fig. 17 schematically illustrates, in terms of a number of functional units, the components of a DPD 1700 according to an embodiment. Processing circuitry 1710 is provided using any combination of one or more of a suitable central processing unit (CPU), multiprocessor, microcontroller, digital signal processor (DSP), etc., capable of executing software instructions stored in a computer program product 1910 (as in Fig.19), e.g. in the form of a storage medium 1730. The processing circuitry 1710 may further be provided as at least one application specific integrated circuit (ASIC), or field programmable gate array (FPGA). Particularly, the processing circuitry 1710 is configured to cause the DPD 1700 to perform a set of operations, or steps, as disclosed above. For example, the storage medium 1730 may store the set of operations, and the processing circuitry 1710 may be configured to retrieve the set of operations from the storage medium 1730 to cause the DPD 1700 to perform the set of operations. The set of operations may be provided as a set of executable instructions. Thus the processing circuitry 1710 is thereby arranged to execute methods as herein disclosed. The storage medium 1730 may also comprise persistent storage, which, for example, can be any single one or combination of magnetic memory, optical memory, solid state memory or even remotely mounted memory. The DPD 1700 may further comprise a communications interface 1720 at least configured for communications with other entities, functions, nodes, and devices, as illustrated in some of the figures. As such the communications interface 1720 may comprise one or more transmitters and receivers, comprising analogue and digital components. The processing circuitry 1710 controls the general operation of the DPD 1700 e.g. by sending data and control signals to the communications interface 1720 and the storage medium 1730, by receiving data and reports from the communications interface 1720, and by retrieving data and instructions from the storage medium 1730. Other components, as well as the related functionality, of the DPD 1700 are omitted in order not to obscure the concepts presented herein. Fig. 18 schematically illustrates, in terms of a number of functional modules, the components of a DPD 1800 according to an embodiment. The DPD 1800 of Fig.18 comprises a number of functional modules; a receive module 1810 configured to perform step S102, a generate module 1820 configured to perform step S104-^, and a combine module 1840 configured to perform step S106-^. The DPD 1800 of Fig.18 may further comprise a number of optional functional modules, such as a transform module 1830 configured to perform step S104a-^. In general terms, each functional module 1810:1840 may in one embodiment be implemented only in hardware and in another embodiment with the help of software, i.e., the latter embodiment having computer program instructions stored on the storage medium 1730 which when run on the processing circuitry makes the DPD 1700 perform the corresponding steps mentioned above in conjunction with Fig 18. It should also be mentioned that even though the modules correspond to parts of a computer program, they do not need to be separate modules therein, but the way in which they are implemented in software is dependent on the programming language used. Preferably, one or more or all functional modules 1810:1840 may be implemented by the processing circuitry 1710, possibly in cooperation with the communications interface 1720 and/or the storage medium 1730. The processing circuitry 1710 may thus be configured to from the storage medium 1730 fetch instructions as provided by a functional module 1810:1840 and to execute these instructions, thereby performing any steps as disclosed herein. The DPD 1700, 1800 may be provided as a standalone device or as a part of at least one further device. For example, the DPD 1700, 1800 may be provided in a node of an access network Alternatively, functionality of the DPD 1700, 1800 may be distributed between at least two devices, or nodes. These at least two nodes, or devices, may either be part of the same network part (such as a radio access network or a core network) or may be spread between at least two such network parts. Thus, a first portion of the instructions performed by the DPD 1700, 1800 may be executed in a first device, and a second portion of the of the instructions performed by the DPD 1700, 1800 may be executed in a second device; the herein disclosed embodiments are not limited to any particular number of devices on which the instructions performed by the DPD 1700, 1800 may be executed. Hence, the methods according to the herein disclosed embodiments are suitable to be performed by a DPD 1700, 1800 residing in a cloud computational environment. Therefore, although a single processing circuitry 1710 is illustrated in Fig.17 the processing circuitry 1710 may be distributed among a plurality of devices, or nodes. The same applies to the functional modules 1810:1840 of Fig.18 and the computer program 1920 of Fig.19. Fig. 19 shows one example of a computer program product 1910 comprising computer readable storage medium 1930. On this computer readable storage medium 1930, a computer program 1920 can be stored, which computer program 1920 can cause the processing circuitry 1710 and thereto operatively coupled entities and devices, such as the communications interface 1720 and the storage medium 1730, to execute methods according to embodiments described herein. The computer program 1920 and/or computer program product 1910 may thus provide means for performing any steps as herein disclosed. In the example of Fig.19, the computer program product 1910 is illustrated as an optical disc, such as a CD (compact disc) or a DVD (digital versatile disc) or a Blu-Ray disc. The computer program product 1910 could also be embodied as a memory, such as a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), or an electrically erasable programmable read-only memory (EEPROM) and more particularly as a non-volatile storage medium of a device in an external memory such as a USB (Universal Serial Bus) memory or a Flash memory, such as a compact Flash memory. Thus, while the computer program 1920 is here schematically shown as a track on the depicted optical disk, the computer program 1920 can be stored in any way which is suitable for the computer program product 1910. The inventive concept has mainly been described above with reference to a few embodiments. However, as is readily appreciated by a person skilled in the art, other embodiments than the ones disclosed above are equally possible within the scope of the inventive concept, as defined by the appended patent claims.