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Title:
MULTIFUNCTIONAL AND MULTI-BIT RESISTIVE STORAGE MEMORIES
Document Type and Number:
WIPO Patent Application WO/2018/006131
Kind Code:
A1
Abstract:
A memristor device is provided, comprising a first electrode; a second electrode; a cathode metal layer disposed on a surface of the first electrode; and an active region disposed between and in electrical contact with the second electrode and the cathode metal layer, the active region comprising at least one layer of an amorphous metal oxide, wherein the amorphous metal oxide comprises doping atoms of a dopant element selected from the group consisting of aluminium, nickel, iron and chromium, and wherein when a switching voltage is applied between the first and second electrodes, the active region exhibits a resistive switching behaviour. Also provided is a method of fabricating such a memristor device.

Inventors:
SRIRAM, Sharath (7B/8 Waterside Place, Docklands, Victoria 3008, 3008, AU)
AHMED, Taimur (1/8 Florence Street, Coburg, Victoria 3058, 3058, AU)
WALIA, Sumeet (3C/8 Waterside Place, Docklands, Victoria 3008, 3008, AU)
BHASKARAN, Madhu (7B/8 Waterside Place, Docklands, Victoria 3008, 3008, AU)
Application Number:
AU2017/050699
Publication Date:
January 11, 2018
Filing Date:
July 06, 2017
Export Citation:
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Assignee:
RMIT UNIVERSITY (124 La Trobe Street, Melbourne, Victoria 3000, 3000, AU)
International Classes:
H01L45/00; G11C11/56; H01L27/24
Attorney, Agent or Firm:
PHILLIPS ORMONDE FITZPATRICK (Level 16, 333 Collins StreetMelbourne, Victoria 3000, 3000, AU)
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Claims:
Claims:

1 . A memristor device comprising:

(a) a first electrode;

(b) a second electrode;

(c) a cathode metal layer disposed on a surface of the first electrode; and

(d) an active region disposed between and in electrical contact with the second electrode and the cathode metal layer, the active region comprising at least one layer of an amorphous metal oxide, wherein the amorphous metal oxide comprises doping atoms of a dopant element selected from the group consisting of aluminium, nickel, iron and chromium, and

wherein when a switching voltage is applied between the first and second electrodes, the active region exhibits a resistive switching behaviour.

2. A memristor device according to claim 1 , wherein the at least one layer of amorphous metal oxide includes an oxide of titanium.

3. A memristor device according to claim 1 , wherein the at least one layer of amorphous metal oxide includes an oxygen deficient amorphous metal oxide.

4. A memristor device according to claim 3, wherein the oxygen deficient amorphous metal oxide includes a strontium titanate expressed by a formula

(amorphous -SrTi03-x), wherein 0.05 < x < 0.15.

5. A memristor device according to claim 1 , wherein the at least one layer of amorphous metal oxide comprises an oxygen deficient amorphous metal oxide layer and an amorphous metal oxide layer.

6. A memristor device according to claim 5, wherein the oxygen deficient amorphous metal oxide layer includes a strontium titanate expressed by a formula (amorphous -SrTi03-x), wherein 0.05 < x < 0.15, and the amorphous metal oxide layer includes a strontium titanate expressed by a formula (amorphous-SrTi03).

7. A memristor device according to claim 5, wherein each of the oxygen deficient amorphous metal oxide layer and the amorphous metal oxide layer has a thickness that falls within the range of about 1 5 nm to about 40 nm.

8. A memristor device according to claim 3, wherein the oxygen deficient amorphous metal oxide comprises doping atoms of chromium.

9. A memristor device according to claim 8, wherein the oxygen deficient amorphous metal oxide includes strontium titanate expressed by a formula

(amorphous-SrTi03-x), wherein 0.05 < x < 0.15.

10. A memristor device according to claim 8 or 9, wherein the ratio of chromium to titanium is between about 0.01 and about 0.05.

1 1 . A memristor device according to claim 1 , wherein the least one layer of an amorphous metal oxide has a thickness that falls within the range of about 15 nm to about 40 nm.

12. A memristor device according to any one of the preceding claims, wherein the cathode metal layer has a thickness that falls within the range of about 3 nm to about 12 nm.

13. A memristor device according to claim 12, wherein the cathode metal layer has a thickness that falls within the range of about 5 nm to about 10 nm.

14. A memristor device according to any one of the preceding claims, wherein the first electrode has a thickness that falls within the range of about 20 nm to about 35 nm and the second electrode has a thickness that falls within the range of about 5 nm to about 10 nm.

15. A memristor device according to any one of the preceding claims, wherein the resistive switching behaviour comprises a bipolar resistive switching (BRS) behaviour that occurs in one or both of a forward direction and a reverse direction.

16. A memristor device according to claim 15 wherein said BRS behaviour is induced via an electroforming step including a relatively high current compliance in a range of 40 to 50 μΑ.

17. A memristor device according to any one of claims 1 to 14, wherein the resistive switching behaviour comprises a complementary resistive switching (CRS) behaviour that occurs in one or both of a forward direction and a reverse direction.

18. A memristor device according to claim 17 wherein said CRS behaviour is induced via an electroforming step including a relatively low current compliance in a range of 1 to 5 μΑ.

19. A memristor device according to any one of claims 1 to 14, wherein the resistive switching behaviour comprises a peculiar complementary resistive (p-CRS) switching behaviour that occurs in one or both of a forward direction and a reverse direction.

20. A memristor device according to claim 19 wherein said p-CRS behaviour is induced via an electroforming step including a relatively moderate current compliance in a range of 5 to 10 μΑ.

21 . A method of fabricating a memristor device, the method comprising the steps of:

a) providing a first electrode;

b) providing a second electrode;

c) providing a cathode metal layer disposed on a surface of the first electrode; and

d) providing an active region disposed between and in electrical contact with the second electrode and the cathode metal layer, the active region comprising at least one layer of an amorphous metal oxide, wherein the amorphous metal oxide comprises doping atoms of a dopant element selected from the group consisting of aluminium, nickel, iron and chromium, and

wherein when a switching voltage is applied between the first and second electrodes, the active region exhibits a resistive switching behaviour.

22. A method according to claim 21 , wherein the dopant element is chromium and the ratio of chromium to titanium is between about 0.01 and about 0.05.

23. A method according to claim 21 or 22, wherein one or more of steps a) to d) is conducted at room temperature.

24. A method according to claim 21 , 22 or 23, further comprising performing an electroforming step including a relatively high current compliance in a range of 40 to 50 μΑ, for inducing a bipolar resistive switching (BRS) behaviour that occurs in one or both of a forward direction and a reverse direction.

25. A method according to claim 21 , 22 or 23, further comprising performing an electroforming step including a relatively low current compliance in a range of 1 to 5 μΑ, for inducing a complementary resistive switching (CRS) behaviour that occurs in one or both of a forward direction and a reverse direction.

26. A method according to claim 21 , 22 or 23, further comprising performing an electroforming step including a relatively moderate current compliance in a range of 5 to 1 0 μΑ, for inducing a peculiar complementary resistive (p-CRS) switching behaviour that occurs in one or both of a forward direction and a reverse direction.

27. A method of fabricating a memristor device on a substrate, the method comprising the steps of:

a) depositing a bottom electrode on a substrate;

b) depositing at least one layer of an amorphous metal oxide on the deposited bottom electrode to define an active region, wherein the amorphous metal oxide comprises doping atoms of a dopant element selected from the group consisting of aluminium, nickel, iron and chromium;

c) depositing a cathode metal layer on the at least one layer of the amorphous metal oxide; and

d) depositing a top electrode on the deposited cathode metal layer, such that the active region is disposed between, and in electrical contact with, the bottom electrode and the cathode metal layer, wherein when a switching voltage is applied between the top and bottom electrodes, the active region exhibits a resistive switching behaviour.

28. A method according to claim 27 wherein the at least one layer of amorphous metal oxide includes an oxide of titanium.

29. A method according to claim 27 wherein the at least one layer of amorphous metal oxide includes an oxygen deficient amorphous metal oxide.

30. A method according to claim 27 wherein the oxygen deficient amorphous metal oxide includes a strontium titanate expressed by a formula (amorphous- SrTi03-x), wherein 0.05 < x < 0.15.

31 . A method according to any one of claims 27 to 30, wherein the dopant element is chromium.

32. A method according to claim 31 , wherein the ratio of chromium to titanium is between about 0.01 and about 0.05.

33. A method according to any one of claims 27 to 32, wherein one or more of steps a) to d) is conducted at room temperature.

34. A method according to any one of claims 27 to 33, further comprising performing an electroforming step including a relatively high current compliance in a range of 40 to 50 μΑ for inducing bipolar resistive switching behaviour.

35. A method according to any one of claims 27 to 33, further comprising performing an electroforming step including a relatively low current compliance in a range of 1 to 5 μΑ for inducing complementary resistive switching behaviour.

36. A method according to any one of claims 27 to 33, further comprising performing an electroforming step including a relatively moderate current compliance in a range of 5 to 10 μΑ for inducing peculiar complementary resistive behaviour.

Description:
MULTIFUNCTIONAL AND MULTI-BIT RESISTIVE STORAGE MEMORIES Cross Reference to Related Application

[0001] The present invention is related to the following patent application, the disclosure of which is incorporated herein by cross reference: International PCT Patent Application No. PCT/AU2016/051 145 entitled a Memristor Device and a Method of Fabrication thereof filed on 23 November 2016.

Technical Field

[0002] The present invention relates to resistive storage memories and in particular relates to multifunctional and multi-bit resistive storage memories. The present invention has been developed for use in compatible memristive systems and will be described hereinafter with reference to this application. However, it will be appreciated that the invention is not limited to this particular field of use.

[0003] The following discussion of the background to the invention is intended to facilitate an understanding of the invention. However, it should be appreciated that the discussion is not an acknowledgement or admission that any of the material referred to was published, known or part of the common general knowledge in Australia or any other country as at the priority date of any one of the claims of this specification.

Background of Invention

[0004] Memory technologies have traditionally been used to store digital data in the form of ones and zeros. Current interest on the other hand, lies in technologies that enable analogue memories to have multiple states. This enables unprecedented high density memories and most significantly neuromorphic computing. These interests rely on the electronic state of memories being highly non-volatile with durable and cyclic switching and easy differentiation between ON/OFF states. Nanoscale resistive memories (or "memristors") satisfy many of these requirements, and are reliant on functional oxides. They are normally configured as passive two terminal metal insulated metal (MIM) devices based on functional binary and ternary metal oxides (e.g. Ti02, SrTi03). These offer a scalable, fast, non-volatile and low energy memristive performance. Their dynamic nonlinear current voltage characteristics also suggest applications in nonlinear circuit design and alternative logic architectures.

[0005] Bipolar resistive switching behaviour in these devices is treated to a combination of electronic effects at the metal/oxide interfaces and reversible redox reactions and nanoionic transport in transition metal oxide layers. These processes are triggered in the oxide upon creation of extended defect structures during an electroforming process, under high electrical gradients.

[0006] Highly nonlinear and non-volatile memristive characteristics of two- terminal capacitor-like metal insulated metal (MIM) devices based on transition metal oxides have attracted intensified research interest due to their potential for development of highly scalable memory devices. They also promise to be precursors for novel computing architectures and unconventional computing such as neuromorphic engineering.

[0007] Among transition metal oxides, strontium titanate (SirTi03; STO), the archetypal perovskite oxide has emerged as a promising candidate for a functional oxide layer in memristive MIM devices. Its self-doping tendency with oxygen vacancies subject to electrical or thermal stress can transform its electronic structure from a band insulator to a metallic conductor and facilitate electro-resistive switching suitable for two terminal memory devices. Strontium titanate has shown great potential for nanoscale resistive switching applications due to an inherent tendency of the stable perovskite structure of STO to harbour oxygen vacancy point defects and a pronounced redox activity along dislocations in the titanium oxide sub-lattice.

[0008] Resistive switching in STO based devices is generally attributed to highly localised accumulation of oxygen vacancies (i.e. nano-filaments) along extended defect structures, which result in local bypassing of the depletion layer at the metal oxide interfaces. Additionally, the defect structure of STO may be directly manipulated via doping with a donor- or acceptor-type transition metal, which can be employed to modulate the electronic structure at local (e.g. grain boundaries and point defects) and bulk levels. This can be used as a tool to engineer the arrangement and electronic/ionic transport properties of nano-filaments, and therefore, the memristive properties of STO based devices. As such, STO-based devices have a potential for high density integration as passive analog memory elements in computing architectures. Moreover, tunability of the STO structure with respect to coupled electromechanical and electro-optical effects highlights an impressive degree of freedom it can render in the design of multifunctional nonlinear devices.

[0010] Non-volatile resistive memories based on selectively doped perovskite oxides have demonstrated an immense potential for future complex neuromorphic computing and compact sequential logic applications. The present invention may provide a resistive memory device having multiple resistive switching behaviours, including bipolar, complementary and "peculiar" complementary resistive switching behaviours. The resistive memory device may comprise a single monolayer amorphous strontium titanate (a-STOx) based memory cell which has been doped with an element such as aluminium (Al), nickel (Ni), iron (Fe) or preferably chromium (Cr).

[0011] Multiple switching behaviours may be defined or induced by current compliance limits set during an initial electroforming process. The electroforming process may induce a specific switching behaviour in a memory cell.

[0012] Based on material and electrical characterization, a possible physical model is proposed herein which explains corresponding resistive switching behaviours by considering density and distribution of oxygen vacancies in a memory cell under influence of set current compliance limits. The existence of multiple distinct resistive switching behaviours in one memory device and their selection by an electric field strength may provide diverse (multi-functional) applications for the memory devices. In particular the "peculiar" complementary resistive switching behaviour may facilitate tri-level storage per unit cell, to realize an ultra-high density data storage unit.

[0013] However, high processing temperatures and non-CMOS compatible substrates typically employed in fabricating STO-based memristor devices can create a barrier to commercialisation of these devices.

[0014] The present invention may provide a resistive memory device and a method of fabrication thereof, which may address or substantially ameliorate at least some deficiencies of the prior art or at least provide an alternative.

Summary of Invention

[0015] According to a first aspect of the present invention, there is provided a memristor device comprising: (a) a first electrode; (b) a second electrode; (c) a cathode metal layer disposed on a surface of the first electrode; and (d) an active region disposed between and in electrical contact with the second electrode and the cathode metal layer, the active region comprising at least one layer of an amorphous metal oxide, wherein the amorphous metal oxide comprises doping atoms of a dopant element selected from the group consisting of aluminium, nickel, iron and chromium, and wherein when a switching voltage is applied between the first and second electrodes, the active region exhibits a resistive switching behaviour.

[0016] The at least one layer of amorphous metal oxide may include an oxide of titanium. The at least one layer of amorphous metal oxide may include an oxygen deficient amorphous metal oxide. The oxygen deficient amorphous metal oxide may include strontium titanate expressed by a formula (amorphous -SrTi03-x), wherein 0.05 < x < 0.15.

[0017] The at least one layer of amorphous metal oxide may comprise an oxygen deficient amorphous metal oxide layer and an amorphous metal oxide layer. The oxygen deficient amorphous metal oxide layer may include strontium titanate expressed by a formula (amorphous -SrTi03-x), wherein 0.05 < x < 0.15, and the amorphous metal oxide layer may include strontium titanate expressed by a formula (amorphous-SrTi03). Each of the oxygen deficient amorphous metal oxide layer and the amorphous metal oxide layer may have a thickness that falls within the range of about 15 nm to about 40 nm.

[0018] The oxygen deficient amorphous metal oxide may comprise doping atoms of chromium. The oxygen deficient amorphous metal oxide may include strontium titanate expressed by a formula (amorphous-SrTi03-x), wherein 0.05 < x < 0.15. The ratio of chromium to titanium may be between about 0.01 and about 0.05.

[0019] The at least one layer of an amorphous metal oxide may have a thickness that falls within the range of about 15 nm to about 40 nm. The cathode metal layer may have a thickness that falls within the range of about 3 nm to about 1 2 nm. The cathode metal layer may have a thickness that falls within the range of about 5 nm to about 1 0 nm. The first electrode may have a thickness that falls within the range of about 20 nm to about 35 nm and the second electrode may have a thickness that falls within the range of about 5 nm to about 1 0 nm.

[0020] The resistive switching behaviour may comprise a bipolar resistive switching (BRS) behaviour that occurs in one or both of a forward direction and a reverse direction. BRS behaviour may be induced via an electroforming step including a relatively high current compliance in a range of 40 to 50 μΑ.

[0021] The resistive switching behaviour may comprise a complementary resistive switching (CRS) behaviour that occurs in one or both of a forward direction and a reverse direction. CRS behaviour may be induced via an electroforming step including a relatively low current compliance in a range of 1 to 5 μΑ.

[0022] The resistive switching behaviour may comprise a peculiar complementary resistive (p-CRS) switching behaviour that occurs in one or both of a forward direction and a reverse direction. p-CRS behaviour may be induced via an electroforming step including a relatively moderate current compliance in a range of

5 to 10 μΑ.

[0023] According to a second aspect of the present invention, there is provided a method of fabricating a memristor device, the method comprising the steps of: a) providing a first electrode; b) providing a second electrode; c) providing a cathode metal layer disposed on a surface of the first electrode; and d) providing an active region disposed between and in electrical contact with the second electrode and the cathode metal layer, the active region comprising at least one layer of an amorphous metal oxide, wherein the amorphous metal oxide comprises doping atoms of a dopant element selected from the group consisting of aluminium, nickel, iron and chromium, and wherein when a switching voltage is applied between the first and second electrodes, the active region exhibits a resistive switching behaviour.

[0024] The dopant element may be chromium and the ratio of chromium to titanium may be between about 0.01 and about 0.05. One or more of steps a) to d) may be conducted at room temperature.

[0025] The method may further comprise performing an electroforming step including a relatively high current compliance in a range of 40 to 50 μΑ, for inducing a bipolar resistive switching (BRS) behaviour that occurs in one or both of a forward direction and a reverse direction.

[0026] The method may further comprise performing an electroforming step including a relatively low current compliance in a range of 1 to 5 μΑ, for inducing a complementary resistive switching (CRS) behaviour that occurs in one or both of a forward direction and a reverse direction.

[0027] The method may further comprise performing an electroforming step including a relatively moderate current compliance in a range of 5 to 1 0 μΑ, for inducing a peculiar complementary resistive (p-CRS) switching behaviour that occurs in one or both of a forward direction and a reverse direction.

[0028] According to a third aspect of the present invention, there is provided a method of fabricating a memristor device on a substrate, the method comprising the steps of: a) depositing a bottom electrode on a substrate; b) depositing at least one layer of an amorphous metal oxide on the deposited bottom electrode to define an active region, wherein the amorphous metal oxide comprises doping atoms of a dopant element selected from the group consisting of aluminium, nickel, iron and chromium; c) depositing a cathode metal layer on the at least one layer of the amorphous metal oxide; and d) depositing a top electrode on the deposited cathode metal layer, such that the active region is disposed between, and in electrical contact with, the bottom electrode and the cathode metal layer, wherein when a switching voltage is applied between the top and bottom electrodes, the active region exhibits a resistive switching behaviour.

[0029] The at least one layer of amorphous metal oxide may include an oxide of titanium. The at least one layer of amorphous metal oxide may include an oxygen deficient amorphous metal oxide. The oxygen deficient amorphous metal oxide may include a strontium titanate expressed by a formula (amorphous-SrTi03-x), wherein 0.05 < x < 0.15.

[0030] The dopant element may be chromium. The ratio of chromium to titanium is between about 0.01 and about 0.05. One or more of steps a) to d) may be conducted at room temperature.

[0031] The method may further comprise performing an electroforming step including a relatively high current compliance in a range of 40 to 50 μΑ for inducing bipolar resistive switching behaviour.

[0032] The method may further comprise performing an electroforming step including a relatively low current compliance in a range of 1 to 5 μΑ for inducing complementary resistive switching behaviour.

[0033] The method may further comprise performing an electroforming step including a relatively moderate current compliance in a range of 5 to 10 μΑ for inducing peculiar complementary resistive behaviour. Brief Description of the Drawings

[0034] Notwithstanding any other forms which may fall within the scope of the present invention, preferred embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which:

[0035] Figure 1 (a) shows a schematic diagram of a memory cell. Figure 1 (b) shows a cross-sectional view of the memory cell and its layers.

[0036] Figure 2(a) shows a waveform of applied electroforming voltage. Figure 2(b) shows a waveform of applied voltage sweep during memory operation. Figure 2(c) shows an l-V plot of an electroforming sweep for inducing complementary resistive switching in an MIM device. Figure 2(d) shows an l-V plot of an electroforming sweep for inducing "peculiar" complementary resistive switching in a MIM device. Figure 2(e) shows an l-V plot of an electroforming sweep for inducing bipolar resistive switching in an MIM device.

[0037] Figure 3 shows characteristics of complementary resistive switching (CRS) behaviour in an MIM device.

[0038] Figure 4(a) shows characteristics of peculiar complementary resistive switching (p-CRS) of an MIM device on a semi-logarithmic scale. Figure 4(b) shows retention performance at room temperature for 10 5 seconds. Figure 4(c) shows the pulsed endurance characteristics of the p-CRS regime for 4000 switching cycles.

[0039] Figure 5(a) shows characteristics of bipolar resistive switching (BRS) behaviour in an MIM device represented on a semi-logarithmic scale. Figure 5(b) shows retention performance at room temperature for 10 5 seconds at a VREAD of +0.2 V. Figure 5(c) shows the endurance of the MIM device for 1 0 4 cycles. For each switching cycle V RE SET of +3 V, V S ET of -2.7 V and V RE AD of +0.2 V are applied as short pulses each with the duration of 50 microseconds.

[0040] Figure 6 shows schematic illustrations of possible physical models of different resistive switching mechanisms induced by variation in current compliance during an initial electroforming process. Detailed Description of Specific Embodiments Results and Discussion Characterization of Cr.a-STOx oxide

[0041] Figure 1 (a) shows a schematic diagram of a fabricated Cr:a-STOx based metal-insulator-metal (MIM) device 1 0 patterned in cross-point structures and deposited layer sequence for the oxide and electrical connections of a single memory cell. Cr: amorphous-STOx (referred to in shortened notational form as STOx) oxide thin films are sputtered onto pre-patterned Pt/Ti bottom electrodes at room temperature using Si02/Si as a substrate. Top Pt/Ti electrodes are deposited to complete the MIM configuration for electrical characterization of fabricated memory cells.

[0042] Figure 1 (b) shows a cross-sectional view of a representative single layer memristor device 1 0 produced according to a preferred embodiment of the present invention. The single layer device 10 is a stacked passive to terminal metal insulated metal (MIM) device or cell that comprises first and second electrodes 20, 30 that act as the top and bottom electrodes, respectively, of the single layer MIM device 10. The first and second electrodes 20, 30 are inert high work function metal electrodes that are produced from a metal selected from the group consisting of platinum, palladium, gold, tungsten and titanium nitride.

[0043] In a preferred embodiment, the first and second electrodes 20, 30 are formed from platinum metal. The thickness of top Pt electrode 20 may fall within the range of about 20 nm to about 30 nm and bottom Pt electrode 30 may fall within the range of about 5 nm to 10 nm.

[0044] As shown in Figure 1 (b), the first or top platinum electrode 20 has a cathode metal layer 40 disposed on an inwardly facing surface thereof. The cathode metal layer 40 is ideally a reactive low work function metal selected from the group consisting of platinum, palladium, gold, palladium-silver, ruthenium and iridium.

[0045] In a preferred embodiment, the cathode metal layer 40 is formed from titanium metal having a thickness that falls within the range of about 3 nm to about 12 nm, more preferably, a thickness that falls within the range of about 5 nm to about 10 nm. [0046] Disposed substantially between, and in electrical contact with, the second or bottom platinum electrode 30 and the titanium cathode layer 40 is an active region that comprises a switching layer in the form of an amorphous metal oxide 50. The amorphous metal oxide switching layer 50 takes the form of a near stoichiometric, oxygen-deficient amorphous perovskite ternary metal oxide layer of strontium titanate that has been doped with chromium, hereinafter referred to as Cr:a-SrTi03- x, wherein 0.05 < x < 0.15.

[0047] In one embodiment, the oxygen-deficient Cr:a-STOx switching layer 50 has a thickness that falls within the range of about 1 5 nm to about 40 nm, more preferably, within the range of about 15 nm to about 30 nm, still more preferably, within the range of about 15 nm to about 25 nm.

Electroforming at difference current compliances

[0048] Sputtering a-STCv oxide in a reducing environment such as pure argon may create inherent oxygen vacancies in Ti-0 6 octrahedra by preferentially removing oxygen atoms due to heavy Ar + ion bombardment. These oxygen vacancies may generate conduction band electrons in Ti 3d states. However, doping Cr in a-STO x by co-sputtering from a metallic Cr target may localize conduction band electrons by trapping them at Cr sites and valence of Cr may be reduced from Cr 4+ to Cr 3+ .

[0049] Consequently, no conduction electrons may be introduced in Ti 3d states and pristine Cr:a-STO x oxide may exhibit an insulating nature. This suggests insulating characteristics of as-deposited Cr:a-STO x thin films. Prior to electroforming, Cr:a-STO MIM cells exhibit device resistances of >1 0 GQ at 0.2 V, indicating highly insulating characteristics of pristine Cr:a-STCv oxide.

[0050] In order to activate resistive switching in STO-based MIM devices, an initial high voltage sweep which is higher than subsequent switching threshold voltages, is usually required as an electroforming step which creates nano filamentary extended defect structures through a redox process in oxide.

[0051] Experiments show that a negative electroforming voltage sweep from the bottom Cr:a-STOVPt interface was required in pristine Cr:a-STO MIM devices. A positive electroforming bias also applied from the bottom Cr:a-STO>/Pt interface but the MIM device could not survive after several cyclic sweeps. This device failure may be attributed to an impermeable nature of bottom Pt electrode than Ti at the top Ti/Cr:a-STCv interface for oxygen ions produced by a redox process during cyclic voltage sweeps.

[0052] Figure 2 shows characteristic electroforming sweeps and associated resistive switching behaviours induced in Cr:a-STO x MIM devices. Electrical characterization of memory devices may be performed via an Agilent B2900 series source/measure unit (SMU) and a Keithley 4200-SCS parameter analyser. A schematic of a waveform of applied voltage used for electroforming is depicted in Figure 2(a), while a schematic of the applied voltage used for the post-electroforming operation of memory devices is depicted in Figure 2(b). All electrical signals, during electroforming and memory switching operations, are preferably applied in a DC dual sweep mode from the bottom Pt electrode (30) while the top Pt/Ti electrode (20,40) is connected to ground.

[0053] Switching behaviours may be induced in MIM devices at varying current compliances. Three distinct switching behaviours, namely complementary resistive switching (CRS, Figure 2(c)), "peculiar" complementary resistive switching (p-CRS, Figure 2(d)) and bipolar resistive switching (BRS, Figure 2(e)) may be induced at current compliance (|/ C c l) limits as described below.

[0054] A current compliance which induces complementary resistive switching (CRS) behaviour during electroforming may range from about 1 μΑ to about 5 μΑ. The electroforming voltage (V ei ), with waveform shown in Figure 2(a), may range from about 2 V to about 4 V. All memory devices tested have same thicknesses, and as explained above, no clear relationship has been observed between changes in lateral dimension and V e/ compliance current. Figure 2(c) shows a linear l-V plot of an electroforming step with a current compliance of 5 μΑ inducing complementary resistive switching.

[0055] A current compliance which induces "peculiar" complementary resistive switching (p-CRS) behaviour during electroforming may range from about 5 μΑ to about 1 0 μΑ. The electroforming voltage (V e f), with waveform shown in Figure 2(a), may range from about 2 V to about 6 V. All memory devices tested have same thicknesses, and as explained above, no clear relationship has been observed between changes in lateral dimension and V e/ compliance current. Figure 2(d) shows a linear l-V plot of an electroforming step with a current compliance of 10 μΑ inducing "peculiar" complementary resistive switching. [0056] A current compliance which induces bipolar resistive switching (BRS) behaviour during electroforming may range from about 40 μΑ to about 50 μΑ. The electroforming voltage (V e/ ), with waveform shown in Figure 2(a), may range from about 3 V to about 7 V. All memory devices tested have same thicknesses, and as explained above, no clear relationship has been observed between changes in lateral dimension and V e / compliance current. Figure 2(e) shows a linear l-V plot of an electroforming step with a current compliance of 40 μΑ inducing bipolar resistive switching.

[0057] The switching characteristics shown in Figures 2(c)-2(e) are illustrations of representative resistive switching behaviours taken from electrical measurements on Cr:a-STO MIM devices. The effect of \l cc \ on the nature of resistive switching behaviour is described below with reference to a physical model.

Complementary Resistive Switching behaviours induced at low and moderate current compliances

[0058] A Complimentary Resistive Switching (CRS) cell is considered as one possible solution to eliminate or alleviate sneak currents in a passive crossbar array for high density memory integration, as it may exhibit an intrinsic selector and a memory element. A commonly known CRS cell comprises two BRS cells connected anti-serially in a tri-layer structure through an intermediate electrode. Each BRS cell may be reversibly switched between a low resistive state (LRS) and a high resistive state (HRS) under opposite applied voltage polarities.

[0059] Unlike bipolar characteristics where two resistive states (HRS and LRS) define the device state, three states "HRS-1 ", "HRS-0" and "ON" may represent different configurations of resistive state in each BRS cell during CRS operation. Both "HRS1 " and "HRS0" states give rise to a high CRS device resistance at low READ voltages ( VREAD) when compared to a certain threshold voltage, which is an intrinsic property of the CRS mechanism to suppress sneak currents in a memory array, while the "ON" state may give rise to a low device resistance at high V RE AD- [0060] Figure 3 shows complementary resistive switching behaviour induced in a Cr:a-STOx MIM device of size 100x1 00 μιη 2 at an |I CC | limit of 5 μΑ. In this electroforming process, one complete switching cycle comprises the three aforementioned resistive states. Transition of resistive states from "HRS-1 " to "ON" and from "ON" to "H RS-0" occurs at positive threshold voltages during cyclic voltage, sweeps denoted in Figure 3 by VTH,1 (~1 .1 V) and VTH,2 (~1 .6 V), respectively.

[0061] Similarly, transition from "HRS-0" to "ON" and from "ON" to "HRS-1 " occurs at negative threshold voltages, denoted by VTH,3 (~-1 .2 V) and VTH,4 (~- 1 .4 V), respectively. In a common CRS characteristic, both "HRS-1 " and "HRS-0" are regarded as stored memory states and exhibit HRS of the CRS cell at low voltages (between VTH,3 and VTH,1 ) while "ON" is a transition state which distinguishes (between "HRS-1 " and "HRS-0") resistive states at higher voltages (such as VTH.1 < VREAD < VTH,2 or VTH,3 < VREAD < VTH,4) as shown in Figure 3.

[0062] Figure 4(a) shows characteristics of peculiar complementary resistive (p- CRS) switching behaviour induced in a Cr:a-STO MIM device of size 40x40 μιη 2 . Figure 4(b) shows retention performance at room temperature for 1 0 5 seconds under constant VREAD, I of +0.2 V and VREAD,2 of +1 .6 V used to measure the HRS/LRS and ON state resistances, respectively. Figure 4(c) shows the endurance characteristics of the p-CRS regime for 4000 switching cycles. During the endurance measurements, a train of short pulses with a duration of 50 microseconds are used to WRITE/ERASE/READ the devices (as depicted in the inset of Figure 4(c)). For each complete WRITE/ERASE/READ cycle, a positive pulse with an amplitude of +2.3 V switches the devices to HRS is followed by a V RE AD, I pulse with an amplitude of +0.2 V. A negative pulse of -2.3 V amplitude switches the devices to LRS/ON followed by VREAD, I (+0.2 V) and V RE AD,2 (+1 .6 V) pulses to READ the LRS and ON states, respectively. Finally, a second negative pulse of -2.3 V is required to restore the LRS/ON states, prior to the next cycle.

[0063] In a conventional readout operation of CRS devices, generally a higher VREAD than transitional thresholds VTH, I and VTH,3 is required, as the stored states ("HRS-1 " and "HRS-0") cannot be distinguished at lower VREAD- This can change the resistive state of the CRS device and re-writing of the resistive state is needed as a result of this destructive readout operation. Interestingly, monolayer Cr:a-STO MIM devices, electroformed at a \I CC \ limit of 10 μΑ, show a reproducible "peculiar" CRS (p-CRS) behaviour, wherein stored resistive states can be distinguished in a non-destructive readout process {i.e., V T H, I > VREAD < V T H,3), as depicted in Figure 4(a).

[0064] A prominent advantage of p-CRS, over conventional CRS, includes a possibility of tri-level storage, wherein LRS, HRS and "ON" may be distinctively stored in a single cell and inherent switchable diode characteristics of p-CRS may facilitate implementation of complete logic operations.

[0065] Similar to the CRS characteristics (Figure 3), transition of resistive states from LRS to "ON" and from "ON" to HRS occur at V M I of -1 .25 V and V M2 of -1 .8 V during positive cyclic voltage sweeps, respectively, as depicted in Figure 4(a). Furthermore, transition from HRS to "ON" and from "ON" to LRS occurs at VTH,3 of — 1 .4 V and V T H,4 of ~-1 .8 V, respectively, during negative voltage sweeps.

[0066] Figure 4(b) shows tri-level retention performance at room temperature for 10 5 seconds under constant VREAD, I of +0.2 V and VREAD,2 of +1 .6 V used to measure the HRS/LRS and ON state resistances, respectively. This suggests stability of tri-level storage of p-CRS behaviour in Cr:a-STO x MIM devices. To further ascertain stability of p-CRS behaviour in Cr:a-STO x MIM devices, electrical characterization was conducted at elevated temperatures in a 330-390 K range. It is worth mentioning that Cr:a-STO* devices exhibited distinguishable bi-level states (HRS and LRS) at the subjected high temperature range, under non-destructive readout. Furthermore, an increase in current levels, in either resistive state, with an increase in temperature suggests a semiconducting nature of conduction through Cr:a-STO MIM devices.

Bipolar resistive switching behaviour induced at higher current compliance

[0067] Figure 5(a) shows bipolar resistive switching (BRS) behaviour induced in a Cr:a-STO x MIM device of size 1 0x10 μιη 2 Figure 5(b) shows retention performance at room temperature for 10 5 seconds at a constant V RE AD of +0.2 V.

[0068] In this electroforming process a forming voltage of —4.8 V and \l cc \ limit of 40 μΑ, sets the Cr:a-STO x MIM device into the BRS regime. Typical bipolar l-V curves under DC voltage sweeps as shown in Figure 5(a) depict a repeatable and well-defined clockwise BRS characteristic which is a signature of a-STO devices. The devices may be RESET when a positive bias is applied from the bottom electrode and SET when a negative bias is applied from the bottom electrode.

[0069] Cr:a-STO MIM devices, which are pre-set to a low resistance state (LRS) by the electroforming process, switch to a high resistance state (HRS) at a RESET voltage { V RE SET) of +2 V. Subsequently, under an applied negative voltage polarity, HRS switches to LRS at a SET voltage ( V S ET) of -1 .2 V. Figure 5(b) shows retention of Cr:a-STCv IM devices in both LRS and HRS with an average ILRS/IHRS ratio of ~1 8.3 at a VREAD of +0.2 V for 1 0 5 seconds, at room temperature.

[0070] No significant degradation in consecutive switching cycles (Figure 5(a) and 5(c)) and retention (Figure 5(b)) indicates a stable clockwise BRS characteristics of Cr:a-STCv MIM devices under the applied electrical conditions.

[0071] As previously mentioned, electrons introduced due to oxygen vacancies in Ti0 6 octahedra, during Cr:a-STO x sputtering, are localized at Cr sites which results in insulating MIM devices in their pristine state. In the electroforming step, regardless of compliance current limit, localized electrons at Cr sites de-trap under the influence of an applied electric field and contribute to the Ti 3d conduction band, consequently increasing the valence of Cr (from Cr 3+ to Cr 4+ ) during an oxidation process.

[0072] It is widely accepted that the electroforming process generates oxygen vacancies and alters their distribution in metal oxides through redox processes. Consequently inducing a localized current flow channel, between the top and bottom electrodes, through the oxide system results in formation of oxygen deficient filamentary paths.

[0073] Conductive filaments may have non uniform cross-sectional area and different shapes, such as conical or hour-glass, depending on the electroforming process and oxide systems. However, regardless of the filaments' shape, subsequent resistive switching may be attributed to capture and rejuvenation of a conductive filamentary path at its weakest part, most likely close to the anode, through drift of oxygen vacancies under influence of an applied bias.

[0074] In Cr:a-STCv MIM devices, Cr doping further increases concentration of localized oxygen vacancies which then contribute to formation of a conductive filamentary path under an applied bias. Also in the case of an asymmetric electrode configuration, with Ti at the top electrode, the Ti/Cr:a-STO interface partially oxidizes and forms a thin layer of TiO* through oxygen exchange reactions, even prior to an electroforming process. This thin sub stoichiometric TiO layer at the vicinity of the top metal-oxide interface may also contribute to resistive switching of Cr:a-STCv MIM devices.

[0075] Figure 6 shows schematic illustrations for possible physical models of different resistive switching mechanisms induced by variation in current compliance during an initial electroforming process. [0076] When the bottom electrode of the Pt/Cr:a-STOx interface is negatively biased, oxygen vacancies start to generate as oxygen ions are pushed towards the top Pt/Ti interface and several localized spots, including Cr doped sites, become oxygen deficient. Under influence of an applied forming bias, positively charged oxygen vacancies drift towards the bottom electrode, acting as a cathode, and start to accumulate at its vicinity. When a sufficient number of oxygen vacancies are accumulated at the cathode interface, their density extends towards the top Pt/Ti electrode, acting as an anode, and form an extended filamentary path.

[0077] At lower \l cc \ limits {i.e., 5 μΑ and 10 μΑ), a lower density of oxygen vacancies is generated during the electroforming step. Also the absence of a sufficient driving force for their migration prohibits complete rejuvenation of the filamentary path across the TiOVCria-STCv interface. This results in formation of two distinctive filamentary paths in the sub stoichiometric TiO and Cr:a-STO x layers.

[0078] While not intending to be bound by any one particular theory, the CRS behaviour in Cr:a-STO x MIM devices may be explained by repetition of processes schematically depicted in Figure 6 (CRS at low and moderate current compliances). Post-electroforming electrical characteristics of the CRS and p-CRS behaviours {i.e., threshold transitions) suggest that both resistive switching behaviours follow a similar switching mechanism in terms of oxygen vacancy distribution and migration in TiO and Cr:a-STO x layers, after forming at lower \I CC \ limits than is required to achieve BRS behaviour.

[0079] On the other hand, in the case of a higher \I CC \ limit (40 μΑ), a higher density of oxygen vacancies is generated during the electroforming step, and a sufficient driving force is available for their migration across the TiOyCna-STCv interface. The subsequent mechanism of BRS behaviour (RESET when a positive bias is applied and SET when a negative bias is applied) may be explained by repetition of the process schematically depicted in Figure 6 (BRS at high current compliances). During BRS operation, when a negative bias is applied at a bottom Pt electrode of the MIM device, SET occurs due to a complete rejuvenation of the extended oxygen-deficient filamentary path across the TiOx Cr:a-STO x oxide structure. When a positive bias is applied to the bottom Pt electrode of the MIM device, RESET occurs as a result of a rupture of the filamentary path due to drift of oxygen vacancies under reverse polarity. [0080] In conclusion, three distinctive resistive switching behaviours, namely - bipolar, complementary and peculiar complementary resistive switching may be observed in a single monolayer Cr:a-STO x MIM device, induced by a current compliance limit during an initial electroforming process. Based on material and electrical characterization it is suggested that Cr doping in a-STO* oxide increases concentration of oxygen vacancies (compared to as-grown insulating oxide) under influence of a forming bias. During an initial electroforming step, set current compliance may define concentration and redistribution of oxygen vacancies across the TiOVCr:a-STO interface and consequently may induce an irreversible resistive switching behaviour in the Cr:a-STO* MIM device. The existence of three distinctive irreversible resistive switching behaviours in one Cr:a-STO based memory cell and their addressability through a single physical parameter, i.e., current compliance during an initial electroforming step, may offer new memristive applications in an ultra-high dense memory array, neuromorphic and logic computation.

Experimental

Material deposition and device fabrication

[0081] Resistive switching devices in a cross-point configuration were fabricated via standard photolithography/lift-off and thin film deposition processes. After patterning through a shadow mask, bottom Pt (7 nm)/Ti (3 nm) electrodes were evaporated onto a S1O2 (300 nm)/Si substrate by electron beam evaporation (Kurt J. Lesker PVD75 Pro-line), prior to lift-off.

[0082] The bottom Ti (3nm) layer may be used to promote adhesion between the Si02/Si substrate and the Pt bottom electrode. This adhesion layer may have insignificant impact on performance of the resistive switching device. The SiCVSi substrate is selected due to its compatibility with conventional CMOS fabrication and has no significant impact on performance of the resistive switching device.

[0083] A 30 nm thin film of amorphous oxygen-deficient STO was RF sputtered (Kurt J. Lesker PVD75 sputtering system) onto the Pt bottom electrode in a pure argon atmosphere at room temperature from a commercial ceramic STO target (99.95%, Testbourne Ltd). Cr species were incorporated into the STO thin film by co- sputtering of a metallic Cr target (99.95%, Testbourne Ltd) via DC magnetron sputtering. Finally, following photolithographic patterning, top Pt (20 nm)/Ti (8 nm) electrodes were evaporated onto the Cr:a-STO x thin film by electron beam evaporation at room temperature. The cross-point devices with top/bottom electrodes of widths 2, 4, 10, 40, 80 and 100 μιη were fabricated for electrical characterization.

Electrical characterization

[0084] Electrical characterization of Cr:a-STO x MIM devices was performed using an Agilent 2912A source meter and Keithley 4200 SCS for two-probe measurements. Characterizations were performed for all measurements using the bottom electrode as a drive electrode with the top electrode connected to system ground. Temperature dependent measurements were carried out in an environmentally isolated stage from Linkam Scientific.

[0085] Where the terms "comprise", "comprises", "comprised" or "comprising" are used in this specification (including the claims) they are to be interpreted as specifying the presence of the stated features, integers, steps or components, but not precluding the presence of one or more other features, integers, steps or components, or group thereof.

[0086] While the invention has been described in conjunction with a limited number of embodiments, it will be appreciated by those skilled in the art that many alternatives, modifications and variations in light of the foregoing description are possible. Accordingly, the present invention is intended to embrace all such alternatives, modifications and variations as may fall within the spirit and scope of the invention as disclosed.