Title:
MULTILAYER CAPACITOR MOUNTING STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2017/098768
Kind Code:
A1
Abstract:
In this multilayer capacitor mounting structure (1), a first multilayer capacitor (11) and a second multilayer capacitor (12) are mounted between a power supply and a ground of an IC (13) on a wiring board (10). A first external electrode (11b) of the first multilayer capacitor (11) and a first external electrode (12b) of the second multilayer capacitor (12) are electrically connected to a power supply pattern (10j) formed on one surface (10a) of the wiring board (10). A second external electrode (11c) of the first multilayer capacitor (11) and a second external electrode (12c) of the second multilayer capacitor (12) are electrically connected to a ground pattern (10i) formed on the one surface (10a) of the wiring board (10). A first path including the first multilayer capacitor (11), and a second path including the second multilayer capacitor (12) are formed in parallel between the power supply and the ground of the IC (13). The first path has a high ESR and a low ESL. The second path has a low ESR and a high ESL.
Inventors:
FUJII YASUO (JP)
Application Number:
PCT/JP2016/076937
Publication Date:
June 15, 2017
Filing Date:
September 13, 2016
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H05K1/18; H01G2/06; H01G4/232; H01G4/30
Foreign References:
| JP2003086927A | 2003-03-20 | |||
| JP2001185441A | 2001-07-06 | |||
| JP2010129657A | 2010-06-10 | |||
| JP2014096541A | 2014-05-22 |
Attorney, Agent or Firm:
UEDA Kazuhiro (JP)
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