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Patent Searching and Data


Title:
MULTILAYER CHIP INDUCTOR AND PRODUCTION METHOD FOR SAME
Document Type and Number:
WIPO Patent Application WO/2012/077413
Kind Code:
A1
Abstract:
[Problem] To provide a multilayer chip inductor that suppresses reduction in core surface area caused by misalignment of stacked insulating layers with a conductor pattern formed thereon, and capable of adapting to adjustments in the number of coil windings. [Solution] Magnetic sheets (A1-A4) that have circulating patterns (30-36) with connecting sections at the corner and end sections thereof formed therein are layered in a prescribed order and connected by through holes, to form a spiral-shaped coil pattern (16). Extraction patterns (40, 42) are formed at positions that do not overlap with the circulating sections of the coil pattern (16) and have an extraction section that connects to external terminal electrodes (18, 20), two connecting sections connected to the extraction section and formed at positions corresponding to a connecting section for the circulating pattern connecting sections, and a cut out formed between the two connecting sections. Reduction in core surface area caused by displacement during stacking can be suppressed by the provision of magnetic sheets (B1, B2), with the extraction patterns (40, 42)disposed thereon, above and below the laminate on which the coil pattern (16) is formed.

Inventors:
MARUYAMA YOSHIKAZU (JP)
KOHARA MASATAKA (JP)
OYAMA KAZUHIKO (JP)
Application Number:
JP2011/073987
Publication Date:
June 14, 2012
Filing Date:
October 19, 2011
Export Citation:
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Assignee:
TAIYO YUDEN KK (?1100005, JP)
MARUYAMA YOSHIKAZU (JP)
KOHARA MASATAKA (JP)
OYAMA KAZUHIKO (JP)
International Classes:
H01F17/00; H01F41/04
Foreign References:
JPH07201568A1995-08-04
JPH09129448A1997-05-16
JPH04134807U1992-12-15
JP2607588Y22001-11-12
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Claims: