MULTILAYER ELECTRONIC COMPONENT AND ITS MANUFACTURING METHOD

WIPO Patent Application WO/2007/049456

A1

Exposed portion of the ends of the internal electrodes on a predetermined surface of a multilayer body constituting a multilayer electronic component are directly electrolytically plated, and thus an external electrode for electrically interconnecting the ends of the internal electrodes can be fabricated with high accuracy. A multilayer body (5) is prepared in which adjacent internal electrodes (3a, 3b) are electrically insulated from each other on an end surface (6) where the internal electrodes (3a, 3b) are exposed, the interval (s) between adjacent internal electrodes (3a, 3b) measured in the direction of the thickness of the insulating layer (2) is 10 μm or less, and the withdrawal length (d) of the internal electrodes (3a, 3b) from the end surface (6) is 1 µm or less. At an electrolytic plating step, electrolytic plating deposited bodies deposited on the end surfaces of the internal electrodes (3a, 3b) are grown so that they are interconnected.

KUNISHI TATSUO (JP)
TAKANO YOSHIHIKO (JP)
KURODA SHIGEYUKI (JP)
MOTOKI AKIHIRO (JP)
KASHIO HIDEYUKI (JP)
NOJI TAKASHI (JP)
OGAWA MAKOTO (JP)

PCT/JP2006/320200

May 03, 2007

October 10, 2006

Click for automatic bibliography generation  

MURATA MANUFACTURING CO (JP)
KUNISHI TATSUO (JP)
TAKANO YOSHIHIKO (JP)
KURODA SHIGEYUKI (JP)
MOTOKI AKIHIRO (JP)
KASHIO HIDEYUKI (JP)
NOJI TAKASHI (JP)
OGAWA MAKOTO (JP)

H01G4/12; C25D7/00; C25D17/16; H01G4/30

JPH10208978A	1998-08-07
JP2004146401A	2004-05-20
JP2002053999A	2002-02-19
JPS63171892A	1988-07-15
JP2002121692A	2002-04-26
JPS58100482A	1983-06-15

KOSHIBA, Masaaki (Nisshin Buiding 14-22, Shitennoji 1-chome, Tennoji-ku, Osaka-sh, Osaka 51, JP)

View/Download PDF      PDF Help

Previous Patent: SEMICONDUCTOR MEMORY CARD

Next Patent: STACKED ELECTRONIC COMPONENT, ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING STACKED ELECTRONIC COMP...