MULTILAYER PRINTED WIRING BOARD AND PRODUCTION METHOD THEREFOR

Title:

MULTILAYER PRINTED WIRING BOARD AND PRODUCTION METHOD THEREFOR

Document Type and Number:

WIPO Patent Application WO/2004/017689

Kind Code:

A1

Abstract:

A multiplayer printed wiring board, which has quality via holes free from defective shapes such as swellings and recesses at end surfaces, and which comprises as a main structure a laminate consisting of a plurality of insulation layers, and via holes (columnar conductors (31a)) provided to respective insulation layers to electrically connect between conductor circuits in own layer or an adjacent layer, wherein the via holes are formed by patterning a metal foil (31) having conductivity. Since the height H (thickness-direction size of a via hole-forming layer) of a via hole is solely determined by the thickness D of the metal foil (31), a via hole can be formed without filling up conductive paste or electroplating to enable the production of a multiplayer printed wiring board having quality via holes free from defective shapes such as swellings and recesses at end surfaces.

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Inventors:

MIYAZAKI MASASHI (JP)
TAKAYAMA MITSUHIRO (JP)
SAWATARI TATSURO (JP)
MUROTA TAKATOSHI (JP)

Application Number:

PCT/JP2003/010049

Publication Date:

February 26, 2004

Filing Date:

August 07, 2003

Export Citation:

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Assignee:

TAIYO YUDEN KK (JP)
MIYAZAKI MASASHI (JP)
TAKAYAMA MITSUHIRO (JP)
SAWATARI TATSURO (JP)
MUROTA TAKATOSHI (JP)

International Classes:

H05K3/38; H05K3/40; H05K3/20; H05K3/46; H05K3/06; (IPC1-7): H05K3/46; H05K3/20; H05K3/38

Foreign References:

JP2002141629A	2002-05-17
EP1093329A2	2001-04-18
JPH07249864A	1995-09-26
JP2001274554A	2001-10-05
JPH11204943A	1999-07-30
JPH11163207A	1999-06-18

Other References: