BACKGROUND OF THE INVENTION

This invention relates to microelectronics, and, more particularly, to the resist structures that are used to prepare circuit elements.

Integrated circuits are electronic elements wherein a large number of individual microelectronic devices of very small size are prepared on a single supporting surface termed a chip, which underlies or supports the devices. The microelectronic devices are formed of layers of semiconductor, insulator and conductor materials selected and arranged to have particular electronic characteristics. The individual microelectronic devices are typically very small, on the order of a few micrometers or less in lateral extent and often much less in thickness. Thousands of the devices can be formed on a single chip a few centimeters in lateral extent and weighing less than a gram, and linked together in logical arrays to form complex electronic circuits that otherwise might require hundreds of times the space and weight of the integrated circuit. The development of microelectronics underlies many of the improvements made in consumer, business and military electronics.

When the individual microelectronic devices are made so small that they cannot be seen by the unaided eye, their manufacture on a mass scale can be very difficult. The devices cannot be made by conventional techniques such as cutting, joining, welding and soldering, because they are

each so small and the number of devices on a chip is so great. Various new techniques are now used in manufacturing the devices, and one of these, mlcrolithography, is the subject of the present invention.

In lithography as applied to manufacturing microelectronic devices, a pattern is placed onto the surface of a chip or a layer of a particular material deposited onto the chip. The pattern is then filled with another material, or a portion of the pattern may be removed by etching. different pattern is then placed onto the surface of the resulting structure, and another material deposited into the pattern. This procedure of patterning the surface and then depositing or removing material can be repeated many times to build up a complex pattern of layers of different materials and geometries. The final structure may include thousands of microelectronic devices, lying side by side on the chip. If the materials and geometry are properly ^chosen, and all of the individual fabrication steps are performed correctly, the final integrated circuit exhibits the desired electronic properties. Lithography is particularly well suited for manufacturing very small microelectronic devices, because it involves photographic techniques such as optical reduction in size, image exposure, and development of the image. Specifically, a desired pattern for one layer of the fabrication process is prepared in a large size template that can be readily prepared and viewed. The pattern of the template is then projected onto the surface of the chip using projecting illumination such as visible light, electron beam, or ion beam. Before projection, the surface of the chip had been covered with a resist structure,

which is a layer or array of layers of materials sensitive to exposure by the projecting illumination. The resist structure is then developed by photographic developing techniques to reproduce the exact geometry of the pattern of the template onto the surface, except that the pattern is reduced in scale by hundreds or thousands of times.

The resist structure must be readily used in large scale manufacturing operations, must be reproducible, and must be extremely precise in faithfully reproducing the template geometry onto the chip. In the most basic approach, a single layer of a resist material is deposited onto the surface of the chip, and then exposed and developed. The surface of the chip at intermediate stages of the manufacturing process is not smooth, by intention. That is, commonly the microelectronic devices incorporate features such as raised areas termed mesas or depressed areas termed vias. If a uniformly thick layer of a resist material is placed onto such a surface, then the upper surface of the resist layer follows the shape of the mesas or vias and is irregular. Such irregularity is undesirable, since the image of the template cannot be precisely focused upon the irregular surface.

To circumvent the problem of an irregular upper surface on the resist material, it is known to use a fairly thick polymer layer termed a planarizing layer deposited over the mesas and vias. The planarizing layer is so thick, and is applied in such a way, that it fills in the areas between the mesas and the vias and has a planar upper surface,- so- that the image of the template can be focused upon it. If the planarizing layer is used, at least one more layer must be deposited

over it to permit selective definition and removal of areas of resist in preparation for formation of additional features.

One such approach uses three layers, the planarizing layer deposited onto the chip, a separate thin imaging layer into which the pattern of the template is first exposed, and a separating layer between the two. The illuminating radiation exposes the pattern of the template onto the surface of the imaging layer, and the exposed pattern is developed. This pattern is transferred to the separating layer, which is a more durable substance that protects the portions of the planarizing layer that are not removed In the next step, which Is the transfer of the pattern of the separating layer to the planarizing layer. This three layer resist structure is useful in a variety of fabrication procedures.

The currently used three layer resist structure approach -has some significant drawbacks, however, arising from the unavailablity of a separating layer material having a particularly desirable combination of properties. In some fabrication approaches, it would be desirable to illuminate different templates, and even different portions of the same template, with different illuminating radiation. No previously known separating layer material can be readily used with different types of illuminating radiation, and also has the necessary resistance to etching to protect the unpatterned portion of the planarizing layer during etching of the patterned portions. The availability of a single type of resist structure, useful for both light and electron beam illumination, - would- be desirable from a fabrication ^' standpoint. Such a single type of resist structure would permit use of either patterning approach with

a single separating layer material, since different patterning approaches may be used on a single layer.

Accordingly, there exists a need for an improved three-layer resist structure, wherein the material of the separating layer is chosen to protect the planarizing layer during etching, and is also compatible with the use of light and electron beam illumination. The present invention fulfills this need, and further provides related advantages.

SUMMARY OF THE INVENTION

The present invention resides in a resist structure used to pattern substrates in manufacturing microelectronic devices. The resist structure incorporates a separating layer that is compatible with the use of both light and electron beam illumination. The material of the separating layer is transparent to visible light, so that the illuminating pattern can be readily aligned with the existing features of the surface to achieve precise registry of the existing features and the features to be added. The separating layer resists etching during pattern transfer to the planarizing layer, so that patterns can be readily exposed on the imaging layer, transferred to the separating layer, and then transferred to the planarizing layer.

In accordance with the invention, an article having a multilayer resist structure on a substrate comprises a substrate, a planarizing layer- : of a polymer ^• material overlying the substrate, a separating layer of a light transparent and electrically conductive material

overlying the planarizing layer, and an imaging layer of a resist material overlying the separating layer. The transparent conductive material is preferably a mixture of indium oxide and tin oxide, also termed indium tin oxide. Indium tin oxide has been known as a conductor material, but has not been used as a separating material in a multilayer resist structure.

Also in accordance with the invention, a process for preparing an article having an etched multilayer resist structure on a substrate comprises the steps of furnishing a substrate, depositing a planarizing ^" layer of a polymer material overlying the substrate, depositing a separating layer of a light transparent and electrically conductive material overlying the planarizing layer, depositing an imaging layer of a resist material overlying the separating layer, defining and developing a pattern in the imaging layer, transferrring the pattern to the separating layer, and transferring the pattern to the planarizing layer. The separating layer is preferably indium tin oxide.

The planarizing layer is a material that can be readily applied over an uneven surface, such as a substrate having mesas or vias, yet itself have a relatively planar upper surface. Many standard polymer materials can be used. Most are applied in a solution with a solvent by flooding the solution of polymer material onto the surface of the substrate, spinning off the excess solution, and allowing the remaining.material to dry.

The separating layer is a transparent conductive material, preferably indium tin oxide. The term indium tin oxide refers to a mixture of indium oxide and tin oxide. The indium tin oxide

can also be thought of as indium oxide doped with tin, or tin oxide doped with indium, when the indium tin oxide is predominantly indium oxide or tin oxide, respectively. A mixture of about 91 percent indium oxide and 9 percent tin oxide is transparent to light and is electrically conductive, but such material has not been used as a separating material in resist structures. The present invention is not limited to this particular composition of indium tin oxide, and no limit is known on the operable compositions in this system. The light transparent and electrically conductive material, preferably indium tin oxide, can be applied to the substrate in any satisfactory manner, with reactive sputtering being preferred.

The use of a transparent material has the important advantage that the surface of the substrate can be seen visually through the separating layer, allowing the pattern of the template to be precisely aligned with the existing structure on the substrate using commercially available optical alignment devices. The use of an electrically conducting material has the advantage that the separating layer can be used for electron beam pattern definition in the imaging layer. When an electron beam is used to pattern the imaging layer, the underlying separating layer must be electrically conducting to complete the circuit with the electron gun, or a static charge will develop at the surface of the imaging layer to deflect the electron beam and distort the pattern. No satisfactory light transparent and electrically conductive material has been previously known for use in conjunction with resist structures, to provide these benefits.

The material of the separating layer must also be resistant to etching by the preferred

techniques used to transfer the pattern to the planarizing layer. The preferred technique is reactive ion etching, which is a dry etching technique that is highly directional and produces a transferred pattern having vertical walls which do not exhibit the undercutting characteristic of wet chemical transfer processes.

The imaging layer is a resist material that can be exposed and developed to produce a pattern on the upper surface of the resist structure, which corresponds to a reduced scale pattern of the template. The imaging layer is ordinarily applied to be very thin, such as about 0.2 micrometers thick, to permit high resolution of the images. The imaging layer can be either a positive or negative resist. A number of light and electron beam resist materials are known and available commercially.

It will be appreciated that the present invention provides . an advance in the art of resist structures for use in manufacturing microelectronic devices. The light transparent, electrically conducting separating layer permits precise optical alignment of the pattern and the substrate, and can be used both for light and electron beam illuminating radiation. The material is sufficiently resistant to etching by conventional dry etching techniques that it permits a sharply defined pattern to be transferred to the underlying planarizing layer. Other features and advantages of the present invention will be apparent from the following more detailed discussion, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the inventi-on.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a side sectional view of a resist structure of the present invention; and

Figure 2 is a flow chart of the steps in preparing and using the resist structure of the invention to produce raised and depressed areas on the substrate, depicting in side sectional view the structure of the resist layer at each step.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention is embodied in a multilayer resist structure 10 on a substrate 12, as illustrated in _^ Figure 1. As used herein, the substrate 12 is the piece upon which the multilayer resist structure 10 is deposited and in conjunction with which it is used. The substrate 12 can be a base, without anything else deposited thereon. Alternatively, as illustrated in Figure 1, the substrate 12 includes a base 14, together with any portion of a structure of a device that has already been deposited upon the base 14. In Figure 1 a layer of silicon 16 has been previously deposited upon the base 14 and etched to form raised areas IS therein, but the invention is not limited to use with any particular previously deposited structure. One of the advantages of the present approach is that it is compatible with a wide variety of underlying substrates 12.

The resist structure 10 includes a planarizing layer 20 overlying the substrate 12. The planarizing layer 20 is sufficiently thick that it fills in the valleys 22 between the raised areas IS. The top surface of the planarizing layer 20 is relatively flat, and serves as the support for the

overlying layers. The planarizing layer 20 can be any polymer material that can be applied to fill in the valleys and have a flat top surface 24. Preferably, the planarizing layer is a polymer such as poly ethylmethacrylate (PMMA), which is a resist material, and which is soluble in an organic solvent. The solution of PMMA is flooded onto the substrate 12 and then the excess solution is removed by spinning . the substrate. During flooding, the solution spreads to cover the surface of the substrate 12, filling in the valleys 22. The substrate covered with the solution is then dried to leave a flat top surface 24 suitable for further processing. The maximum thickness of the planarizing layer is typically about 2 micrometers. Optionally, the planarizing layer can be baked to harden it further.

A separating layer 26 overlies the planarizing layer 20. The separating layer 26 is a transparent, electrically conductive glassy material, preferably indium tin oxide, and most preferably indium tin oxide of composition 91 atomic percent indium oxide and 9 atomic percent tin oxide. Indium tin oxide is electrically conductive and transparent to visible light. The preferred composition of 91 atomic percent indium oxide and 9 atomic percent tin oxide has sufficient electrical conductivity and optical transparency to make it operable for use as a separating layer. The separating layer is applied by any convenient technique. For example, a layer of indium tin oxide is conveniently deposited on the nonmetallic planarizing layer 20, in a thickness of about 0.1 to about 0.2 micrometers, by sputtering of a compound target. ^. . ^. . - — -

Conventional prior art separating layers were sometimes formed of metals such as

aluminum or rhodium, or of silicon, which are electrically conductive but not transparent to visible light. Although these materials gave acceptable results in some operations, there was uncertainty in attempting to align the projected image of the template onto the substrate 12 in precisely the correct position. Alternatively, the separating layers were sometimes formed of silicon dioxide or other electrically nonconducting oxides. When present in a sufficient thickness to resist thinning by reactive ion etching, the silicon dioxide is transparent. However, it is not an electrical conductor and cannot be used in conjunction with electron beam lithographic definition of the pattern for etching. Silicon dioxide is also attacked by fluorine that may be released from polymers used to cover electrodes during dry etching, and is thereby further limited in use. The separating layer material of the present invention avoids these problems and yields the advantages described above.

The separating layer 26 is overlaid by an imaging layer 28. The pattern of the template is exposed and developed into this imaging layer 28, which is therefore chosen to be a resist material sensitive to the illuminating radiation to be used. A resist material is one that undergoes a structural change when exposed to the illuminating radiation, and can then be developed in developing solutions to either remove or retain the exposed regions. If the exposed regions are removed, the resist material is termed a positive resist. If the exposed regions remain, the resist material is termed a negative resist. Examples of resist materials-, suitable for use-as the imaging layer 28 are the Shipley Micropositive or American Hoechst AZ series and Kodak 809 (positive photoresist),

Kodak 747 and Microneg (negative photoresist), PMMA (electron beam positive resist), and P4CS (electron beam negative resist). These resist materials are applied overlying the separating layer 26 according to the standard practice. For example, a solution is prepared of P4CS (poly-4-chlorostyrene) in MIBK (methylisobutylketone) and then flooded onto the surface. The excess solution is removed by spinning the substrate. The thickness of the remaining P4CS resist layer after drying to remove the solvent is typically about 0.2 to about 0.5 micrometers.

In using the multilayer resist structure 10, the structure 10 is first deposited in the manner just described. Then, as illustrated in Figure 2, a pattern in the imaging layer 28 is defined by projection illumination, usually by either light or electron beam illumination. The material of the imaging layer 28 is chosen as a resist for the illuminating radiation to be used. The exposed image is then developed in a developing solution prescribed for the resist material chosen, so that a pattern 30 is etched through the imaging layer 28. The pattern is transferred to the separating layer, preferably by a dry etching technique such as argon sputter etching. The resist structure is placed into an ionized argon atmosphere and a negative voltage applied to the resist structure. Argon ions are accelerated against the portion of the separating layer 26 that is exposed through the openings of the pattern 30 through the imaging layer 28. The argon ions dislodge the exposed indium tin oxide from the separating layer 26., so that the pattern 30" is ^~ transferred to the separating layer.

The pattern is transferred to the

planarizing layer 20, preferably by oxygen reactive ion etching. This technique has the advantage that it Is highly directional, and produces a straight sided pattern downwardly in the planarizing layer 20. The resist structure is placed into an oxygen atmosphere that is excited by a radio frequency signal to produce positive oxygen ions. A negative plasma voltage is applied to the resist structure, so that the oxygen ions are accelerated against the portion of the planarizing layer 20 that is exposed through the openings of the pattern 30. The oxygen ions dislodge the material of the planarizing layer 20 to transfer the pattern 30 to the planarizing layer 20. It will be recalled that the planarizing layer 20 is relatively thick, and it is necessary to continue the reactive ion etching for a period of time to etch the pattern 30 completely through the planarizing layer. The reactive ion etching is so powerful that it quickly removes the remaining portion of the imaging layer 28. The remaining unpatterned portion of the separating layer 26 must therefore be highly resistant to the reactive ion etching, so that the pattern 30 is faithfully transferred to the planarizing layer 20 without rounding of the edges.

The pattern 30 is now completely transferred to the planarizing layer 20, down to the substrate 12. The pattern 30 is used for its intended purpose. Figure 2 illustrates two different subsequent processing alternatives as examples. In one, a layer of a conductor 31 might be deposited through the openings of the pattern 30, thence overlying the substrate 12 only in the areas of the openings. In the other, material is removed from the raised portien 18 of the substrate 12 by etching through the openings of the pattern 30. After these operations ^re complete, the

resist structure 10 is removed by dissolving away the planarizing layer 20. If necessary, the entire procedure is repeated with another, new template and resist structure to produce yet further microelectronic circuit elements on the substrate 12.

The approach of the present invention has been successfully used on test pieces with both light and electron beam pattern definition. Light illumination is preferred for large structures where high resolution of the structures is not necessary. For example, light illumination might be used to define the raised areas or mesas themselves. Electron beam illumination is capable of higher resolution, and is used to define precise patterns such as submicrometer gate structures in field effect transistors. The separating layer of the invention is useful with both light and electron beam illumination, while permitting alignment by visual means. The present resist structure and process have been used to prepare a submicrometer 8 8 multiplier large scale integration (LSI) circuit with over 1400 polysilicon gate transistors. The present invention therefore provides an improved approach for performing lithographic procedures in manufacturing microelectronic devices. The light transparent, electrically conductive material such as indium tin oxide used as the separating layer performs well in protecting the unpatterned portions of the planarizing layer during reactive ion etching. It is transparent in the required thicknesses, so that the pattern of the template can be precisely aligned. -and--matched with the substrate.- It is also electrically conductive to conduct the charge of electron beam illumination, so that electron beam

pattern definition can be used.

Although a particular embodiment of the invention has been described in detail for purposes of Illustration, various modifications may be made without departing from the spirit and scope of the invention. Accordingly, the invention is not to be limited except as by the appended claims.