TECH N ICAL FI ELD

The invention relates to multilevel converters.

BACKGROUND AND PRIOR ART

Multilevel chain link converters are used in many high power applications. In particular, modular converters, where a number of switching cells, each i ncluding a number of switching elements, or switching units, and an energy storing element in the form of a DC capacitor, are connected i n series in a chain link to form a variable voltage source, have found increased use. These modular converters are used in HVDC (High Voltage Direct Current) and FACTS (Flexible Alternating Current Transmission Systems) applications.

A commonly used modular converter consists of serially connected full-bridge, or H-bridge, switching cells, each switching cell comprising four switching units, in the form of semiconductor switches, for example IGBTs (Insulated-Gate Bipolar Transistor) or IGCTs (I ntegrated Gate-Commutated Thyristor), and one DC capacitor unit.

The losses in semiconductor switches is dependent on both the switchi ng of, as well as the conduction by, the switches. In many FACTS converters, the conduction losses have a greater impact on total loss than the switching losses.

Patent document WO2014/194968 A1 discloses (see e.g . abstract and page 10 line 14-21 in WO2014/194968) a multilevel converter for a three phase AC power system . The multilevel converter comprises three phase legs (10, 20, 30) and an energy transfer circuit (40). Each phase leg comprises switching cells (1 1 A-n, 21 A-n, 31 A-n) that comprises semiconductor switches, such as IGBTs and an energy storage element, such as a capacitor (1 2A- n, 22A-n, 32A-n). Each switching cell may be provided i n an H- bridge configuration of the capacitor and four IGBTS , each I GBT in anti-parallel connection with a diode. The energy transfer circuit (40) is centrally arranged in relation to the phase legs (10, 20, 30) and comprises an energy storage element (44) and semiconductor switches, e.g . incl uding IGBTS and diodes, for selective connection to any of the phase legs in order to transfer energy between the energy storage elements (1 2A-n, 22A-n, 32A- n , 44). By means of the energy transfer circuit it is possi ble to transfer energy between the phase legs and counteract imbalances, wherein the need for redundant switching cells is lower than i n prior multilevel converters (such as illustrated in e.g . fig . 9 in WO2014/194968).

SUMMARY OF I NVENTION

An aim of the i nvention is to provide a multilevel converter wherei n the number of switching cells can be comparatively low, still providing a comparatively large number of voltage levels in the output. A further aim is to provide a multilevel converter for a three phase AC system that during use has comparatively low conduction losses.

In a first aspect, the invention provides a multilevel converter for a three phase AC power system . The multilevel converter comprises:

- a first, a second and a third switching leg , wherein each switchi ng leg comprises:

- a first connection provided at a first end of the switching leg for connection to a respective phase (A, B, C) of the three phase AC power system;

- a second connection at a second end of the switching leg opposite the first end ;

- at least one leg switching segment configured as a segment of the switching leg and arranged between the first connection and the second connection , wherein each of said at least one leg switching segment comprises at least one switching block comprising at least one H-bridge switching cell , preferably a plurality of series connected H-bridge switching cells.

The multilevel converter further comprises:

- a delta circuit comprising a first connection, a second connection and a third connection for the switching legs and comprising a respective switching block in a current conduction path between each pair of the first, second and third connections, wherein each switchi ng block of the delta circuit is provided with bi-directional voltage blocking capability and comprises at least one H-Bridge switchi ng cell , wherei n the delta circuit is centrally arranged i n relation to the switching legs, and interconnects the switching legs. Preferably, each switching block of the delta circuit comprises a plurality of H-bridge switching cells arranged in series.

In an embodiment of the first aspect, each switching block of the delta circuit comprises at least one reverse voltage blocking semiconductor switch arranged to provide the bi-directional voltage blocking capability of the delta circuit. Thus enabling that a current path i n each leg of the delta circuit can be selectively blocked or used .

In an embodiment of the first aspect, the at least one reverse voltage blocking semiconductor switch of the delta circuit is arranged in series with the at least one H-Bridge switching cell .

In an alternative embodiment of the first aspect, said at least one reverse voltage blocking semiconductor switch of each switching block of the delta circuit consists of a plurality of reverse voltage blocking semiconductor switches that constitute the switches of the at least one H-Bridge switching cell .

In an embodiment of the first aspect, each switching leg is directly connected by means of its second connection to a respective one of the delta connections of the delta circuit. In an embodiment of the first aspect, each switching leg is connected by means of its second connection via a respective delta connection circuit to the delta circuit, wherein each respective delta connection circuit comprises two switching arms each comprising a switching block, and which switching arms are interconnected at a respective first end at the second connection of said switching leg , and wherei n each of the two switchi ng arms has a respective second end , wherein the two second ends of each delta connection circuit extends to different delta connections and connects each switching leg to two connections of the delta circuit, wherein for each delta connection circuit a respective one of the switching blocks of the delta circuit interconnects the second ends of the two switching arms.

In an embodiment of the first aspect, each switching block of the switchi ng arms of the delta connection circuits comprises at least one H-Bridge switching cell and at least one reverse voltage blocking semiconductor switch arranged to provide bi-directional voltage blocking capability to the switching arms.

In an embodiment of the first aspect, said at least one reverse voltage blocking semiconductor switch of the delta connection circuits is arranged i n series with the at least one H-Bridge switchi ng cell of the delta connection circuits.

In an embodiment of the first aspect, said at least one reverse voltage blocking semiconductor switch of the of the delta connection circuits consists of a plurality of reverse voltage blocking semiconductor switches that constitute the switches of the at least one H-Bridge switching cell of the delta connection circuits.

In an embodiment of the first aspect, each switching block of the delta circuit comprises a pl urality of H-Bridge switching cells in serial connection . In an embodiment of the first aspect, each switching leg comprises a pl urality of leg switching segments arranged i n series.

In an embodiment of the first aspect, each of said at least one leg switchi ng segments comprises a plurality of H-Bridge switching cells in series. In an embodiment of the first aspect, at least one of said at least one leg switching segments comprises at least one switching block that comprises at least one reverse voltage blocking semiconductor switch arranged to provide bi-directional voltage blocking capability to the switching leg .

In an embodiment of the first aspect, the at least one reverse voltage blocking semiconductor switch of at least one switching segment of each switching leg is arranged in series with the at least one H-Bridge switching cell of the switching segment.

In an embodiment of the first aspect, said at least one reverse voltage blocking semiconductor switch of at least one leg switchi ng segment of each switching leg consists of a plurality of reverse voltage blocking semiconductor switches that constitute the switches of the at least one H-Bridge switching cell of the leg switchi ng block.

In an embodiment of the first aspect, said switchi ng segment of each switching leg consists of only one single switching block.

In an embodiment of the first aspect, said switchi ng segment of each switching leg consists of three switching blocks, wherei n one of the switching blocks is arranged in parallel with the other two switching blocks of said switching segment. In an embodiment of the first aspect, each of said three switching blocks of said leg switching segment comprises either:

- at least one reverse blocking semiconductor switch , which is arranged in series with the at least one H-Bridge switching cell of the switching block, or

- a plurality of reverse blocking semiconductor switches that constitute the switches of the at least one H-Bridge switching cell of the switching block. In an embodiment of the first aspect, each reverse blocking semiconductor switch consists of a reverse-voltage blocking I GBT (Insulated-Gate Bipolar Transistor), preferably a silicon-carbide reverse-blocking IGBT. BRI EF DESCRI PTI ON OF TH E DRAWI NGS

Embodiments of the i nvention will be described with references to the accompanying drawings wherein :

Figure 1 A-B illustrate embodiments of a multilevel converter in accordance with the invention ;

Figure 2A-B illustrate embodiments of a switching segment for the multilevel converter;

Figure 3A-B illustrate embodiments of a switching block with reverse voltage blocking capability for the multilevel converter; Figure 4A-B illustrate the topology of two embodiments of the multilevel converter embodiments of figure 1 A and 1 B ;

Figure 5 illustrates useful features of the multilevel converter; Figure 6A-E illustrates dynamic re-configuration of the multilevel converter;

DETAI LED DESCRI PTI ON OF EMBODI MENTS

Figure 1 illustrates a multilevel converter 1 connected to a three phase AC power system, illustrated as three transmission lines for phases A, B , and C. The multilevel converter 1 comprises a first, second and a third switching leg 10A, 10B , 10C and a first second and third connection 1 1 A, 1 1 B, 1 1 C whereby each switchi ng leg 10A, 10B, 10C is connected to a respective phase A, B , C of the three phase AC power system. The switching legs 10A, 10B , 1 0C have the same constructional details, and for reasons of clarity only the first switching leg 10A is illustrated in detail . The multilevel converter 1 further comprises a delta circuit 2 arranged between the switching legs 10A, 1 0B, 10C at the end opposite the connections 1 1 A, 1 1 B , 1 1 C to the three phase power system, so that the switching legs 10A, 10B , 10C are interconnected by means of the delta circuit 2. The delta circuit 2 comprises three switching blocks 9 arranged in the legs between three connections 3, 4, 5 of the delta circuit 2, i .e. one switching block 9 in each leg of the delta circuit 2. I n the embodiment of figure 1 , each switching leg 1 0A, 10B, 1 0C is directly connected to the delta circuit 2 at one respective connection of the connections 3, 4, 5 of the delta circuit 2. Each switching leg 10A, 10B, 10C also comprises a reactor 16 arranged between the switchi ng segments 12 , 13 and the connection 1 1 A, 1 1 B , 1 1 C to the three phase AC power system for smoothening the current provided to the three phase AC power system . The multilevel converter 1 also comprises a controller 40 configured to control the switching performed by the switchi ng blocks 9 of the delta circuit 2 and the switching segments 12 , 1 3 of the switching legs 10A, 10B, 10C. Each of the switching blocks 9 of the delta circuit 2 comprises a plurality of H-bridge switching cells arranged in series, and each of the switching blocks 9 has bi-directional voltage blocking capability. Embodiments of the switching blocks 9 are illustrated in figures 3A and 3B.

In the embodiment of figure 3A, each switchi ng block 9 comprises a plurality of H-bridge switching cells 91 , wherein each H-bridge switchi ng cell 91 comprises a capacitor 95 as energy storage element and four semiconductor switches 93 with reverse voltage blocking capability, exemplified as RB-IGBTs ("Reverse-Blocking Insulated-Gate Bipolar Transistors"), and preferably a SiC, "silicon carbide", RB-IGBT. Each one of the semiconductor switches 93 with reverse voltage blocking capability is a bidirectional switch implemented by two anti-parallel RB-IGBTs. In the alternative embodiment of figure 3B, each switching block 9 comprises a pl urality of H-bridge switchi ng cells 92, wherei n each H-bridge switching cell 92 comprises a capacitor 95 as energy storage element and four semiconductor switches 94 with freewheeling diodes. Thus, the H-bridge switching cells 92 of the embodiment in figure 3B does not have reverse voltage blocking capability, and are exemplified as I GBTs. The H-bridge switching cells 92 are in this embodiment arranged in series with a pl urality, or at least one, semiconductor switches 93 with reverse voltage blocking capability, exemplified as RB-IGBTs, in order to provide the bi-directional voltage blocking capability to the switching block 9. When reverse voltage is applied on the semiconductor switches 94 that has no reverse voltage blocking capability the diodes of these semiconductor switches will conduct current. When reverse voltage is applied on the semiconductor switches 93 that are provided with reverse voltage blocking capability the current can be controlled by selectively turni ng the corresponding RB-IGBT on or off, i .e. the current can be controlled in both directions. Each of the switchi ng segments 12, 13 of the switching legs 1 0A, 10B, 10C comprises a plurality of H-bridge switchi ng cells arranged in series. Preferably, each switching segment 1 2, 13 is also provided with means for reverse voltage blocking capability in order to enable blocking of the current through any of the switchi ng segments 12, 13.

Embodiments of the switching segments 12 , 13 are illustrated in figures 2A and 2B, respectively. The switching segment 12, of figure 2A, comprises a si ngle switchi ng block 9 of any of the two types illustrated in figures 3A and 3B , respectively. Thus, the switching segments 12 of this embodiment may consist of the same type of switching blocks 9 as the delta circuit 2. The switching segment 13, of figure 2B , comprises three switchi ng blocks 9 of any of the two types illustrated in figures 3A and 3B, respectively. The three switching blocks 9 of the leg switchi ng segment of figure 2B is arranged i n parallel between its connection points "input/output", wherein one of the three switchi ng blocks 9 is arranged i n parallel with the other two of the three switching blocks 9. The switching blocks 9 of the switching segment 13 of figure 2B is arranged in a delta, however the delta has only two connections for external connection to the switchi ng leg 10A, 10B , 10C, so that a pl urality of switching segments 13 may be arranged in serial connection i n the switching leg 10A, 10B, 10C. The switching segments 13 of this embodiment may consist of three switching blocks 9 of the same type as the switchi ng blocks 9 selected for the delta circuit 2. Figure 1 B illustrates a second embodiment of a multilevel converter 1 . The multilevel converter 1 of figure 1 B is similar to the multilevel converter 1 of figure 1 A, and comprises switching legs 10A, 10B , 10C with smootheni ng coil 16, switchi ng segments 12, 13 and controller 40 configured in the same way as i n the embodiment of figure 1 A. The multilevel converter 1 of figure 1 B also includes a centrally arranged delta circuit 2 that interconnects the switching legs 10A, 10B, and 10C. However, the multilevel converter 1 of the embodiment of figure 1 B comprises a delta connecting circuit 20 arranged between each switchi ng leg 10A, 10B , 10C and the delta circuit 2. Each delta connecting circuit 20 comprises a first and a second switchi ng arm 21 and 22, respectively, wherein each switching arm 21 , 22 of the delta connecting circuit 20 comprises a switching block 9. Each switching block 9 of the connection circuit 20 is of any of the types illustrated in figures 3A and 3B , and may preferably be of the same type as the switching blocks 9 of the delta circuit 2 and/or the switching blocks 9 of the switching segments 12, 13 of the switching legs 10A, 10B, 10C. Each delta connecting circuit 20 is provided with bi-directional voltage blocking capability of each switching arm 21 , 22. Each delta connecting circuit 20 is connected at a first end to the respective switching leg 1 0, 1 0B, 10C, wherein the switching arms 21 , 22 of the delta connecting circuit 20 are interconnected at the switching leg 10A, 1 0B, 10C. Each delta connecting circuit 20 is connected to the delta circuit 2 by means of the second end of each switching arm 21 , 22, wherei n the second ends of the switching arms 21 , 22 of each delta connecti ng circuit 20 is connected to a respective connection 3, 4 , 5 of the delta circuit so that the two switching arms 21 , 22 are connected on opposing sides of a switching block 9 of the delta circuit 2. Thus, by means of the respective delta connection circuits 20, each switching leg 10A, 10B, 10C is connected to two of the three connections 3, 4 , 5 of the delta circuit, wherein each switching leg 10A, 10B , 10C is connected on opposing sides of a respective one of the three switching blocks 9 of the delta circuit 2.

Figures 4A and 4B illustrate features of the multilevel converter when the switching segment 13 of figure 2B is utilized i n the embodiments of the multilevel converter 1 of figures 1 A and 1 B , respectively.

Only one phase (phase C) is illustrated in detail in figure 4A. The arrangement of the switching blocks 9 of the multilevel converter 1 illustrated in figure 4A can be provided by means of switching segments 13, arranged in serial connection i n each switchi ng leg , wherei n the switching segments 1 3 are connected at only two of its three connections to the switching leg , and wherein one switchi ng segment 13 constitute the delta circuit 2 connected at its three connections 3, 4, 5 to the switching legs 10A, 1 0B, 10C, i .e. one connection 3, 4, 5 to each switching leg . Only one phase (phase A) is illustrated in detail in figure 4B. The arrangement of the switching blocks 9 of the multilevel converter 1 illustrated in figure 4B can be provided by means of switching segments 13, arranged in serial connection i n each switchi ng leg , wherei n the switching segments 1 3 are connected at only two of its three connections to the switching leg , and wherein for each switchi ng leg 10A, 10B , 10C the delta connecting circuit 20 and one of the switching blocks 9 of the delta circuit 2 is provided by means of a single switching segment 13 at the end of the switchi ng leg 10A, which si ngle switchi ng segment 13 is connected at one of its connections to the switching leg 1 0A and its other two connections (connections 3, 5 for phase A) to corresponding si ngle switchi ng segments 13 at the respective end of the other switching legs 10B, 10C.

The multilevel converter 1 comprises switchi ng blocks 9 with bidirectional voltage blocking capability in the delta circuit 2, in order to enable a dynamic reconfiguration of the switching blocks 9 for providing the voltages and currents to the phases A, B , C. The provision of bi-directional voltage blocking capability in the switchi ng segments 12 , 13 of the switching legs 10A, 10B, 10C and/or in the switching arms 21 , 22 of the delta connecting circuit 20 makes further reconfiguration possi ble. Such reconfiguration is especially beneficial in cases when the phase current of each phase A, B , C is shifted about 90 degrees i n relation to the phase voltage. The current conducti ng path of the highest phase currents may be shortened with such dynamic reconfiguration since the phase voltage has its lowest levels when the phase current levels are high . Dynamic reconfiguration of the multilevel converter 1 will further described with reference to figures 5 and 6A-E.

Figure 5 illustrates the use of the multilevel converter 1 of the present invention , and how the multilevel converter 1 can be controlled , especially dynamically re-configured . As an example, one possi ble configuration of the multilevel inverter 1 is illustrated in figure 5. This example may be generalized for other topologies of the present invention. In the multilevel converter of figure 5, some switching blocks 9 have been blocked, illustrated by a diagonal line through the switching block 9, in order to vary the current conducting length of each phase current , IB, lc In the blocked switching blocks 9 of figure 5, all semiconductor switches 93 with reverse voltage blocking capability are off. In case the blocked switching block 9 includes semiconductor switches 94 without reverse blocking capability, as in the embodiment of figure 3B, these (94) are also off. The multilevel converter of the invention is especially useful when the phase difference between the currents and voltages are about 90 degrees, such as in for example FACTS applications. In figure 5, the neutral point of the three phases A, B, C of the multilevel converter has been provided close to phase A. In the example, the voltage of phase A is the lowest, and the voltage of phase C is the highest. When the phase voltage is low, the phase current is high in applications where the voltage and current have a phase difference of about 90 degrees. In phase A that has the lowest voltage and highest current only one switching element 9 is conducting the phase current . The phase voltage of phase B is provided with three switching blocks 9, while the highest phase voltage of phase C is provided by five switching blocks, which phase C however experiences the lowest current of the phases A, B, C. Thus, the five switching blocks 9 required for providing the voltage of phase C conducts the lowest phase current lc. Since the conduction path of the highest phase current ( ) has been shortened, the conduction losses will be comparably short, when compared to ordinary multilevel converters.

In comparison, in prior art multilevel converters most capacitors for the phase that has the lowest voltage will be bypassed. However, such bypass still requires that the switches (such as IGBTs) of the H-bridges to conduct the phase current, which create conduction losses. The multilevel converter 1 of the invention can be controlled to vary the conducting length by moving the neutral point N. This moving will require some extra switching compared to the prior art for providing such a commutation of the current paths, which is illustrated in figures 6A-E.

An anti-parallel combination of IGBT and diode can be blocked, wherein the semiconductor switch is off while the anti-parallel diode may still conduct. Thus, the branch of semiconductor switch of the IGBT is off while the diode branch can conduct if voltage of the correct polarity is applied. An anti-parallel connection of two RB-IGBT's can be blocked, in the same way as an IGBT and anti- parallel diode, wherein one semiconductor is off and the other is on. To facilitate understanding of figures 6A-6E, this state of an RB-IGBT will be referred to as partially blocked and partially bypassed in the following description of figures 6A-6E. The RB- IGBT' combination can also be totally blocked or turned off, wherein both semiconductors are off, and thus none of its two branches can conduct current. Thus, the blocking of the RB-IGBT combination constitutes an enhancement in the blocking capability as compared to an ordinary IGBT.

Figures 6A-E illustrates how the current paths (similar to IA, IB, IC of figure 5), and therefore the current conduction lengths, can be commutated. In figure 6A, the neutral point is provided in connection N4 of the delta circuit 2. In figure 6E, the neutral point has been moved to connection point N3. To move the neutral point N, some extra switching should be performed between two control periods of the multilevel converter. In the example of Figures 6A-E, the switching blocks 9 of each phase leg are controlled in accordance with a suitable modulation scheme of the multilevel converter, while the switching blocks 9 of the delta circuit 2 is switched to move the neutral point N. In the control period of figure 6A, the neutral point is at the connection N4 of the delta circuit 2 and the switching block in the middle, marked M in figure 6A, is blocked. For the case of using the switching block 9 type shown in figure 3B, the semiconductor switches 93 with reverse voltage blocking capability are off and the semiconductor switches 94 without reverse blocking capability, in the H-bridge switching cells 92, are all off in the middle switching block M. The right switching block R and the left switching block L is used for the phase currents IA and lc, respectively. In the following control period of figure 6E, the neutral point is at connection N3 and the left switching block 9, marked L is blocked. For the switching block 9 of figure 3B, the semiconductor switches 94 are off and the reverse blocking semiconductor switches 93 are off in the left L switching block of figure 6E. Further, in figure 6E, the middle switching block M is used for phase current , and the right switching block R is used for phase B, or, in other words, switching block M and R are used for the modulation, while switching block L is blocked.

In the first step illustrated in figure 6B, the middle switching block M is totally blocked, while the right R and left L switching blocks are partially blocked and partially bypassed, where "partially" means that some semiconductor switches are on and some are off. In case of using the switching block 9 of figure 3B, the reverse blocking semiconductor switches 93 are on and current flows through the diodes of the semiconductor switches 94 in the left L and right R switching blocks, whereas in the middle M switching block, the reverse voltage blocking semiconductors 93 are off. Thus, no current flows in the middle branch through the middle M switching block. In case of using the switching block 9 of the type illustrated in figure 3A, each switch on the left in each position of the switches 93 is off while each switch on the right in each position of the switches 93, i.e. the switches corresponding to the diodes of figure 3A, is on. Thus, in figure 6B, the left L and right R switching blocks are partially blocked and partially bypassed allowing current to be conducted in those two branches, whereas the middle switching block M is totally blocked so that no current is conducted on that branch. In the second step 6C, left switching block L is partially blocked and partially bypassed , while the other switching blocks, M and R, are bypassed , wherein the currents are commutated . In case of using the switching block 9 of figure 3B , the reverse blocking semiconductor switches 93 of the middle block M is turned on/bypassed , and the capacitors 95 of the H-bridge cells 92 of the right R and middle M switching blocks are bypassed by means of the semiconductor switches 94 (e.g . IGBTs). The H-bridge cells 92 of the left L switching block 9 is blocked , and the reverse blocking semiconductor switches 93 of the left block L remains on . In case of usi ng the switching block 9 of figure 3A, the RB- IGBTs on the left of each position are off, and the RB-IGBTs on the right in each position are on in the left switchi ng block L, so that the current commutates and eventually there is no current on that branch . The right R and middle M switching blocks are bypassed by means of the RB-IGBTs of these switching blocks allowing current to be conducted on those branches.

In the third step 6D, the left L switching block is totally blocked . In case of usi ng the switching block 9 of figure 3B , the H-bridge cells 92 of the left L switching block 9 are blocked , and the reverse blocking semiconductor switches 93 of the left block L are turned off. The reverse blocking semiconductor switches 93 of the middle M and right R switching blocks remain on and the capacitors 95 of the H-bridge cells 92 of the middle M and R switchi ng blocks remai n bypassed . In case of usi ng the switchi ng block 9 of figure 3A, all the semiconductor switches 93 of the left L switchi ng block are off, and conducts no current. The right R and middle M switching blocks remain bypassed by means of the RB-IGBTs (93) of these switching blocks allowing current to be conducted on those branches.

In the fi nal step of figure 6E , the switchi ng cells 91 , 92 of the right R and middle M switching blocks 9 are modulated for the next control period in accordance with the modulation scheme. The left L switchi ng cell is blocked . In case of using the switching block 9 of figure 3B, the reverse blocking semiconductor switches 93 are off in the left L switching cell. In case of using the switching block 9 of figure 3A, the reverse blocking semiconductor switches 93 of the H-bridge switching cells 91 are off in the left L switching cell.

The commutation process illustrated in figures 6A-E can be generalized to all embodiments of the multilevel converter 1 , and the neutral point can be moved in the delta circuit 2, in any of the delta connecting circuits 20 and in any of the phase legs 10A-C.

Similarly, the conduction paths of the phase currents IA, IB, IC through any leg switching segment 13, as illustrated in figure 5, can be commutated. Embodiments of a multilevel converter 1 comprising a first 10A, a second 10B and a third 10C switching leg have been described. In these embodiments, each switching leg 10A, 10B, 10C comprises a first connection 11 A, 11 B, 11 C for a respective phase A, B, C of a three phase AC power system; a second connection 14A, 14B, 14C opposite the first; and at least one leg switching segment 12, 13 arranged between the first connection 11 A, 11 B, 11 C and the second connection 14A, 14B, 14C. Each switching segment 12, 13 comprises at least one switching block 9 comprising at least one H-Bridge switching cell 91, 92. The multilevel converter 1 further in comprises a delta circuit 2 comprising connections 3, 4, 5 for the switching legs 10A, 10B, 10C and a respective switching block 9 in a current conduction path between each pair of the connections 3, 4, 5 Each switching block 9 of the delta circuit 2 is provided with bi-directional voltage blocking capability. The delta circuit 2 is centrally arranged and interconnects the switching legs 10A, 10B, 10C.

The invention is not limited to these embodiments, but may be varied within the scope of the claims.