FIELD OF THE INVENTION The present invention generally relates to converters for conversion between AC and DC. More particularly the present invention relates to a multilevel voltage source converter as well as to a method of handling faulty semiconducting elements of a voltage source converter.

BACKGROUND

Cell based multilevel voltage source converters are known to be used for converting between AC and DC voltages .

The cells of these converters are made up of strings of series connected semiconducting elements, such as pairs of Integrated Gate Bipolar Transistors (IGBTs) with antiparallel diodes.

The cells are often used in high voltage applications such as High Voltage Direct Current (HVDC)

applications. In order to enhance the reliability in these systems, redundant semiconducting elements are often used. The normal way to provide redundancy is to provide auxiliary semiconducting elements in each cell, for instance one auxiliary semiconducting element in every cell.

These semiconducting elements are expensive elements, because of their high rated voltages and currents. Furthermore, because of the high voltages used, the number of cells has to be high. It is for instance not unusual with 38 cells in a converter. This means that if every cell is to comprise one auxiliary semiconducting element, the whole converter will have to comprise a lot of auxiliary semiconducting elements, and in the example given above 38 such elements, which makes the converter expensive.

There is therefore a need for lowering the amount of auxiliary semiconducting elements used in a voltage source converter while at the same time retaining a high reliability of the converter.

B. Jakobsson et al . describe in "VSC-HVDC Transmission with Cascaded Two-Level Converters", CIGRE SC B4

Session 2010 (2010) a scalable converter employing cells comprising semiconducting elements that are presspack Integrated Gate Bipolar transistors (IGBTs) . The cell voltage of these cells can be controlled, where this type of control can be used for assigning lower voltages to cells having faulty positions. Cell voltage control is also described in US

2011/0222323. In this document a capacitor voltage is compared with a reference capacitor voltage for

calculating a correction value, which in turn is added to an AC reference voltage of a cell for raising or lowering the AC voltage reference.

However, none of these documents give enough guidance for allowing a reduction in the number of semiconducting elements to be made as compared with auxiliary semiconducting elements in each cell.

There is therefore a need for an improvement when providing redundancy in cell based multilevel voltage source converters .

SUMMARY OF THE INVENTION

The present invention addresses this situation. The invention is thus directed towards improving handling of faulty semiconducting elements in a multilevel voltage source converter.

This is according to one aspect of the invention achieved through a multilevel voltage source converter comprising

a first group of cells connected in cascade between a first DC terminal and an AC terminal for providing a pole voltage V _DC i at the first DC terminal,

where each cell provides a cell voltage V _c and

comprises a first string of series connected

semiconducting elements between one end of a cell capacitor and a first cell terminal, the cell voltage V _c being initially set based on (n-l)*V _S soA _/ where n is the number of semiconducting elements in the first string and V _SSOA is the maximum allowed voltage of a semiconducting element, and

a control unit configured to

control, upon detection of a fault on one semiconducting element in a cell, the cell voltage V _c of this cell to a lower level with a voltage lowering step corresponding to the maximum allowed voltage V _S SO _A of one

semiconducting element, and

control one or more of the other cells of the first group to compensate the cell voltage lowering.

This object is according to another aspect of the invention achieved through a method of handling faulty semiconducting elements of a multilevel voltage source converter comprising a first group of cells connected in cascade between a first DC terminal and an AC terminal for providing a pole voltage V _DC i at the first DC terminal, each cell providing a cell voltage V _c and comprising a first string of series connected

semiconducting elements between one end of a cell capacitor and a first cell terminal, the cell voltage V _c being initially set based on (n-l)*V _S soA _/ where n is the number of semiconducting elements in the first string and V _SSOA is the maximum allowed voltage of a semiconducting element,

the method comprising the steps of

controlling, upon detection of a fault on one

semiconducting element in a cell, the cell voltage V _c of this cell to a lower level with a voltage lowering step corresponding to the maximum allowed voltage V _SSOA of one semiconducting element, and

controlling semiconducting elements of one or more of the other cells of the first group to compensate the cell voltage lowering.

The invention has a number of advantages. It allows the number of redundant semiconducting elements in a group of cells to be kept low. This is due to the fact that it is possible to provide an auxiliary capacity using other cells of the group, instead of providing

auxiliary switching elements in each cell. This also has the advantage of allowing continued operation in more situations when there are faulty semiconducting elements. This thus means that the invention allows the voltages lost because of faulty elements to be replaced independently of in which cell they are provided. BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will in the following be

described with reference being made to the accompanying drawings, where fig. 1 schematically shows a cell-based multilevel voltage source converter according to one variation of the invention for converting between AC and DC

voltages ,

fig. 2 schematically shows one variation of a cell used in a voltage source converter,

fig. 3 shows a chart showing the operating cell voltage of a cell in relation to a maximum allowed cell voltage, and

fig. 4 schematically shows a flow chart of a number of method steps being performed in a control unit of the voltage source converter.

DETAILED DESCRIPTION OF THE INVENTION

In the following, embodiments of the invention will be described . The present invention is directed towards providing a multilevel voltage source converter for converting between AC and DC. This converter may as an example be provided in a converter station linking a Direct

Current (DC) system with an Alternating Current (AC) system, which systems may both be power transmission systems. The DC system can for instance be a High

Voltage Direct Current (HVDC) power transmission system and the AC system may be a Flexible Alternating Current Transmission System (FACTS) . However these types of systems are mere examples of such systems and should not be considered as a requirement. The invention can also be applied in for instance power distribution systems. The converter may also be provided as a part of a back-to-back converter between two AC systems or as part of a DC/DC converter.

Fig. 1 schematically shows a multilevel voltage source converter 10 according to one variation of the

invention for provision in an HVDC converter station.

The converter 10 has a DC side with a first DC terminal Tl for providing a first DC voltage V _DC i and a second DC terminal T2 for providing a second DC voltage V _DC 2 · The first DC voltage is also termed a first pole voltage, while the second DC voltage is termed a second pole voltage. The converter also comprises an AC side with at least one AC terminal T3 for providing an AC

voltage . The converter 10 is cell-based, which means that it comprises a number of cells 14. There is in this embodiment a first group of cells connected in cascade between the first DC terminal Tl and the AC terminal T3. There is here also a first phase reactor LA

connected between the AC terminal T3 and the first group of cells. In the converter there is also a second group of cells connected in cascade between the second DC terminal T2 and the AC terminal T3. There is here also a second phase reactor LB connected between the AC terminal T3 and the second group of cells. The first phase reactor LA and the first group of cells here form a first phase arm, while the second phase reactor LB and the second group of cells form a second phase arm.

The first and second phase arms together form a phase leg that stretches between the two DC terminals Tl and T2. There is normally three such phase legs connected between the two DC terminals, each provided with a corresponding AC terminal. The phase arms may

furthermore be symmetrical to each other in relation to the AC terminal. They may thus have the same amount of cells on both sides of the AC terminal and the same sized phase reactors. Here only one phase leg is shown in order to simplify the description of the invention. It is however possible with for instance two phase arms . Each cell 14 is in this embodiment a half-bridge cell. This means that it is provided with two switches SI and S2 connected in series with each other. The series- connected switches are furthermore connected in

parallel with a cell capacitor. The midpoint between two switches here forms a first cell terminal, while one end of the cell capacitor forms a second cell terminal. In this way either the connection point between the first switch and a first end of the cell capacitor forms the second cell terminal or the

connection point between the second switch and a second end of the cell capacitor forms the second cell

terminal. In the first group of cells, the first cell terminal of a first cell is connected to the first phase reactor LA and the second cell terminal of this cell is connected to the first cell terminal of a following cell. The second cell terminal of this following cell is then connected to the first cell terminal of a next cell. In this way cells are

connected in cascade until the second terminal of the last cell of the first group is connected to the first DC terminal Tl. In the second group of cells, the second cell terminal of a first cell is connected to the second phase reactor LB and the first cell terminal of this cell is connected to the second cell terminal of a following cell. The first cell terminal of this following cell is then connected to the second cell terminal of a next cell. In this way cells are

connected in cascade until the first terminal of the last cell of the second group is connected to the second DC terminal T2.

All the cells in a group are being used in forming DC voltages. The cells each provide a cell voltage that contributes to the pole voltage. The voltage of the cells of a cell arm are selected to provide the voltage VDCI - V _DC 2, which if V _DC i = -V _DC 2 can be the voltage

2*V _DC i . The traditional way is then to divide the pole- to-pole voltage evenly. Each cell of a phase arm, such as the first phase arm, may then have a voltage

2*V _DC i/j, where j is the number of cells in a cell arm. This cell voltage can be controlled. It can be raised or lowered. The nominal cell voltages, i.e. the cell voltages at ordinary steady state operation when all cells are healthy, are furthermore selected in such a way that they are able to have their voltages raised. They collectively provide a voltage margin that may be used for compensating faults.

Finally the converter comprises a control unit 12 configured to control the cells 14. The control is indicated with dashed arrows going from the control unit 12 to all the cells 14.

The basic functionality of the control unit 12 is to control the cells for providing the AC voltage V _AC on the AC terminal T3, which is done through switching the cell switches. This is as such known. According to the invention the control unit also has another function, namely to handle faults occurring in the cells. Fig. 2 schematically shows a cell 14 according to one variation of the invention. The above-mentioned first and second switches are here each made up of a number of series connected semiconducting elements. The semiconducting elements are in this embodiment each in the form of a semiconductor of turn-off type together with an anti-parallel diode. In this example the semiconductor of turn-off type is an Insulated Gate Bipolar Transistor (IGBT) . However, also other types can be used such as Integrated Gate-Commutated

Thyristors (IGCT), Metal-Oxide-Semiconductor Field- Effect Transistors (MOSFET) or BImode insulated Gate Transistors (BIGT) . Furthermore, in this example the first switch is made up of a first string of series connected semiconducting elements Sli, SI ₂ , ... Sl ₇ and Sis connected between the first end of the cell

capacitor and the first cell terminal CTl. The first end of the cell capacitor in this embodiment makes up the second cell terminal CT2. The second switch is made up of a second string of semiconducting elements S2i,

S2 ₂ , S2 ₇ and S2 ₈ connected between the second end of the cell capacitor and the first cell terminal CTl. In this first embodiment there are eight semiconducting elements in the first switch and eight semiconducting elements in the second switch.

The semiconducting elements are furthermore provided using press-pack technique, for instance in the form of so-called StakPak IGBTs, which means that if one element fails it will get short-circuited and thereby allowing the cell to continue to operate. This also means that the semiconducting element is of a fail safe type that, when faulty, forms a safe short circuit state or enters a short circuit failure mode (SCFM) . By that a current can still pass though the remaining elements and operation of the cell can continue.

Fig. 3 schematically shows a chart showing the cell voltage V _c of a cell in relation to a maximum allowed cell voltage n*V _SS oA and a lower level (n-1)* V _{S SOA} , which chart will be used for describing and two current levels Ii and I SSOA - Each semiconducting element in the first string has a highest allowed voltage V _{S SOA} ^ which is a highest allowed voltage in switched operation. This voltage is typically denoted a switching safe operating area (SSOA) voltage. If a higher voltage than this voltage VSSOA is applied over the semiconducting element, it may fail. This voltage has a linear dependency of the current at high current levels. The voltage may have a fixed voltage V _S SOAO up till a current level Ii through the element and at higher current levels V _S SOA may have a linear dependence of the current according to V _S SOA = VSSOAO - g*(I-Il), where g is a constant. This

relationship is then valid up to a current level I SSOA at which the semiconducting element may fail. The area bounded by the voltage n*V _SS oA and current I SSOA is then defined as SSOA a switching safe operating area (SSOA) .

The cell will then be able to operate at n*V _S soA _/ where SSOA may be the average maximum allowed voltage of the cells and n is the number of semiconducting elements in the cell, in this example eight.

According to the invention the cell voltage V _c is initially set based on (n-1 ) *V _{S S} OA, · The cell voltage is thus set to correspond to a lower voltage than the maximum allowed voltage. It may here furthermore be set with a margin m, so that V _c = (N-1)* V _S SOA ^_ m, where the margin as one example can be zero. This will lead to each semiconducting device initially being set to handle a voltage [ (n-1 ) *V _SS oA ^_ ni ] /n in steady state.

However, in transient state each semiconducting device can handle a voltage up to the maximum allowed voltage VSSOA- This means that transiently V ₀ /n cannot be larger than V _S SOA or put differently transiently V _c cannot be larger than n*V _S soA- Therefore the cell has a safety area between the operating cell voltage V _c and n*VSSOA, which may be transiently used. This relationship can also be described as a semiconducting element having a maximum allowed voltage V _{S SOA} is operated at an

operating voltage set based on to n*V _SS oA/ (n-1 ) . in order to be able to transiently handle a higher voltage than in steady state. The cell voltage may therefore be set based on V _S soA*(n-l) . The voltage margin m may furthermore with advantage be selected so that V _c remains below (n-l)*V _SS oA0 in the whole SSOA, i.e. also up to the maximum current I _{S SOA} -

The semiconducting elements of the second string are typically provided and designed in the same way as the cells in the first string. The gates of the semiconducting elements are here furthermore connected to corresponding gate control units 20 that receive a logical gate control signal from the control unit 12 and converts the logical gate control signal to a voltage level suitable for

application on gates of the semiconductors of the semiconducting elements. The gate control units may also receive or obtain failure indications for the semiconducting element, i.e. an indication that the semiconducting element has failed, and forward this indication to the control unit 12 (not shown) . Here it can be seen that the gate control units 20 for the semiconducting elements of the first switch receive the same logical gate-control signal. The gate control units for the semiconducting elements of the second switch also receive the same logical gate-control signal, which however differs from the logical gate control signal provided for the semiconducting elements of the first switch. The cell capacitor here comprises a number of capacitor elements divided into two halves Ci and C2 and the cell also comprises a cell voltage measuring unit 16 provided in parallel with the capacitor. The cell voltage V _c is here made up of a voltage V _C i over the first half Ci and a voltage V _C 2 over the second half C2. The cell voltage measuring unit 16 comprises a cell voltage measuring element 18 and two resistors Rl and R2, each in parallel with a corresponding cell

capacitor half Ci and C2, respectively.

Now the functioning of the invention according to the first embodiment will be described in more detail with reference being made to fig. 1, 2 and 3 as well as to fig. 4, which shows a flow chart of a number of method steps being performed in the control unit 12 of the voltage source converter 10. Initially the cell capacitors are fully charged, meaning that they have a charge for providing a cell voltage V _c = V _C i + _C 2 to contribute to the DC voltage as well as being switchable for using the same voltage to contribute to the AC voltage. This cell voltage is also initially (n-1 ) *VSSOA-m. This means that it is possible to raise the voltage of each cell with at least the maximum allowed voltage V _S SOA of one

semiconducting element. This means that a voltage margin of VSSOA+ΠΙ exists within the cell.

The method will now be described in relation to the first group of cells, i.e. the cells between the AC terminal T3 and the first DC terminal Tl. It should here be realized that a similar type of control will be provided for the second group of cells.

The semiconducting elements are, as was described above, designed so that the cell voltage V _c initially is VSSOA* (n-1 ) -m, so that the voltage applied over each switching element will be [ (n-1 ) *V _S soA~ni] /n in steady state. This is thus the initial cell voltage of all cells when there are no faulty semiconducting elements in any cells. All cells of the first group are thus healthy when this cell voltage is used.

The control unit 12 has a vector K with counters ki for each cell i in the first cell arm, where i is an integer ranging from 1 to x. Such a counter is keeping track on how many times the voltage of a cell has been lowered because of faulty semiconducting elements.

There is thus a counter value for all cells in the first group. The method here starts with the control unit 12 resetting the vector K, such that all the individual vector values are set to zero, step 22.

Thereafter the control unit 12 controls the cells in the first and second group for contributing to the the AC voltage on the AC terminal T3, step 24.

The control unit 12 then continues and investigates if there is any faulty element in the first group of cells, i.e. if any cell has a faulty semiconducting element. A faulty semiconducting element may be

detected through the voltage across it being zero, i.e. through the element being short-circuited, which is typically the case in press-pack IGBTs. With the above mentioned setting of the cell voltage it is possible that a cell may be able to continue functioning even if one semiconducting element becomes faulty, because the remaining healthy semiconducting elements will be able to receive a portion of the voltage earlier applied over the faulty element without exceeding the maximum allowed voltage of the semiconducting elements.

If there is no faulty element, step 26, then the control unit 12 continues to control the cells of the first and second group to contribute to the AC voltage, step 24. The cell voltages are furthermore retained. They remain untouched.

However, in case there is such a faulty semiconducting element in one cell i, step 26, then the control unit 12 proceeds and investigates the counter vector K and if any vector value k is larger than a threshold value TH, here as an example set as three, step 28, then the converter 10 is tripped, step 30. However, if no counter value has reached this threshold, step 28, then the control unit 12 investigates if there is sufficient redundancy, i.e. if there is any voltage margin left in the first group of cells for replacing the DC voltage loss caused by the faulty semiconducting element.

If there is no sufficient redundancy, step 32, the converter 10 is tripped, step 30. However, if there is sufficient redundancy step 32, then the cell voltage V _c of the cell i with the faulty element is controlled to a lower level, step 34, which is typically to a level being the next lower level. The lowering is performed in order to lower the stress on the remaining healthy semiconducting elements of the cell. The cell voltage can here be seen as made up of the voltage

contributions formed by the voltages of the

semiconducting elements. The voltage is thus made up of a number of voltages of semiconducting elements. The lowering is in this variation of the invention a lowering with a voltage lowering step corresponding to a maximum allowed voltage V _SSOA of one semiconducting element. Thereby the remaining healthy semiconducting elements of the cell are again able to withstand an added voltage caused by a failed element.

The control unit 12, then furthermore controls one or more other cell of the first group to compensate for the cell voltage loss, step 36. It thus controls at least one cell to compensate for the lowering of the cell voltage of the faulty cell. The cells chosen for this compensation may furthermore only be healthy cells, i.e. cells without faulty semiconducting

elements. It is also possible that all healthy cells in the first group are selected. This compensation may be performed simultaneously with the cell voltage

lowering. The control unit 12 here also increments the value of the counter ki of cell i having the faulty element, step 38.

The lowering of the cell voltage may be performed through discharging the cell capacitor halves Ci and C ₂ . The discharging is typically performed through turning on the IGBTs in the second switch when there is a current in the direction from the first cell terminal CT1 to the second cell terminal CT2. The charging of the capacitor may in an analogous manner be performed through turning on the IGBTS in the second switch when there is a current in the direction from the second cell terminal CT2 to the first cell terminal CT1. The cell voltage measuring element 18 here measures the cell voltage using the resistors Rl and R2 and reports the measurements to the control unit 12 in order for the control unit 12 to know when to start and stop charging or discharging. The control is typically performed through comparing the measured cell voltage with a cell voltage reference and charging or

discharging the cell capacitor until the cell voltage reference is reached.

Furthermore, a fixed cell voltage reference is given to a cell with a faulty semiconducting element. This means that a cell having a faulty semiconducting element will not be used in the compensation of cell voltage

lowering in other cells. The pole voltage regulation performed by the control unit is thus only performed using cells lacking faulty semiconducting elements.

Thereafter the control unit 12 continues and performs regular AC control, step 24. If then a faulty element is again detected, step 26, the control unit 12

investigates the counters k for all cells and if none is above the threshold, step 28, and there is

sufficient redundancy, step 32 the cell voltage of the faulty cell is lowered, step 34, the lowering

compensated, step 36, and then regular AC control is continued, step 24. If any cell counter is above the threshold TH, step 28, or if the redundancy has been used up, step 32, then the converter is tripped, step 30. As can be seen operation is thus continued, despite faulty elements being detected, until either the auxiliary capacity, the pole voltage margin, has been used up or one cell counter has exceeded the threshold TH. It can thus be seen that the control unit may repeat lowering the cell voltage of a cell based on the detection of further faulty semiconducting elements in this cell. This may then be repeated for this cell until the threshold is reached. This avoids

unnecessarily tripping the converter and therefore the converter may be used longer before having to be serviced than if the converter were to be tripped as soon as a second fault occurs in a cell. It is here possible that two strings of a cell are considered jointly in that the control unit 12 will only lower a cell voltage if a string of a cell, prior to a certain element being detected as faulty in this string, has the same number or more faulty elements than the other string of the cell. This can also be described in the following way. Suppose that the first string has a first faulty semiconducting element and the cell voltage has been lowered because of this first faulty semiconducting element. If now a second

semiconducting element is detected as being faulty in the second string, then no cell voltage lowering is performed because of the earlier performed cell voltage lowering. However, if thereafter a third semiconducting element becomes faulty in the first or second string, then the cell voltage will again be lowered. This means that if more than one semiconducting element in a cell is faulty, the cell voltage is controlled based on the lowest number of healthy semiconducting elements in the first or the second switch.

It is also possible that the detection of a failure of a semiconducting element during the cell voltage lowering is disregarded. It is thus possible that a possible detection of failure of a semiconducting element of a cell when the cell voltage is controlled to a lower level is disregarded. This means that if a semiconducting element is detected as being faulty when the cell is in the process of having its cell voltage being lowered, but before the lower level has yet been reached, then such a fault may be disregarded by the control unit.

The above-mentioned method may also be performed in the same way for the cells in the second group, i.e. for the cells in the second phase arm between the AC terminal T3 and the second DC terminal T2.

The invention has a number of advantages. It allows the number of redundant semiconducting elements in a group of cells to be kept low. This is due to the fact that it is possible to provide the auxiliary capacity through all the healthy cells of the group. This also has the advantage of allowing continued operation in more cases. It is also possible to continue to operate a converter even if more than one semiconducting element in a cell is being faulty. This means that no cell tripping will occur when a single or a few

semiconducting elements fail. This also means that the invention allows the voltages lost because of faulty elements to be replaced independently of in which cell they are provided. Furthermore, no arrester is used to protect the cells.

As no arrester is used the withstand voltage of a cell can be variable and set by the lowest number of healthy semiconducting elements in the first or the second switch of a cell. The withstand voltage of a cell is based on a cell pre-fault voltage and the added voltage in a worst fault case for a blocked converter. On top of that an insulation margin is added according to international standard.

A cell is able to withstand voltage in blocked mode dependent on the number of healthy semiconducting elements.

The cell voltage reference may furthermore be set with a margin to be able to handle fault cases that charge the cell capacitor to higher than normal values. There are number of variations that may be made to the invention apart from those already mentioned.

The cell structure could be changed. The second cell terminal of the half-bridge cell could as an example be provided at the second end of the cell capacitor, i.e. at the connection point between second end of the cell capacitor and the second switch. As yet another

alternative the cells may be full-bridge cells. It is also possible to have the AC voltage control provided separately. It may thus not need to be handled by the control unit shown in fig. 1 but may be taken care of by a separate control unit. For this reason the control unit of the invention may be provided only for handling faulty semiconducting elements in cells. It was earlier described that the cells in the second group could be provided and controlled in the same way. It should be realized that as an alternative they may be provided as traditional cells with fixed cell voltages and with one redundant semiconducting element each.

The threshold was above exemplified as being set to three. It is possible with other values. In one

embodiment of the invention the cell or converter may be tripped if half the semiconducting elements of a string are faulty.

The control unit may be provided as a processor with computer program memory including computer program code instructions causing the computer or processor to perform the functionality of these element and units.

The voltage detecting element may be provided as any conventional voltage detector.

From the foregoing description of different variations of the present invention, it should be realized that it is only to be limited by the following claims.