Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
MULTIPHASE MULTIPLIER
Document Type and Number:
WIPO Patent Application WO/1989/000739
Kind Code:
A1
Abstract:
A multiphase multiplier circuit employs analog switches, each of which is duty controlled for multiplying input voltage signal with a multiplier determined depending on the duty cycle of ON/OFF period. The multiphase multiplier circuit further includes means for multiplying a reference voltage signal by a desired factor for deriving the difference between the product and the factor for controlling duty cycles of the analog switches on the basis of the difference.

Inventors:
Oshima
Kenji, Kito
Yasutami
Application Number:
PCT/JP1988/000705
Publication Date:
January 26, 1989
Filing Date:
July 15, 1988
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
OTIS ELEVATOR COMPANY OSHIMA
Kenji, Kito
Yasutami
International Classes:
H03F3/38; G06G7/161; H03K7/08; (IPC1-7): G06G7/161
Foreign References:
US3588713A1971-06-28
DE1170685B1964-05-21
US3466460A1969-09-09
US3536904A1970-10-27
Download PDF:
Claims:
- 11 -WHAT IS CLAIMED IS:
1. A multiplier circuit comprising: a multiplier including a first analog switch connected an input signal source, said first analog switch being switched ON and OFF according to a controlled duty cycle for multiplying input signal received from said input signal source by a factor corresponding to said duty cycle; a reference multiplier connected to a reference input source and having a second analog switch being switched ON and OFF according to said controlled duty cycle for multiplying a reference input received from said reference input source by a factor corresponding to said duty cycle; and duty cycle adjusting means, recieving the output of said reference multiplier, for comparing the received output of said reference multiplier with a mutiplier indicative signal for feedback controlling said second duty cycle so that said output of said reference multiplier coinsides with said multiplier indicative signal.
2. A multiplier circuit as set forth in claim 1, wherein said multiplier circuit includes an operational amplifier connected to said analog switch for receiving said input signal through said first analog switch, a feedback resistor and a filtering amplifier.
3. A multiplier circuit as set forth in claim 1, wherein said multiplier circuit further includes an input resistor having a resistance cooperative with said feedback resistor for determining mufactor for adjusting multiplier.
4. A multiplier circuit as set forth in claim 1, wherein said duty cycle adjusting means includes means 12 for deriving the difference between the received output of said reference multiplier and a multiplier factor indicative signal to produce a difference indicative signal having a value variable depending upon said difference and means for generating a pulse signal having a pulse width corresponding to the signal value of said difference indicative signal.
5. A multiplier circuit as set forth in claim 1, wherein said pulse generating means comprises a frequency signal source for generating signal of a constant frequency and constant amplitude and a comparator which compares said frequency signal with said difference indicative signal for producing said pulse signal defining said duty cycle.
6. A multiphase multiplier circuit comprising: a plurality of multipliers, each including a first analog switch connected an input signal source, said first analog switch being switched ON and OFF according to a controlled duty cycle for multiplying input signal received from said input signal source by a factor corresponding to said duty cycle; a reference multiplier connected to a reference input source and having a second analog switch being switched ON and OFF according to said controlled duty cycle for multiplying a reference input received from said reference input source by a factor corresponding to said duty cycle; and duty cycle adjusting means, recieving output of said reference multiplier, for comparing the received output of said reference multiplier with a muptiplier factor indicative signal for feedback controlling said duty cycle so that said output of said reference multiplier coinsides with said multiplier factor indicative signal. 13 .
7. A multiplier circuit as set forth in claim 6, wherein each of said multipliers includes an operational amplifier connected to said analog switch for receiving said input signal through said first analog switch, a feedback resistor and a filtering amplifier.
8. A multiplier circuit as set forth in claim 6, wherein each of said multipliers further includes an ' input resistor having a resistance cooperative with said feedback resistor for determining mufactor for adjusting said multiplier.
9. A multiplier circuit as set forth in claim 6, wherein said duty cycle adjusting means includes means for deriving the difference between received output of said reference multiplier and a muptiplier factor indicative signal to produce a difference indicative signal having a value variable depending upon said difference and means for generating a pulse signal having a pulse width corresponding to the signal value of said difference indicative signal.
10. A multiplier circuit as set forth in claim 6, wherein said pulse generating means comprises a frequency signal source for generating a signal having a constant frequency and constant amplitude and a comparator which compares said frequency signal with said difference indicative signal for producing said pulse signal defining said duty cycle.
11. A multiphase multiplier circuit for multiplying a plurality of mutually distinct input signals with by common factor, comprising: a plurality of multipliers, each including a first analog switch connected an input signal source, said first analog switch being switched ON and OFF according to a controlled common duty cycle for multiplying input signal received from said input signal source by a factor corresponding to said duty cycle; a reference multiplier connected to a reference input source and having a second analog switch being switched ON and OFF according to said controlled duty cycle for multiplying a reference input received from said reference input source by a factor corresponding to said duty cycle; and duty cycle ad usting means, recieving output of said reference multiplier, for comparing the received output of said reference multiplier with a muptiplier factor indicative signal for feedback controlling said duty cycle so that said output of said reference multiplier coinsides with said multiplier indicative signal.
Description:
S P E C I F I C A T I O N

MULTIPHASE MULTIPLIER

BACKGROUND OF THE INVENTION

Field of the Invention The present invention relates to a multiphase multiplier circuit for multiplying a plurality of analog voltage signals with a common multiplier value. Description of the Background Art

Conventionally, LOG amplifiers, multiplier IC circuits are known as analog multiplier circuits. Such conventional multiplier circuits amplify analog voltage signals representative of values to be multiplied at mu-factors corresponding to multipliers. These multiplier circuits generally comprise operational amplifiers and operational resistors to provide desired electrical characteristics, such as accuracy in arthimetic operation and response characteristics. On the other hand, such conventional multiplier circuits have complicated circuit constructions which cause them to be relatively high in cost. Therefore, in the case of an apparatus using a plurality of multiplier circuits, it becomes necessary to provide the necessary number of multiplier circuits which causes substantial cost in constructing the circuit. Such a problem may be encountered even in a multiphase multiplier circuit which amplifies a plurality of analog voltage signals with a common mu-factor, since corresponding number of multiplier circuits are required. SUMMARY OF THE INVENTION

Therefore, it is an object of the present invention to provide a multiphase multiplier circuit which has simplified construction.

Another object of the invention is to provide a multiphase multiplier circuit of a simplified construction which can maintain in accuracy performance

construction which can maintain in accuracy performance and response characteristics equivalent to the level of the conventional circuit.

In order to accomplish aforementioned and other objects and advantages, a multiphase multiplier circuit, according to the invention, employs analog switches, each of which is duty controlled for multiplying input voltage signal with a multiplier determined depending on the ON/OFF ratio in duty cycle. The multiphase multiplier circuit further includes means for multiplying a reference voltage signal by a desired factor for deriving the difference between the produce and the factor for controlling duty cycles of the analog siwtches on the basis of the difference. According to one aspect of the invention, a multiplier circuit comprises a multiplier including a first analog switch connected an input signal source, the first analog switch being -switched ON and OFF in a controlled duty cycle for multiplying input signal received from the input signal source by a factor corresponding to the duty cycle; a reference multiplier connected to a reference input source and having a second analog switch being switched ON and OFF according to a controlled duty cycle for multiplying a reference input received from the reference input source by a factor corresponding to the duty cycle; and duty cycle adjusting means, recieving the output of the reference multiplier, for comparing the received output of the reference multiplier with a muptiplier factor indicative signal for feedback controlling the second duty cycle so that the output of the reference multiplier coinsides with the multiplier factor indicative signal.

According to another aspect of the invention, a multi-phase multiplier circuit comprises

- 3 -

a plurality of multipliers, each including a first analog switch connected an input signal source, the first analog * switch b.eing switched ON and OFF according to controlled duty cycle for multiplying input 5 signal received from the input signal source by a multiplier corresponding to the duty cycle; a reference multiplier connected to a reference input source and having a second analog switch being switched ON and OFF according to the controlled 0 duty cycle for multiplying a reference input received from the reference input source by a factor corresponding to the duty cycle; and duty cycle adjusting means, recieving output of the reference multiplier, for comparing the received 5 output of the reference multiplier with a muptiplier indicative signal for feedback controlling the duty cycle so that the output of the reference multiplier coinsides with the multiplier indicative signal.

Each of the multipliers may include an 0 operational amplifier connected to the analog switch for receiving the input signal through the first analog switch, a feedback resistor and a filtering amplifier.

In the preferred construction, each of the multipliers further includes an input resistor having a resistance 5 cooperative with the feedback resistor for determining mu-factor for adjusting multiplier. The duty cycle adjusting means may includes means for deriving the difference between the received output of the reference multiplier and a muptiplier factor indicative signal to 0 produce a difference indicative signal having a value variable depending upon the difference and means for generating a pulse signal having a pulse width corresponding to the signal value of the difference indicative signal. 5 Preferably, the pulse generating means comprises a frequency signal source for generating a a

signal having a constant frequency and constant amplitude and a comparator which compares the frequency signal with the difference indicative signal for producing the pulse signal defining the duty cycle. According to a further aspect of the invention, a multi-phase multiplier circuit for multiplying a plurality of mutually distinct input signals with a common multiplier, comprises a plurality of multipliers, each including a first analog switch connected to an input signal source, the first analog switch being switched ON and OFF according to a controlled common duty cycle for multiplying input signal received from the input signal source by a factor corresponding to the duty cycle; a reference multiplier connected to a reference input source and having a second analog switch being switched ON and OFF according to the controlled duty cycle for multiplying a reference input received from the reference input source by a factor corresponding to the duty cycle; and duty cycle adjusting means, recieving the output of the reference multiplier, for comparing the received output of the reference multiplier with a muptiplier factor indicative signal for feedback controlling the duty cycle so that the output of the reference multiplier coinsides with the multiplier indicative signal. BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be understood more fully from the detailed description given herebelow and from the accompanying drawings of the preferred embodiment of the invention, which, however, should not be taken to limit the invention to the specific embodiment but are for explanation and understanding only.

In the drawings:

Fig. 1 is a circuit diagram of the preferred embodiment of a multiphase multiplier circuit according to the present invention; and

Figs. 2(a) through 2(d) are charts showing waveforms of signals at different components of the preferred embodiment of the multiphase multiplier circuit of Fig. 1. DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to the drawings, Fig. 1 shows the preferred embodiment of a multiphase multiplier circuit according to the invention, which has n-phase multipliers 11, to 1n. The multipliers 11, to 1n have input terminals IN, to IN which are respectively connected to field-effect transistors (FETs) T, to T via input resistors R,, to R, . The FETs T, to T serve as analog switch whose ON/OFF periods are duty controlled.

The FETs T, to T are respectively connected to operational amplifiers A, to A , outputs of which are connected to output terminals OUT, to OUT . The outputs of the operational amplifiers A, to A are also connected to inputs thereof via feedback resistors R„-, to R„ and via filtering capacitors C,, to C, . As seen from Fig. 1, the feedback resistors R„, to R and the filtering capacitors C,, to C, are arranged in parallel to each other.

The preferred embodiment of the multiphase multiplier circuit also includes a reference multiplier 2. Similarly to the multipliers 1, to 1 , the reference multiplier 2 has an input terminal IN which is connected to an operational amplifier A via a series circuit comprising an input resistor R., and a FET T . The operational amplifier A of the reference multiplier 2 has parallel feedback circuits respectively including feedback resistor R. and filtering capacitor C ? . The output of the operational amplifier A is connected to

- 6 -

an output terminal OU connected to a control amplifier

4 which will be discussed herebelow, to feed output of tthhee ooppeerational amplifier A as feedback input for the latter. The control amplifier 4 includes a variable resistor VR connected to the output terminal OUT . The variable resistor VR is, in turn, connected to an operational amplifier A . The operational amplifier A is also connected to an absolute value circuit 3 which receives input K representative of the factor by which for multiplying the input voltages IN, to IN will be multiplied. The absolute value circuit 3 outputs positive polarity signal V. to the input of the operational amplifier A via an input resistor R- . The operational amplifier A C*» has a primary delay capacitor C, and a positive polarity cut diode D. The operational amplifier A is connected to inverting input terminal of a comparator 6. The comparator 6 has a non-inverting terminal connected to a triangular wave generator circuit 5 which generates a negative polarity of triangular wave having constant frequency and constant amplitude. The comparator 6 compares the output of the control amplifier V. with the output of the triangular wave generator circuit 5 to produce a pulse signal Pc having a pulse width corresponding to the level of the output V. of the control amplifier 4. The pulse signal Pc is applied to the source of respective FET T and T, to T for turning the latter ON for a period corresponding to the pulse width of the pulse signal Pc.

The operational amplifier A of the control amplifier 4 operates to determine the level of "the output V. so that at a given balance between the output

Vi.n of the absolute value circuit 3 and feedback in c put Vosc- of the reference multip c lier can be established.

With the circuit construction set forth above,

- 7 -

the input voltages at the input terminals IN, to IN of the multipliers 1, to 1 serve as signals representing values to be multiplied. On the other hand, /the input K of the absolute value circuit 3 serves as a common multiplier. The absolute value circuit 3 outputs the absolute value signal V. corresponding to the input K.

The operational amplifier A receives the output OUT of the reference multiplier 2 generated in response reference in -p ~ ut IN s and the absolute value sig ~ nal V x.n of the absolute value circuit 3. The operational amplifier A compares the inputs and outputs negative polarity signal V. representative of the difference between the output OUT of the reference multiplier 2 and the absolute signal V. of the absolute value circuit 3. The negative polarity signal V. is fed to the comparator 6. The comparator 6 compares the negative polarity signal value with the triangular wave signal of negative polarity input from the triangular signal generator circuit 5 to formulate a pulse signal Pc having a pulse width corresponding to the level of the negative polarity signal Pc. By this pulse signal Pc, duty cycle of the ON/OFF period of the FETs Ts and Ti, to T is controlled.

Figs. 2(a) to 2(d) show waveforms of the signals in the preferred embodiment of the multiphase multiplier circuit of Fig. 1. As seen from Fig. 2(a), the reference input IN for the reference multiplier 2 is held the- voltage level at constant value. On the other hand, the input V. of the control amplifier 4 increases according to increasing of absolute value of the input K as the multiplier.

The output OUT of the reference multiplier 2 is initially held zero. Therefore, difference of the output OUTs of the reference multiplier 2 and the output Vi.n of the absolute value circuit 3 increases,

Therefore, the level of the negative polarity signal V.

- 8 -

of the operational amplifier A is lowered from initial zero level. Since the ON/OFF period of the duty cycle the FET T is determined by the pulse width of the pulse signal Pc of the comparator 6 which increases according to lowering of the level of the negative polarity signal. Therefore, the output OUT •3 increases. When the input K reaches the desired value and is held constant, tthhee oouuttppuutt OOUUTT ooff tthhee rreeffeerreennccee mmuullttiipplliieerr 22 rreepprreesseennttss the product obbttained by multiplying the reference input IINN bbyy mmuullttiipplliieerr KK.. At this time, gain G of the system can be illustrated by:

G = V in IN s = a/1N s < X K

The forgoing equation can be modified when the resistance R of the variable resistor VR is varied, as follows:

G = (Vi.n/'INs) x (R-V_R/R c 5). = (1/IN S ) x w /R 5 ) x K

When gain, e.g. R 2 ,/R,, , is same as the gain (R./R-.) in the reference multiplier 2, the relationship between inputs 1, to 1 and outputs OUT, to OUT becomes the same as that in the reference multiplier 2. For example, the -output OUT, of the multiplier 1, can be illustrated by:

OUT χ = IN 1 x {(1/IN-^ x (R VR /R 5 )} x K

As can be appreciated from the above, of the

FETs T j^ to T n and T as duty controlled the ON/OFF period by the pulse signal Pc perform chopper for obtaining multiplied outputs from the inputs IN, to IN and IN S. The duty. 2 cy- Z cle of these FETs TI, to Tn and Ts is adjusted based on the difference between the output OUT of the reference multiplier 2 and the input K as

the multiplier in feedback manner. By this, the inputs

IN, to IN can be accurately amplified by a mu-factor corresponding to the input K multiplier. Therefore, the shown embodiment of the multiphase multiplier circuit can operate accurately.

In addition, since multipliers 1, to 1 and 2 perform the multiplying operation by chopper operation of the analog switches constituted by FETs T, top T and

Ts', leak current and offset level in each circuit can be kept low held ' small so that accurate multiplying operation become possible for substantially low level inputs. Furthermore, since the FETs T, to T and T as the analog switches are capable of high frequency switching operation, improved response characteristics in multiplying operation can be provided.

Furthermore, the multiplying gain in the preferred embodiment of the multiphase multiplier can be adjusted simply by adjusting the resistance of the variable resistor. ' If necessary, by adjusting the gain of each multiplier which can be done by adjusting resistances of the input resistor and feedback resistor, each of the multiplier can be adjusted independently of the other multipliers. With the construction and operation set forth above, the present invention fulfills all of the objects and advantages sought therefor.

While the present invention has been disclosed in terms of the preferred embodiment in order to facilitate better understanding of the invention, it should be appreciated that the invention can be embodied in various ways without departing from the principle of the invention. • Therefore, the invention should be understood to include all possible embodiments and modifications to the shown embodiments which can be embodied without departing from the principle of the invention set out in the appended claims. For example,

though the shown embodiment of the multiphase multiplier circuit employs the feedback circuit constituted by the control amplifier 4, the triangular wave generator circuit 5 and the comparator 6, for controlling the duty cycle for chopper operation, any circuit constructions of feedback circuit which can accurately adjust duty cycle can be employed. Furthermore, the circuit construction of the multiplier can be modified in any way as long as the capability of ^ chopper operation is maintained.