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Title:
A MULTIPLE CHANNEL CACHE MEMORY AND SYSTEM MEMORY DEVICE
Document Type and Number:
WIPO Patent Application WO/2018/026562
Kind Code:
A1
Abstract:
A high performance, low power, and cost effective multiple channel cache-system memory system is disclosed.

Inventors:
LEE, Sheau-Jiung (20792 Saint Joan Court, Saratoga, CA, 95070, US)
Application Number:
US2017/043556
Publication Date:
February 08, 2018
Filing Date:
July 24, 2017
Export Citation:
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Assignee:
TSVLINK CORPORATION (24044 Jabil Lane, Los Altos Hills, CA, 94024, US)
International Classes:
H03M9/00; G06F13/14; H04L27/36; H04L27/38
Foreign References:
US20150312070A12015-10-29
US20140215245A12014-07-31
US20090307406A12009-12-10
Attorney, Agent or Firm:
YAMASHITA, Brent (DLA Piper LLP US, 2000 University AvenueEast Palo Alto, CA, 94303, US)
Download PDF:
Claims:
CLAIMS

What is claimed is:

1. A computing device comprising:

a first chip comprising one or more CPU cores, a memory controller coupled to the one or more CPU cores, and a first serializer-deserializer device;

a second chip comprising cache memory managed by the memory controller, a data router, and a second serializer-deserializer device;

system memory separate from the first chip and the second chip and managed by the memory controller; and

an analog interface coupled to the first chip and the second chip, wherein the first serializer-deserializer device and the second serializer-deserializer device exchange data over the interface using quadrature amplitude modulation;

wherein a memory request from the one or more CPU cores is serviced by the memory controller and the data router by providing data to the one or more CPU cores from the cache memory or the system memory.

2. The computing device of claim 1, wherein the memory controller is coupled to the one or more CPU cores with a processor bus.

3. The computing device of claim 2, further comprising a system bus coupled to the memory controller.

4. The computing device of claim 3, wherein the system bus is coupled to one or more graphics processor unit (GPU) cores.

5. The computing device of claim 4, wherein the memory controller comprises an arbiter for managing control of the analog interface.

6. A computing device comprising:

a first chip comprising one or more CPU cores, a memory controller coupled to the one or more CPU cores, and a first serializer-deserializer device;

a second chip comprising cache memory managed by the memory controller, a data router, and a second serializer-deserializer device;

system memory separate from the first chip and the second chip and managed by the memory controller;

an analog interface coupled to the first chip and the second chip, wherein the first serializer-deserializer device and the second serializer-deserializer device exchange data over the interface using quadrature amplitude modulation; and

a bus between the memory controller and the data router, wherein the bus transfers command and address information in a multiplexed fashion;

wherein a memory request from the one or more CPU cores is serviced by the memory controller and the data router by providing data to the one or more CPU cores from the cache memory or the system memory.

7. The computing device of claim 6, wherein the memory controller is coupled to the one or more CPU cores with a processor bus.

8. The computing device of claim 7, further comprising a system bus coupled to the memory controller.

9. The computing device of claim 8, wherein the system bus is coupled to one or more graphics processor unit (GPU) cores.

10. The computing device of claim 9, wherein the memory controller comprises an arbiter for managing control of the analog interface.

11. A method for reading data in a computing device, the computing device comprising a first chip, a second chip, and system memory, the first chip comprising one or more CPU cores, a memory controller coupled to the one or more CPU cores, and a first serializer- deserializer device, the second chip comprising cache memory managed by the memory controller and a second serializer-deserializer device, the method comprising:

receiving, by the memory controller, a read request from the one or more CPU cores for data associated with an address;

determining that the data associated with an address is stored in the cache memory; obtaining the data associated with an address from the cache memory;

modulating, using the second serializer-deserializer device, the data associated with an address using quadrature amplitude modulation to generate an analog signal;

transmitting the analog signal from the second chip to the first chip over an analog interface;

demodulating the data, using the first serializer-deserializer device;, to generate the data associated with an address; and

sending the data associated with an address to the one or more CPU cores in response to the read request.

12. The method of claim 11, wherein the modulating step comprises:

converting the data associated with an address into an intermediate analog signal;

modulating the intermediate analog signal using a plurality of quadrature amplitude modulators; and summing the output of the plurality of quadrature amplitude modulators to generate the analog signal.

13. The method of claim 12, wherein the demodulating step comprises:

applying a gain to the analog signal to generate an amplified analog signal;

demodulating the amplified analog signal using a plurality of quadrature amplitude modulators;

filtering the demodulated signal using low-pass filters; and

converting the filtered data into the data associated with an address.

14. A method for reading data in a computing device, the computing device comprising a first chip, a second chip, and system memory, the first chip comprising one or more CPU cores, a memory controller coupled to the one or more CPU cores, and a first serializer- deserializer device, the second chip comprising cache memory managed by the memory controller and a second serializer-deserializer device, the method comprising:

receiving, by the memory controller, a read request from the one or more CPU cores for data associated with an address;

determining that the data associated with an address is stored in the cache memory; receiving, by the second chip, a command and address from the first chip over a multiplexed bus for commands and addresses;

obtaining the data associated with an address from the cache memory;

modulating, using the second serializer-deserializer device, the data associated with an address using quadrature amplitude modulation to generate an analog signal;

transmitting the analog signal from the second chip to the first chip over an analog interface; demodulating the data, using the first serializer-deserializer device;, to generate the data associated with an address; and

sending the data associated with an address to the one or more CPU cores in response to the read request.

15. The method of claim 14, wherein the modulating step comprises:

converting the data associated with an address into an intermediate analog signal;

modulating the intermediate analog signal using a plurality of quadrature amplitude modulators; and

summing the output of the plurality of quadrature amplitude modulators to generate the analog signal.

16. The method of claim 15, wherein the demodulating step comprises:

applying a gain to the analog signal to generate an amplified analog signal;

demodulating the amplified analog signal using a plurality of quadrature amplitude modulators;

filtering the demodulated signal using low-pass filters; and

converting the filtered data into the data associated with an address.

Description:
A MULTIPLE CHANNEL CACHE MEMORY AND SYSTEM MEMORY DEVICE

PRIORITY CLAIM

[0001] This application claims priority to U.S. Provisional Application No. 62/369,597, filed on August 1, 2016, and titled "Multiple Channel Cache Memory and System Memory Device Utilizing a Pseudo Multiple Port for Commands and Addresses and A Multiple Frequency Band QAM Serializer/De-Serializer for Data," which is incorporated herein by reference.

TECHNICAL FIELD

[0001] A high performance, low power and cost effective multiple channel cache

memory/system memory is disclosed.

BACKGROUND OF THE INVENTION

[0002] The performance of both cache memory and system memory is critical in high

performance computing systems containing multiple cores processors or multiple processors, particularly systems using additional hardware accelerators such as graphics processing units (GPUs). These computing systems increasingly not only perform general purpose computing but also perform deep machine learning and large data mining.

[0003] To handle the demands placed on the computing system, the memory systems need to be optimized for memory access latency and memory bandwidth at the same time. In order to optimize memory access latency and memory bandwidth on the same computing system, one must increase cache performance as well as reduce the frequency of memory collisions on the buses.

[0004] Prior art approaches have included increasing cache performance by integrating a large cache RAM on the same silicon as the processor cores it is servicing. However, this approach is limited due to the cost of large size RAM.

[0005] Other prior art approaches have used large off-chip RAM located on different silicon than the processor cores it is serving. However, this approach requires a large number of connection pins between the RAM chip and the processor core chip, and the system design cost become unfavorable.

[0006] Another prior art approach is a "brute force" approach that increases memory bandwidth by increasing the bus width and clock rate of the memory bus. However, under this approach, memory requests from different memory masters of the system can easily collide when the system has multiple hardware accelerators.

[0007] Another prior art approach is a multiple concurrent memory channel, which is the most effective solution to maintain a high effective memory bandwidth and support the high bandwidth to multiple hardware accelerators. The limitation of this approach is that once again you need a large number of interface connection pins between the processor chip and the RAM chip. Using a large number of connection pins increases the cost, size, and manufacturing complexity of the chips.

[0008] The prior art also includes multiple approaches for transmitting data from one chip to another chip. In U.S. Patent 9,369,318, titled "Scalable Serial/De- serial I/O for Chip-to-Chip Connection Based on Multi Frequency QAM Scheme," which is incorporated by reference herein and which shares an inventor with this application, an embodiment of a

serializer/deserializer ("SerDes") was disclosed.

[0009] This prior art technique is shown in Figure 5. Serializer 530 and deserializer 540 typically are located on different chips and are connected by I/O interface 510. Serializer 540 receives parallel digital data, in this example shown as eight bits, DO to D7. The data is converted into analog form by digital-to-analog 2-bit converters 501, 502, 503, and 504. Each analog output from the digital-to-analog 2-bit converters 501, 502, 503, and 504 is coupled to QAM mixers. Output from DAC 501 is received at the QAM I channel at mixer 505, which also receives a 90 degree out-of-phase modulation carrier F1_I. Output from DAC 502 is received at the QAM I channel at mixer 506, which also receives a 90 degree out-of-phase modulation carrier F1_Q. Mixers 505 and 506 are both associated with QAM modulator 524. Similarly, output from DAC 503 is coupled to mixer 507 which also receives 90 degree out-of-phase modulation carrier F2_I, while output from DAC 504 is received at mixer 508 which also receives 90 degree out-of-phase modulation carrier F2_Q. Mixers 507 and 508 are both associated with QAM modulator525. Outputs from the mixers of both QAM modulators 524 and 525 are summed at adder 509 and output over I/O interface 510 from the chip containing serializer 530. Through this modulation process, the parallel input is thus serialized into a series output as an analog signal.

[0010] The analog signal over I/O connection 510 is received by deserializer 540 in a second chip. Deserializer 540 preferable includes amplifier 511 which receives the signal and provides a gain stage to compensate for loss in the low pass filter. The amplified signal is provided to mixers 512 and 513 in a first QAM demodulator 526, which receives 90 degree out-of-phase modulation carriers F1_I, F1_Q, respectively, and to mixers 514 and 515 in a second QAM demodulator 527, which receives the amplified signal as well as 90 degree out-of-phase modulation carriers F2_I, F2_Q. Four analog signal channels are output from mixers 512, 513, 514, and 515 to low pass filters 516, 517, 518, and 519, respectively. The low pass filters may be of any desired configuration and order (i.e., 2nd order, 3rd order and so forth). Output from low pass filters 516, 517, 518, and 519 is received by two-bit analog-to-digital converters (ADC) 520, 521, 522, and 523, respectively, which output the digital data. Through this demodulation process, the analog serial input is thus deserialized back to a parallel digital output. Typically, each chip will contain serializer 530 and deserializer 540, such that either chip can send data and either chip can receive data.

[0011] Thus, in the prior art system of Figure 5, an 8 bit parallel input is serialized by two frequency bands of QAM 16 to one I/O interface in a first chip, sent to a second chip, and then deserialized in the second chip by two frequency bands of QAM 16 demodulation back into the original parallel data. It should be appreciated that other configurations can be used, such as using 16 bits of parallel data and four frequency bands of QAM 16 or two frequency bands of QAM256. To date, the SerDes design of Figure 5 has not been used in a memory system.

[0012] The prior art includes other techniques for maximizing the amount of information that can be transmitted over a given channel. U.S. Patent 5,206,833, titled " Pipelined Dual Port RAM," which is incorporated by reference herein and which shares an inventor with this application, introduced a technique of a pseudo multiple port memory. This prior art technique is shown in Figure 6. Devices 601 and 602 each output data, which is received by multiplexor 603. Multiplexor 603 is controlled by an arbitration signal. Multiplexor 603 combines the data from devices 601 and 602 into a single channel, as shown. In one embodiment, device 601 is given priority over device 602, and the data from device 602 is output from multiplexor 603 only when device 601 is in a lull. This effectively creates a pseudo-multiple port device even though in reality only one port exists. To date, this technique has not been used in handling command and address data in a memory system.

[0013] What is needed is a new architecture for cache memory and system memory that allows multiple memory channels that can operate concurrently while also optimizing memory access latency and memory bandwidth without adding a large number of additional pins between a processor chip and a memory chip.

SUMMARY OF THE INVENTION

[0014] The embodiments described herein comprise a cache memory and system memory architecture that utilizes the SerDes technique for the data bus and the pseudo-multiple port technique for the command/address bus, resulting in multiple channel, concurrent cache-system memory. The proposed multiple channels of cache-system memory results in good cache performance as well as good system memory performance.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 depicts an embodiment of a computing device utilizing an improved cache memory and system memory architecture.

[0016] Figure 2 contains a block diagram of a quad channel of an embodiment utilizing the improved cache memory and system memory architecture.

[0017] Figure 3 depicts an exemplary timing diagram for a bus between a processor chip and cache memory chip utilized in the improved cache memory and system memory architecture.

[0018] Figure 4 depicts a prior art memory system. [0019] Figure 4B depicts a block diagram of an embodiment utilizing the improved cache memory and system memory architecture.

[0020] Figure 5 depicts a prior art serializer and deserializer.

[0021] Figure 6 depicts a prior art pseudo-multiple port device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Figure 1 depicts an embodiment of computing device 100 comprising a 4-channel concurrent cache- system memory system. Computing device 100 comprises system-on-chip processor (labeled as "SOC") 110, which contains last level cache and system memory controller (labeled as "LLC/DRAM controller") 104. SOC processor 110 is coupled to cache system chip 120, which is separate from SOC processor 110.

[0023] Cache system chip 120 integrates multiple channels of cache RAM and legacy PHY to connect different type of system memory. Cache system chip 120 comprises data router 127 that regulates the traffic between cache system chip 120, system memory bus 117, and processor cache bus 129. Cache system chip 120 further comprises cache memory arrays 126a...126j (where j is an integer, such as 4) and legacy physical interfaces (PHY) 128a...128d (where d is an integer, such as 4) to connect cache system chip 120 to system memory 130 such as LPDDR, DDR, GDR, HBM, HMC etc. In this example, cache memory arrays 126 comprise four arrays of 4 MB each. One of ordinary skill in the art will understand that the example of Figure 1 can be expanded to include additional memory channels and larger cache RAM size depending the target performance and complexity of the system-on-chip.

[0024] SOC processor 110 further comprises CPU cores 101a... lOli (where i is an integer, such as 2 or 4), each of which is coupled to an LI cache memory system 102a...102i, each of which in turn is coupled to L2 cache memory system 103. L2 cache memory system 103 is coupled to LLC/DRAM controller 104 (specifically, to last level cache controller 105) over processor cache bus 129. Here, LLC or last-level cache refers to the last level of cache memory utilized by CPU cores 101a... lOli, such as L3 or L4 (the latter of which would require another level of cache memory between L2 cache memory 103 and last level cache controller 105).

[0025] SOC processor 110 further comprises graphics processor unit (GPU) cores 115a...115k (where k is an integer), each of which is coupled to shared GPU cache memory system 116.

[0026] SOC processor 110 further comprises system bus 117, to which the following devices are coupled: shared GPU cache memory system 116, Serial MFI SerDes controller 118, bus bridge 121, display engine 123, DSP video multimedia processor 124, and SOC processor 110. Serial MFI SerDes controller 118 is also coupled to Serial MFI SerDes 119, which in turn connects to external devices 140 such as a solid state drive or hardware accelerator. Bus bridge 121 is coupled to PCIe (PCI Express) controller 122, which in turn is coupled to Legacy Phy 125. Display engine 123 also is coupled to Legal Phy 125, which in turn connects to I/O ports 150, such as USB, Ethernet, and HDMI ports.

[0027] LLC/DRAM controller 104 further comprises last level cache (LLC) controller 105, quad channel memory arbiter 106, MFI SerDes 107, DRAM controller 108, and MFI SerDes 109. Quad channel memory arbiter 106 is coupled to system bus 117.

[0028] As shown in Figure 1, it is likely that a system will have multiple hardware accelerators and memory masters. A multiple memory channel can reduce the probability of memory requests colliding and can achieve a high sustained memory bandwidth. If two memory requests do collide at a particular memory channel, then memory arbiter 106performs request arbitration to grant the service to a specific memory master based on the arbitration algorithm. [0029] Figure 2 contains additional details regarding the quad-channel concurrent cache memory/system memory system of computing device 100. Processor cache bus 129 and system bus 117 are depicted. System memory bus 117 is connected to quad channel memory arbiter 106, which in turn is coupled to system memory controller 108, SerDes 107, and pseudo multi- port CMD/ADR 205a, 205b, 205c, and 205d. Processor cache bus 129 is coupled to LLC Tag 206, which in turn is coupled to LLC controller 105, SerDes 107, and pseudo multi-port CMD/ADR 204a, 204b, 204c, and 204d. .. Pseudo multi-port CMD/ADR 204, 204b, 204c, 204d, 205a, 205b, 205c, and 205d are coupled to cache system chip 120, specifically, to system CMD/ADR interface 202a, 202b, 202c, and 202d. SerDes 107 is coupled to cache system chip 120, specifically, to SerDes interface 201a, 201b, 20c, 201d, 203a, 203b, 203c, and 203d. Data router 127 is coupled to Legacy Phy 128a, 128b, 128c, and 128d, which in turn are coupled to system memory 130.

[0030] In Figure 2, the memory requests are asserted not only by memory masters on system memory bus 117 but also by last level cache 105 when there is a cache miss. That is, for a particular memory request, LLC controller 105 will first check the last level cache memory for the data. If the data is not present in the last level cache memory or if the data is stale, that will be considered a cache miss, and the request will be forwarded to cache system chip 120. The data path for memory access will be arranged by data router 127 in cache memory chip 120 for various bus conditions. Once arbiter 106 decides which memory master to serve, the bus request is forwarded to the system memory controller 108. The state machine inside system memory controller 108 will issue the correct sequence of command and address to system memory 130.

[0031] When arbiter 106 forwards a request to system memory controller 108, it also needs to forward the same memory request to the last level cache (LLC) TAG 206, for snooping comparison if the memory request is on cacheable exchange memory region. If there is a snooping hit, data router 127 in the cache memory chip 120 must perform the data path re-route from the fast cache RAM 126a...126j instead of the relatively slow system memory 130.

[0032] The SOC processor 110 accesses memory concurrently to other system memory masters when the processor memory request is a cache hit. But when there is a cache miss, the LLC TAG 206 must forward the processor memory request to the arbiterl06, and the arbiter 106 grants system memory bus 117 to LLC TAG 206. Once this cache miss cycle is executed, the data router 127 in the cache memory chip 120 must perform data path re-outing.

[0033] Table 1 shows how data router 127 within the cache memory chip 120 performs routing for all possible cycles:

TABLE 1

Cache flush idle idle Write to system memory miss

idle Snooping read hit, LLC RAM to system bus idle

(inclusion miss, LLC

clean)

idle Snooping read hit, LLC RAM to system bus Updated by LLC RAM

(inclusion miss, LLC

dirty)

Idle Snooping read hit Upper cache to system idle

(inclusion hit, clean) memory bus

idle Snooping read hit Snooping read hit Updated by upper cache

(inclusion hit, dirty) (inclusion hit, clean)

Idle Snooping write hit Write to LLC RAM idle

(inclusion miss,

clean)

idle Snooping write hit Write to LLC RAM idle

(inclusion miss, dirty)

Idle Snooping write hit Upper cache invalidate, idle

(inclusion hit, clean) Write to LLC RAM

idle Snooping write hit Flush from upper cache, Flush from upper cache,

(inclusion hit, dirty) Read- modify- write read to LLC RAM

[0034] In this embodiment, data router 127 in cache memory chip 120 must perform the memory data path routing described in the Table 1. [0035] Utilizing the SerDes architecture can reduce the number of pins required for the data bus between the SOC processor 110 and cache memory chip 120 as shown in Figure 2. But the SerDes design cannot be used for the command and address bus because the latency of a half- duplex SerDes degrades the memory performance. A full duplex SerDes can solve the latency problem but the cost of doubling the pin number simply defeats the advantage of SerDes as compared to a parallel bus.

[0036] When the system memory bus 117 transfers the data in the fixed burst length transfer, one can observe the idle cycles between consecutive commands and addresses on the bus. In a typical memory design, the burst length is a fixed burst of 4 or 8 for each memory access. The choice of burst length for memory bus is to synchronize the processor cache line size and DRAM fixed burst length.

[0037] For the case of memory burst length is 8, the fastest consecutive command and address will be no earlier than the 8th clock. Figure 3 shows timing sequence of the interface bus between processor and cache RAM chip with a pipeline latency for the memory array is 2-1-1-1- 1-1-1-1.

[0038] The first command/address is asserted by memory master 0 at 1st clock. The memory array returns 8 consecutive data starting at 2nd clock and ending at 9th clock. As shown in the Figure 3, the fastest next consecutive command address by the memory master 0 is at 9th clock after issuing the command address at 1st clock. That is to say, between 1st clock and 9th clock, the command/address bus is idle to memory master 0 and is available for other memory masters to issue the command address to the same bus. Thus, other memory masters can perform "cycle stealing" from the idle command address bus. Through this type of cycle stealing on a single command address bus, one can support multiple memory channels on a single command address bus without multiple dedicated command address bus to each memory channel. Figure 3 shows the memory burst length of 8 can support up to 8 concurrent memory channel command address cycles on a single command address bus.

[0039] Because the memory array architecture consists of a row and column decoder, further reduction of the command and address bus protocol can be achieved without performance degradation. A cache memory chip 120 typically consists of SRAM where one can decode a column address later than the row address without slowing down the memory access. Therefore, an SRAM command address bus protocol can strobe the row address at a rising clock edge and strobe the column address at a falling edge. In this way, one can reduce the number of address signals by half.

[0040] The command address bus protocol to cache RAM chip 120 consists of two sets of command address protocol, namely, one to cache RAM and the other to legacy system memory. Data router 127 must re-route the data between the cache RAM 126a...126j and system memory 130 as described in Table 1, whenever there is a cache miss or a snoop hit. Thus, in the command to cache RAM chip, one must include the instruction to the data router 127 as to how to re-route the memory data.

[0041] The four separated cache RAM command address bus shown in the Figure 2 can be implemented by a single command address bus based on fixed burst length cycle stealing technique described above. That is, a single command address bus performs as a pseudo multiple port of memory command address bus. The four legacy system memory command can also reduce to a single command address bus like a cache RAM command address bus.

[0042] High-level differences between the design of the prior art and these embodiments is shown in Figures 4 A and 4B. [0043] In Figure 4A, a prior art system 400 is shown, where a processor SOC 410 contains a last-level cache 420, and the SOC 410 interfaces to system memory 430 (e.g., a DRAM chip) over numerous data pins 440 and command/address pins 450. Increasing the size of the last- level cache 420 would improve the cache hit rate. However, the SOC semiconductor process is relatively expensive, so using a larger last-level cache 420 on the SOC 410 would be expensive.

[0044] In Figure 4B, computing device 100 is shown, where processor SOC 110 interfaces to a cache-system memory 120 over a SerDes interface 112 and a command/address interface 410. The cache-system memory module 120 comprises last-level cache memory 126a...126j as well as system memory 128a...128d and 130. Because the last-level cache is on a separate chip from the SOC, the last-level cache can be made larger than in Figure 4A because the cache-system memory module can be manufactured with a cheaper semiconductor process. Typically, an SOC is manufactured with around 11 metal layers, whereas a memory chip can be manufactured with around 6 metal layers.

[0045] Another benefit of the embodiment shown in Figure 4B is that no pins are required between the SOC and system memory. Those pins typically require substantial power and also require termination circuitry.

[0046] In summary, we describe an invention for multiple channel concurrent cache RAM and system memory based on a short latency SerDes and a pseudo multiple port command address bus. The invention not only reduces the number of interface pin between processor and memory system for multiple memory channel for cost competitive manufacturing but also maintains high memory performance of short latency and high concurrency.