Title:
MULTIPLE CHANNEL MEMORY SYSTEM
Document Type and Number:
WIPO Patent Application WO/2022/115167
Kind Code:
A3
Abstract:
A system including a memory controller chiplet having a memory interface that is configured to couple the memory controller chiplet to first and second memory devices. The memory interface includes first and second memory channels having respective data widths, and configured to couple first and second I/O interfaces of the memory controller chiplet to an interface of the first memory device having a data channel width at least equal to the combined first and second memory channel widths, where the first and second memory channels have independent command/address (CA) paths; and third and fourth memory channels having respective data widths, and configured to couple third and fourth I/O interfaces of the memory controller chiplet to an interface of the second memory device having a data channel width at least equal to the combined third and fourth memory channel widths, wherein the third and fourth memory channels have independent CA paths.
Inventors:
BREWER TONY M (US)
PATRICK DAVID (US)
HORNUNG BRYAN (US)
PATRICK DAVID (US)
HORNUNG BRYAN (US)
Application Number:
PCT/US2021/053812
Publication Date:
August 25, 2022
Filing Date:
October 06, 2021
Export Citation:
Assignee:
MICRON TECHNOLOGY INC (US)
International Classes:
G06F12/02
Domestic Patent References:
| WO2020117700A1 | 2020-06-11 | |||
| WO2020190369A1 | 2020-09-24 | |||
| WO2020176291A1 | 2020-09-03 |
Foreign References:
| US20200226094A1 | 2020-07-16 | |||
| US20190163565A1 | 2019-05-30 |
Attorney, Agent or Firm:
PERDOK, Monique M. et al. (US)
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