Title:
MULTIPLE CPU UNIT
Document Type and Number:
WIPO Patent Application WO/2000/000903
Kind Code:
A1
Abstract:
A plurality of CPU units are used for multiple CPU control. Each CPU unit includes a device memory for processing device data, a shared memory for reading data from and writing data onto the CPU unit and other CPU units, an OS describing the procedure of transferring data, and a microprocessor for transferring data between its own CPU unit and other CPU units according to the procedure described in the OS. Each microprocessor fetches the device data stored in the shared memory of other CPU units into the device memory of its own CPU unit.
Inventors:
YOSHIDA MASATOSHI (JP)
YABUSAKI TATSUMI (JP)
YABUSAKI TATSUMI (JP)
Application Number:
PCT/JP1998/002939
Publication Date:
January 06, 2000
Filing Date:
June 30, 1998
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
YOSHIDA MASATOSHI (JP)
YABUSAKI TATSUMI (JP)
YOSHIDA MASATOSHI (JP)
YABUSAKI TATSUMI (JP)
International Classes:
G06F15/17; (IPC1-7): G06F15/16
Foreign References:
| JPH04358204A | 1992-12-11 | |||
| JPS588307A | 1983-01-18 | |||
| JPH03129457A | 1991-06-03 | |||
| JPH01297759A | 1989-11-30 | |||
| JPS59229663A | 1984-12-24 | |||
| JPH1021159A | 1998-01-23 | |||
| JPH09319410A | 1997-12-12 | |||
| JPH08202672A | 1996-08-09 | |||
| JPH0473253U | 1992-06-26 | |||
| JPH0358163A | 1991-03-13 |
Other References:
HIROAKI TAKEMURA, SHINJI MURAYAMA, NAOAKI IKENO, "Development of SYSMAC LINK System (in Japanese)", OMRON TECHNICS, Vol. 31, No. 3, 1991, pages 207-212.
Attorney, Agent or Firm:
Soga, Michiteru (Kokusai Building 8th floor, 1-1, Marunouchi 3-chom, Chiyoda-ku Tokyo, JP)
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