TECHNICAL FIELD

[0001] The present invention relates to electrical circuits.

More specifically, the present invention relates to an N-path filter using a transconductance that is a sum of multiple transconductances .

BACKGROUND OF THE INVENTION

[0002] It is well known, to those familiar in the art of

filter design, that greater attenuation of in band blockers can be achieved by cascading multiple stages of filtering. An example of this would be cascading two or more RC filters to achieve greater filtering.

[0003] For charge domain filters, this can be done by

cascading two or more stages of filtering, where each stage uses the same structure as in Figure 3.

[0004] There are two problems associated with cascading

charge domain filters :

1) Cascading leads to more hardware and greater silicon area. Particularly costly are additional resettable integrators, especially if the make use of active integrators.

2) In a single stage of charge domain filtering current is integrated onto the capacitor in the resettable integrator forming a voltage across that capacitor. The larger the signals integrated on to the capacitor, the higher the voltage across the

capacitor, and the poorer the linearity. Even though adding a second stage of filtering helps to attenuate these large undesired signals, the damage due to reduced linearity has already occurred.

The more filtering that can be achieved before the conversion to voltage in the resettable integrator, the better the linearity achieved. In other words, for identical filtering cascading two charge domain filters will, in practice, result in poorer linearity performance compared to a case where the additional filtering were achieved in a single stage.

SUMMARY OF THE INVENTION

[0005] The present invention provides circuits and methods related to charge domain filters. A time varying current distributor produces multiple time varying current outputs which are received by filter elements. The outputs of the filter elements are received by a selector components which selects one of the filter outputs for its output. The time varying current distributor has multiple transconductance circuits, each of which produces time varying currents which are proportional to a distributor input. The

transconductance circuits are composed of

transconductance sub-circuits, each of which produces time varying currents, each of which is offset from other time varying currents by a predetermined time interval .

[0006] In one aspect, the present invention provides a

circuit comprising:

- a distributor component receiving an input and producing a plurality of time varying current outputs - a plurality of filter elements, each filter element receiving an output of said distributor component

- a selector component for producing an output of said circuit, said selector component receiving output of said filter elements, said selector component

selecting which of said plurality of filter elements will have its output as part of said output of said circuit wherein

- said distributor component comprises a plurality of transconductance circuits,

- each of said plurality of transconductance circuits comprises at least two transconductance sub-circuits,

- each of said transconductance sub-circuits producing a time-varying current such that for each of said at plurality of time varying current outputs of said distributor, said time varying current output is a sum of at least two of said time varying currents from said sub-circuits,

- said input being sent to each of said

transconductance circuits, at least one of said transconductance circuits being selected such that an output of a selected transconductance circuit is sent to one of said plurality of filter elements. In another aspect, the present invention provides a time varying current (TVC) distributor for

distributing a plurality of currents, each of said currents being based on an input, said TVC distributor comprising : a plurality of transconductance circuits, each of said transconductance circuits producing one of said plurality of currents, each of said plurality of currents being proportional to said input in a time varying manner wherein each of said plurality of currents is offset by a predetermined time interval from other ones of said plurality of currents; each of said plurality of transconductance circuits comprises at least two transconductance sub-circuits, each of said transconductance sub-circuits producing a time-varying current such that for each of said plurality of currents, said current is a sum of at least two of said weighted currents.

BRIEF DESCRIPTION OF THE DRAWINGS ] The embodiments of the present invention will now be described by reference to the following figures, in which identical reference numerals in different figures indicate identical elements and in which:

FIGURE 1 illustrates an N-Path filter with 5 paths;

FIGURE 2 shows a typical 3-path charge domain filter;

FIGURE 3 illustrates the use of active resettable integrators ;

FIGURE 4 illustrates the use of passive resettable integrators ; FIGURE 5 illustrates one example embodiment of the invention; and

FIGURE 6 illustrates a timing diagram for use with the circuit illustrated in Figure 5.

DETAILED DESCRIPTION OF THE INVENTION

[0009] An N-path filter is a filter which comprises:

- a distributor responsive to a common filter input to periodically distribute an input signal in turn to N path-filters,

- N path-filters responsive in turn to the N outputs of the distributor to filter the sequence signals coupled into them

- a selector for coupling each path-filter output in turn to a common output.

[0010] The distributor in an N-path filter accepts a common input signal and distributes time shifted samples of the common input to each of the path filters . An example with 5 paths is shown in Figure 1. In this example, the input signal in is distributed to 5 path- filters PF1 PF2 and so on to PF5. The 5-path filter does this by periodically closing each switch

connected to each path-filter in sequence .

Specifically, the switch connected to the first path- filter PF1 closes for some predetermined interval then the switch connected to PF2 closes for some

predetermined interval and so on until the input has been connected to all 5 path-filter inputs. This series of switches closed in sequence provides the time shifted samples of the common input to each path filter. Then the sequence repeats periodically by first closing the switch connected to PF1 again. Each of the signal distribution switches can be closed with approximately a 20% duty cycle.

[0011] Whether these signal distribution switches should be break-before-make or make-before-break depends on circuit level details. For example, the signal distributor samples voltage onto 5 capacitors, one for each path-filter input, the switches might be designed to be break-before-make (non-overlapping) to avoid shorting the input capacitors together. If the input signal is a current, to be transferred to each path- filter input during the time that the switch is on and the switches are MOS devices, then the switches might be designed to be make-before-break (overlapping) to reduce charge injection or other second order effects.

[0012] As a result, each of the path filters (for example a switched capacitor filter) can be clocked at a lower rate. If the period of input selection switch is close to the frequency of a desired passband, the N-Path filter can provide a bandpass filter even with low pass or continuous time filters in each path-filter. For discrete time path filters, a clock with the same period as the clocks for the distribution switches can be used to clock the path-filters.

[0013] It should be noted that the technique described above and illustrated in the Figures may also be used in implementing the invention as well as the other circuits and devices discussed in this document.

[0014] The selector is defined herein as a collection of

passive, active, digital and analog circuit components that provide the functionality of extracting some predetermined information from the signal on each of the paths. Typically, the desired information to extract is simply a reconstruction of the original signal with attenuation of undesired signals. If the path filters contain A/D converters, the selector will typically be digital. Generally, the selector can be arbitrarily complicated. For example it may be convenient to treat the paths as different phases of a complex radio signal and demodulate the radio signal directly from these different phases rather than recombine them to a single filter output.

[0015] A simple selector can be provided by a series of

switches closed in sequence. The same clocks used for the input signal distribution can also be used for output selection. If the path filters each use a two- phase non-overlapping clock, the activities on each path can be summarized in Table 1. For discussion, we can divide the period of the clocks into 5 equal intervals. When a distribution switch is closed, the table reports "sample" similarly, "out" is displayed for time intervals where each path is connected to the output .

Table 1:

Out switch out

Path 3 Dist. switch sample

clk3 phi2 phi2 phil phil phi2

Out switch out

Path 4 Dist. switch sample

clk4 phil phi2 phi2 phil phil

Out switch out

Path 5 Dist. switch sample clk4 phil phi2 phi2 phi2 phil

Out switch out

[0016] If the N-path filter provides sufficient filtering

outside the desired bandwidth of the N-path filter, it is possible to decimate. When such decimation occurs, the output sampling frequency is lower than the input sampling frequency. This occurs, for example, when there is a continuous time input to the filter, which can be thought of asymptotically as an infinite sampling rate, and a finite output sampling rate. More conventionally, if the distributor has a sampling rate K times faster than the sampling rate at the N-path filter output, then the N-path filter is said to decimate by a factor of K. This decimation has been demonstrated before A/D conversion (see US Patent

Application 12/742,670) and is possible after A/D conversion .

[0017] Another implementation detail for all known N-Path

filters is that the selector and the distributor must be synchronized. To synchronize the distributor and the selector, the two units are usually made responsive to a common timing reference which may or may not be included in either of the distributor or the selector. Commonly, a series of dividers or, more generally, a finite-state-machine (FSM) is responsive to a clock with a frequency higher than the output sample rate of the N-Path filter. This reference clock may be a part of either the selector or the

distributor, or it may be external to the entire N- Path Filter. One-shot state-machines are particularly advantageous in that the state of the machine can be directly used for many of the required clocks. These states can then be used to derive a collection of clock signals that control analog switches or digital multiplexers for the output selector. Similarly, clocks for the selector can be derived from the same FSM. In cases where the selector and the distributor both require the same clock signals, the clock signals can be derived from either one and then sent to the other .

[0018] Because of this large variety in the well-known or obvious ways to accomplish the required

synchronization between the distributor and the selector, the synchronization is not shown in many of the figures to simplify the presentation.

[0019] As an example of how to synchronize the distributor and the selector of an N-Path filter, we can again consider the filter of Figure 1 and Table 1. If a one- shot FSM is derived from a reference clock in the selector and provides 5 outputs Pl(t), P2 (t) , P3 (t) , P4 (t) , and P5 (t) , where PI (t) is high only during time interval 1, where P2 (t) is high only during time interval 2, and similarly for the other phases. Using these pulses, the "out" pulse for Path 1 can be implemented with P5(t), while the "out" pulse for Path 2 can be implemented with PI (t) and so on. Similarly, in the selector, clocks for the filter and resettable integrator can be generated from these same 5 pulses Pl(t) to P5 (t) . The phil pulse for Path 1 can be implemented with the logical OR of PI (t) and P2 (t) and so on .

[0020] Figure 2 shows a typical 3-Path charge domain filter.

The example in Figure 2 is that of a charge domain filter with:

- a time varying current distributor (a block labeled Distributor in Figure 2) responsive to an input Vin for providing path currents on summing nodes, in Figure 2 these summing nodes are labeled Snl to Sn3

- resettable integrators (in Figure 2 these are labelled AccAl-AccA3) each responsive to the path currents, coupled by the co-responding summing node, and providing an output proportional to the integrated charge

- a selector (a block labelled Selector in Figure 2) coupling each of the path-filter outputs to a common output .

[0021] One or more paths can be used. To teach from a

concrete example, three paths are used in the example in Figure 2. The number of outputs from the time varying current distributor must match the number of resettable integrators. Each output of the time varying current distributor provides a signal charge inserter to a corresponding resettable integrator. [0022] A time varying current (TVC) distributor is defined herein as a collection of passive and/or active circuit components which respond to an input to provide one or more time varying output currents.

Further, each of the output currents is proportional to the input, and, additionally, the ratio of proportionality Gm between the input and the time varying output current is a function of time Gm(t) . Further, when there is more than one path, the Gm(t) proportionality ratio on each path is offset by a time interval Ts on each path. This time interval is Ts = 1/fs where fs is the final output sampling frequency of the filter. The proportionality ratio Gm(t) may also be referred to as an input current weight.

[0023] One distinguishing feature of these charge-domain

filters is that they provide a TVC distributor. A TVC distributor has the advantages that the sample is formed by integrating current over a long period of time compared to a conventional sample and hold circuit. They also create a sample by integrating current to obtain a charge on a capacitor rather than sampling a voltage to get a voltage across the two terminals of a capacitor. This is one motive for referring to it as a charge-domain filter. In the older switched capacitor filters, the voltage sampled produced a charge that was dependent on capacitor size and capacitor linearity. In charge-domain filters, the charge sampled is dependent primarily on the Gm(t), the time-varying proportionality ratio between the input current and an output current of the TVC distributor . [0024] Early TVC distributor work noticed that a fixed Gm could be multiplied by a sequence of tap coefficients to form a Gm(t) which could be used to provide a charge domain filter. Later work showed that more elaborate Gm(t) functions could provide more

complicated filters and described methods and apparatus capable of providing such elaborate Gm(t) functions .

[0025] One way to implement a TVC distributor can be

illustrated using a single path. When the time varying input current weighting Gm(t) changes faster than the output sampling rate, a charge domain filter can be built with only one path. That is, a charge domain filter can be described as an N-Path filter, even for the case where N=l. In this example, a single path proportionality ratio Gm(t) is provided by a single fixed Gm which is effectively multiplied by a repeating sequence [1 j -1 -j ] depending on whether the Gm element is connected to inverting or

noninverting nodes of in-phase and quadrature resettable integrators. This example further

illustrates that the paths can be a differential signal using 2 wires or a complex signal using 4 wires .

[0026] The functionality of an N-path distributor can be

provided by either the rotating tap currents technique or the rotating tap coefficients technique outlined in US Patent Application 12/742,670 (this document is incorporated herein by reference) . For example, using the rotating tap-current technique, a first fixed transconductance Gma is connected to the different summing nodes - the transconductance Gma is first connected to summing node Snl, then to summing node Sn2, then to summing nodeSn3. Similarly a second fixed transconductance Gmb is connected to the summing nodes but in a sequence different from the sequence used for transconductance Gma . For transconductance Gmb, this transconductance is first connected to summing node Sn3, then to summing node Snl, then to summing node Sn2. As a result we have the path current weighting Gml (t) of the input signal being a function of time. Similarly the other two path currents are also time varying weightings of the input signal. (See Equation Group 1)

Equation Group 1 :

Gm2(t) = f Gmc 0 < t < Ti

Gma Ti≤t < 2Ti

Gmb 2Ti < t < 3Ti and

This pattern repeats with a period of 3Ti. Switches and clock signal generation to make these connections should be well known to those versed in the art and are outlined in detail in the reference patent application, US Patent Application 12/742,670

(International Filing Date 14 November 2008, PCT application PCT/CA2008 /002004 ) , the entirety of which is incorporated herein by reference.

[0028] The functionality of the output selector is to

transfer to the filter output a signal proportional to the charge accumulated in each resettable integrator.

[0029] When the resettable integrator functionality is

provided by an active resettable integrator, the output selector can be provided by circuitry as simple as a series of switches closed in sequence. The detailed operation of this is described with reference to the N-Path filter in Figure 1 and Table I.

[0030] A resettable integrator is defined herein as a

collection of passive or active circuit components whose functionality has the following two modes:

1. to accept the charge inserted at its input over a predetermined time interval between reset pulses and to accumulate the charge on an integrating capacitor during that time interval, and

2. when a reset pulse is asserted, to place a predetermined charge onto the capacitor.

[0031] Many resettable integrators are known to those versed in the art. Figure 3 illustrates the use of active resettable integrators. Figure 4 illustrates the use of passive resettable integrators. In Figure 3, the output of the active resettable integrator is Resl which is a different circuit node than Snl, while in Figure 4, the output of the passive resettable integrator Resl is actually the same wire as Snl. This passive resettable integrator version, without the operational amplifier, requires a high output

impedance from the signal.

[0032] In each of the resettable integrators shown in Figures

3 and 4, the integrator is a capacitor (Cil) that can have its charge reset to a predetermined value of zero charge or zero volts across the capacitor. To reset to some non-zero value it is necessary to use two switches, one for each terminal of the capacitor, connecting each terminal to an appropriate voltage source. In order to do this, it may also be necessary to have more switches so that the capacitor can be disconnected from the other circuitry used in

integrate mode .

[0033] To teach from the simplest example, the circuit

descriptions for the resettable integrator have shown simple, single ended circuit implementations. However:

- Generally, fully differential or balanced circuit implementations are better for power supply rej ection .

- Many improvements for resettable analog integrators are well known. These often show up in the field of A/D conversion.

- With active resettable integrators, as in Figure 3, many techniques such as chopper stabilization or correlated double sampling are well known to reduce offsets and low frequency operational amplifier noise.

- a continuous time charge inserter may be used. [0034] Figure 5 shows the case where N=3 to teach the principle of operation of one aspect of the invention by a simple example. In this example, a three output TVC distributor is used as the signal charge inserter for 3 resettable integrators. In the example in Figure 5, a distributor block (labelled Distributor) has three distinct transconductance circuits , each transconductance circuit producing a time varying output current based on a time varying proportionality ratio (Gml (t) , Gm2 (t) , Gm3 (t) ) and the input current. Each transconductance circuit' s output is sent to a corresponding resettable integrator block (AccAl, AccA2, AccA3) by way of a summing node (Snl, Sn2, Sn3) . The outputs of the integrator blocks are received by a selector block (labelled Selector in Figure 5) and each output is received by a

corresponding sampling switch (Sampl, Samp2, Samp3) in the selector block. Within each transconductance circuit of the time varying current distributor block are three clock controlled transconductance sub- circuits, the outputs of which are each fed into their corresponding summing node for their corresponding resettable integrator.

[0035] As can be seen, the circuit in Figure 5 provides 3 paths with each path having a TVC distributor transconductance circuit, a corresponding summing node, a corresponding resettable integrator block, and a corresponding sampling switch.

[0036] The timing of this operation is shown in Figure 6.

Figure 6 shows parts of the operation of the filter for three T _s clock cycles which repeat indefinitely while the filter is in operation. The first cycle shown in the figure is for clock cycle k after the filter has been running for (k-1) _s seconds. As with prior art charge domain filters, the system forms an N-Path Filter where the total charge integrated onto each integrating capacitor Cil, Ci2 and Ci3 is charge QTI r QT2 and QT.3- Also, as with prior art charge domain filters, each of the integrated charges is

proportional to a weighted average of the input signal. Thus the next sample (the k ^th sample) will be made after kT _s seconds on pathl. The (k+l) ^th sample will come from path2 and so on to path3 and repeating from pathl. As with the prior art, this weighted average charge is given by: for the k ^th sample stored in integrating capacitor Cil. Here T _a is the time interval of the definite integration also called the aperture time. What is different from prior art is that Gml (t) is the sum of three time varying transconductances (from the three transconductance sub-circuits), Gmla(t), Gmlb(t) and Gmlc(t) illustrated in Figure 5. Each of the three transconductances from the sub-circuits is weighted by a different factor aO, al and a2. These weighted sums form Snl, Sn2 and Sn3. Furthermore, each of these three time varying transconductances is identical, except that each has been offset in time relative to the other by a time interval, T . This is shown in Figure 6, where it can be seen that Gmlb(t) has been offset by a time interval of 1 Ti relative to Gmla(t) and Gmlc(t) has been offset by a time interval of 2 Ti relative to Gmla (t) .

[0038] Substituting for Gml (t) in Equation 2 we obtain: Q _c . -^ =J [aOGi-ιΙαί» - lG lb i. ^' t) - 2 G lc[ t) ^' _ Vin [ t)dt

[0039] The three transconductances form an FIR filter with tap weights given by aO, al and a2 and a sampling rate of 1/Ti. This filter is separate from the filtering provided by each of the time varying transconductances and forms a Virtual' second stage of filtering, prior to the resettable integrators. Of course, depending on the implementation, the tap weights for the transconductances may be the same or equal for each transconductance . The transconductance sub-circuits in Figure 5 may, regardless of the description above, be different from each other. A preferred

implementation would have each sub-circuit be as close to identical as possible to the other sub-circuits.

[0040] Because the total transconductance on each path

(formed by the parallel combination of the three transconductances) does not change, the area increase in this approach is smaller than if a second full stage of filtering were used. Furthermore, large undesired signals are farther attenuated (compared to prior art) before forming a voltage on the sampling capacitor, reducing the final voltage and improving linearity .

[0041] US Patent Application Patent 12/742,670 and other

prior art on charge domain filters describe how to provide the time varying transconductances Gm(t) . Typically the time interval between changes in the value of Gm(t), T is set by one cycle of a high frequency clock or a particular phase of a poly-phase clock. In either case we can think of T as the time difference between rising edges of a single high- frequency clock with a rate of f±=l/Ti. This f± then provides an effective input sampling frequency for the charge domain filter. This time interval of T is also indicated in Figure 8. As with the prior art charge domain filters, the output sample rate, f _s = 1/T _S is sometimes lower to provide decimation to a lower sampling frequency. Figure 8 shows this sample period as well. A person understanding this invention may now conceive of alternative structures and embodiments or

variations of the above all of which are intended to fall within the scope of the invention as defined in the claims that follow.