MULTIPLE INPUT SIG MA-DELTA ARCHITECTURE

Field of the Invention

[0001] The present invention relates to signal processing, and in particular to providing a sigma-delta modulator architecture capable of effectively operating at higher frequencies.

Background of the Invention

[0002] Sigma-delta modulators provide excellent analog-to-digital, digital- to-analog, and digital-to-digital conversion capabilities in an economical and efficient manner. One significant advantage of a sigma-delta modulator is that a high resolution input signal can be converted to a lower resolution signal using only a limited resolution quantizer. Unfortunately, high resolution can only be maintained for low and medium signal bandwidths. As such, sigma- delta modulators are mainly incorporated in devices where the bandwidth of the input signal is small relative to the operating rate of the sigma-delta modulator. Sigma-delta modulators are often found in audio applications and the like. The bandwidth restriction associated with sigma-delta modulators is indirectly due to the feedback path within a typical sigma-delta modulator architecture. Providing the feedback and the necessary processing associated therewith significantly limits the operating rate of the sigma-delta modulator. The restricted operating range corresponds to restricted bandwidths.

[0003] Normally, sigma-delta modulators are not used in wideband wireless applications, such as those requiring digital-to-analog conversion. Wideband wireless transmitters often incorporate lower speed digital-to- analog converters followed by an analog upconversion process and a conventional power amplifier. This traditional approach suffers from the normal limitations associated with analog circuitry, including component variations and temperature stability. The simplicity and cost effectiveness of sigma-delta modulators would be beneficial in wideband wireless applications to overcome these limitations; however, the large signal bandwidths and the high carrier frequencies have made sigma-delta modulators impractical.

[0004] Accordingly, there is a need for a way to incorporate sigma-delta modulators in wideband wireless applications and in other high-frequency applications in a cost-effective and efficient manner, while overcoming the traditional bandwidth limitations associated with sigma-delta modulators.

Summary of the Invention

[0005] The present invention provides a sigma-delta architecture, which is capable of effectively operating at higher than traditional operating rates. In particular, a number of parallel modulation functions are configured to provide sigma-delta modulation (SDM) on a plurality of low sampling rate signals. These multiple low sampling rate signals are representative of a high sampling rate input signal. The low sampling rate signals may be generated from effectively demultiplexing a high sampling rate input signal or may be created in lieu of the high sampling rate input signal. The resultant sigma- delta modulated signals from each of the modulation functions are combined in a multiplexing fashion to create a high sampling rate output signal. Some, if not all, of the modulation functions are interdependent. This interdependency stems from the error signals from each of the modulation functions being provided to a parallel block digital filter, which will provide a processed error signal to feed back into the input of each modulation function. The processed error signal for a given modulation function may be a function of the error signals derived from multiple ones of the modulation functions. In one embodiment, there are N modulation functions, and the operating rate of the modulation functions is f _s / N wherein the sampling rate of the high frequency output signal is f _s .

[0006] Those skilled in the art will appreciate the scope of the present invention and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

Brief Description of the Drawing Figures

[0007] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the invention, and together with the description serve to explain the principles of the invention.

[0008] FIGURE 1 is a block representation of a sigma-delta modulator architecture according to one embodiment of the present invention. [0009] FIGURE 2 is a block representation of a quadrature-based digital upconverter according to one embodiment of the present invention. [0010] FIGURE 3 is a block representation of a sigma-delta modulator architecture including multiple sigma-delta modulator sub-blocks according to one embodiment of the present invention.

[0011] FIGURE 4 is a logical representation of a multiple-input sigma-delta modulator architecture according to one embodiment of the present invention. [0012] FIGURE 5 is a block representation of a sigma-delta modulator architecture including a single multiple input sigma-delta modulator array according to one embodiment of the present invention.

Detailed Description of the Preferred Embodiments [0013] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the invention and illustrate the best mode of practicing the invention. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the invention and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. [0014] The present invention provides a sigma-delta modulation architecture capable of operating efficiently and effectively in high bandwidth applications, including wideband wireless applications where input signal bandwidths are large and centered about high frequency carriers. Based on a required output sampling rate, a sigma-delta modulator architecture is decomposed into a number of parallel modulation functions, each of which provides sigma-delta modulation (SDM) at a much lower sampling rate. In particular, if the sampling rate of the output signal is f _s , there may be N modulation functions, which operate at a sampling rate of f _s /N. As such, sigma-delta modulation can take place at a lower operating rate in each of the parallel modulation function paths, and then the results may be combined to form an output signal operating at the desired operating rate. The N parallel

modulation functions are interrelated and associated with a parallel block digital filter in a manner assuring that the effective sigma-delta transfer function is the same as if a single sigma-delta modulator architecture operating at the higher operating rate were employed. [0015] The overall concept of the present invention is illustrated in Figure 1 , where a basic sigma-delta architecture 10 is illustrated according to one embodiment of the present invention. At the heart of the sigma-delta modulator architecture 10 is an SDM array 12, which includes N modulation functions (MFs) 14, which operate at a frequency f _s /N. In essence, a demultiplexer (DEMUX) function 16 effectively demultiplexes a digitized input signal X(z), which was sampled at a sampling rate of f _s , amongst the N modulation functions 14. Accordingly, each modulation function 14 will receive every Mh sample and provide a sigma-delta modulation operation, which will be described in further detail below. [0016] As with all sigma-delta modulator schemes, the number of bits used to represent the input signal is reduced, often to one or two bits, as those skilled in the art will appreciate. Accordingly, the signals provided to each of the modulation functions 14 are effectively quantized to provide modulated output signals. The quantization noise is filtered by the sigma-delta modulation and the resultant quantization signal is provided to a multiplexer (MUX) function 18, which will effectively assemble an output signal Y(z) from the outputs of the modulation functions 14. The output signal Y(z) will have an effective operating rate of f _s . The signal processing provided by the SDM array 12 will operate to provide a transfer function H(z) substantially the same as if only one sigma-delta modulator was used and was functioning at an operating rate of f _s . Thus, the present invention provides sigma-delta modulation by breaking the input signal into a plurality of lower operating rate parallel paths. Each path provides a modulation function 14, and the resultant outputs are combined to assemble an output signal operating at the desired operating frequency f _s . The demultiplexing function 16 and the multiplexing function 18 can be provided in various ways and in different contexts. The illustrations in Figure 1 are merely logical illustrations used to convey the broad concepts of the present invention.

[0017] Turning now to Figure 2, a block representation of a digital upconversion architecture for a wideband wireless application is illustrated. The upconversion architecture incorporates a multi-input sigma-delta modulator 12. Assume that the SDM array 12 has N paths, which are capable of providing modulation functions 14 (not shown). In this embodiment, assume that the in-phase (I) and quadrature phase (Q) samples of a baseband signal are respectively provided to a baseband processing function 20, which will provide the requisite baseband processing, including complex tuning, rate changing, coding, and the like, and will provide the resultant signals to a polyphase interpolation function 22. The baseband processing function 20 and the polyphase interpolation function 22 are operating at a rate of f _s /N. The polyphase interpolation function 22 will effectively upconvert the respective in-phase and quadrature phase sample streams by a factor of N, and will effectively provide interpolation between adjacent samples to provide additional samples sufficient for the upconversion. Accordingly, for every input sample received from the baseband processing function 20, the polyphase interpolation function 22 will provide N samples at an operating rate of fs/N. Each of the N samples form one of N sub-channels, which are provided to a quadrature modulation function 24. [0018] As such, the quadrature modulation function 24 will receive N pairs of upconverted in-phase and quadrature phase signal pairs. The quadrature modulation function 24 will effectively provide N output signals, which represent the quadrature modulation of the in-phase and quadrature phase input signals. The N outputs of the quadrature modulation function 24 are provided to corresponding N inputs of the SDM architecture 10, which will provide the parallel sigma-delta modulation operations at the operating rate of f _s /N and provide an output signal Y(z) having an operating rate of f _s . This one or multi-bit output signal may be used to drive filter circuitry 26 to effectively provide a digital-to-analog conversion, providing an analog output y(z). Again, the final output operating rate is achieved by combining the lower operating rate outputs of the parallel sigma-delta modulation paths provided by the SDM array 12. As such, only a small portion of the overall design is required to operate at the final operating rate required to generate the output signal y(z).

[0019] With reference to Figure 3, an embodiment providing the functionality of the SDM array 12 and the multiplexing function 18 is illustrated. In this embodiment, the SDM array 12 is made up of M multi-input SDM sub-blocks 28. There are N input signals to the SDM array 12. Each multi-input SDM sub-block 28 will include P inputs and P parallel but interdependent data paths, where P ≤ N. Each input X|(z) for / = 0, 1 , ..., λ/-1 and the corresponding internal data paths operate at a sampling rate of R. Therefore, the final output rate of the output signal Y(z) is N * R. As illustrated, an input interconnect function 30 is shown to facilitate interconnection between each input signal Xι(z) to the SDM array 12, and an output interconnect 32 is used to connect the output of the SDM array 12 to an output commutator 34, which effectively multiplexes the N signals emanating from the SDM array 12 to provide the output signal Y(z). The output interconnect 32 and the output commutator 34 provide the functionality of the multiplexing function 18 of Figure 2.

[0020] The effective input signal provided to the overall architecture of Figure 3 is given by:

where X{z) represents the z transform of the time domain inputs X _/ (n). In one embodiment of the invention, the input signals X|(z) are directly derived from the outputs of either polyphase interpolation filter phases or polyphase quadrature modulator phases. [0021] The input interconnect 30 facilitates the connection of the inputs Xι(z) to the parallel, but independent multi-input SDMs 28 as follows:

Eq. 2 W- J (Z) = X _jM+1 (Z) ,

where

Eq. 3 z e [0,l,...,M -I] ,

and

Eq. 4 J s [0,1, ...,P -I] .

Note that P and M must be chosen such that:

Eq. 5 M x P = N .

[0022] Each of the M elements of the SDM array 12 may be substantially identical, and have a noise transfer function NTF(z) and a signal transfer function STF(z). Within the framework of the architecture illustrated in Figure 3, the noise transfer function NTF(z) and signal transfer function STF(z) of the overall architecture is provided by:

Eq . 6 NTF _T0P (z) = NTF (z ^M )

and

Eq . 7 STF _TOP (z) = STF (z ^M ) ,

respectively. As such, M, NTF(z), and STF(z) may be chosen such that the overall signal and noise transfer functions have desired characteristics, which will vary from one environment to another. As an example, NTF _TO p(z) may have a band-stop filter characteristic, and STFT _O P(Z) may have an allpass filter characteristic centered at a target carrier frequency. [0023] The multi-input SDM sub-block 28 may be derived by applying block digital concepts to a conventional error feedback-based sigma-delta modulator architecture. Further detail on the block digital concepts is provided in, "Multi-Rate Systems and Filter Banks," by P.P. Vaidyanathan, Inglewood Cliffs, New Jersey, 1993, which is incorporated herein by reference. Conventional error feedback architectures are highlighted in "Stable High-Order Delta-Sigma Digital-to-Analog Converters," by P. Kiss; J.

Arias; D. Li; and V. Boccuzzi, IEEE Transactions on Circuits and Systems-I, vol. 51 , issue 1 , January 2004, pp. 200-205, which is also incorporated herein by reference.

[0024] An example of applying block digital concepts to a traditional error feedback sigma-delta modulation architecture is provided in Figure 4. The inputs to a given mujti-input SDM sub-block 28 Wj, ₀ (z) through Wi, _P-1 (z) are fed to corresponding data paths. Each data path will include summation circuitry 36, a quantization function 38, and a difference function 40. Those skilled in the art will recognize that an output feedback structure could be used instead of the error feedback architecture illustrated in Figure 4. An output feedback architecture would not process feed forward and output signals. Instead, the output signal becomes the feedback signal, which is fed to a parallel block digital filter 42. [0025] The multi-input SDM sub-block 28 will also include a parallel block digital filter 42. In operation, the input signals W _ij0 (z) through Wj, _P- i(z) are fed to the corresponding summation functions 36, which will add the input signals Wi _, o(z) through Wj, _P- i(z) to corresponding processed error signals Uj, ₀ (z) through Ui _1P-I (Z), which are provided by the parallel block digital filter 42. The respective outputs of the summation functions 36 are provided to the respective quantization functions 38 and perhaps to the difference functions 40, depending on the configuration of the embodiment. Truncation may be used to provide the effective functionality of the quantization functions 38 and the difference functions 40 without requiring the subtraction operation. The truncated bits are used as the feedback signal. The outputs of the quantization functions 38 provide the outputs V _ii0 (z) through Vj _, p.i(z) of the multi-input SDM sub-block 28. The inputs and outputs of the quantization functions 38 are provided to the corresponding difference functions 40 to create corresponding error signals Ej, ₀ (z) through Ej _)P- i(z), which are fed to the parallel block digital filter 42. Based on the error signals Ej _>0 (z) through Ej _ιP- ^ ₁ (z), the processed error signals Uj, ₀ (z) through U _iiP-1 (z) are generated in accordance with:

Eq. 8 U(Z) = H(Z)I ₁ (Z) ,

where

Eq. 10 E _i (z) = [E. _p _ ₁ (z)...E _ifi (z)] ^T ,

and where T is the transpose operator. The matrix H(z) is pseudocirculant in nature, with its 0 ^th row defined as:

Eq. 11 [H ₀ (Z)H ₁ (Z)... H _p _ _x (z)] ,

where

and where ntf(n) is the impulse response of the noise transfer function NTF(Z). In this way, H _j (z) describes the filter transfer functions that interconnect the parallel data paths within a multi-input SDM sub-block 28. Note that in order to avoid the creation of unrealizable delay-free loops, H ₀ (z) must not have a non-zero z ^' ° term. Therefore, for readability of the prototype, it is required that:

Eq. 13 «t/(0) = l .

[0026] Furthermore, in the preferred embodiment, the impulse response ntf(n) is constrained to have integer values only. This facilitates the realization of the integer coefficients η/z) using only adders (i.e. no multipliers), which allows for the pipelining of feedback loops as described in, "A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5- Mb/s GFSK modulation," by M.η. Perrott; T.L. Tewksbury III; and CG. Sodini, IEEE Journal of Solid-State Circuits, Volume 32, Issue 12, Dec. 1997, pages

2048-2060, which is incorporated herein by reference. This pipelining can dramatically improve the achievable operating rate of the SDM processing because the critical path through each multi-bit adder is reduced to a one-bit full adder. [0027] The outputs V _u (z) of the multi-input SDM sub-blocks 28 are formed into intermediate system outputs V _/ (z) in accordance with:

Eq. 14 Y _l ^) = V _modUMX[l/Mi (z) ,

where

Eq. 15 Z e [0,1,...,AT-I] .

The corresponding time-domain representation is given by:

Eq. 16 y _t (77.) = v _mod(lMxlUMi (n) .

[0028] The final output of the SDM modulator architecture is formed as:

Eq. 17 y(n) = y _→hN) in/Ni) ,

which has a sampling rate of NxR . The corresponding z-domain representation is given by:

N-I Eq. 18 Y(z) = σ ∑Y,(z ^N ) _Z - ¹

/=0

Note that in a digital hardware realization, the commutation function provided by the output commutator 34 can be implemented using an λ/-input multiplexer and associated control logic. [0029] With reference to Figure 5, yet another embodiment of the present invention is illustrated wherein the SDM array 12 is essentially configured as having a single multi-input SDM 28. As such, each of the parallel data paths

is provided in a common architecture. Thus, M = I and P = N for the prior analysis of the respective signals mathematically described in association with Figures 3 and 4.

[0030] With the above embodiments, the limitations currently associated with sigma-delta modulator architectures can be overcome in a cost-effective and efficient manner. With the present invention, benefits of sigma-delta modulators can be achieved where input signal bandwidths are large and centered at high frequency carriers. Sigma-delta modulation processing will no longer be limited to situations where the bandwidth of the input signal is small relative to the operating rate of the sigma-delta modulation architecture. Accordingly, sigma-delta modulation architectures may be implemented in wideband wireless applications where input signal bandwidths are 60 MHz or more and centered at frequency carriers of 2.1 GHz or more. In these instances, the sigma-delta modulation operating rates among the parallel data paths may be an order of magnitude or more less than the final operating rate of the output signal.

[0031] Given the digital-to-digital nature of the sigma-delta modulation of the present invention, the concepts may be implemented in various types of applications. The output signals may be single bit output signals as well as multi-bit output signals. The single bit output embodiments may be used to drive conventional power amplifiers when the SDM architecture 10 is followed by an analog reconstruction filter. The single bit output may be used to directly drive a switching type amplifier. In multi-bit output embodiments, the output signal can be used to drive a multi-phase switching amplifier where the multi-level output is decoded to form switching waveforms for each of the constituent phases, which may be represented in the output signal. [0032] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present invention. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.