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Title:
A MULTIPLE-LOOP SYMMETRICAL INDUCTOR
Document Type and Number:
WIPO Patent Application WO/2012/050703
Kind Code:
A1
Abstract:
A symmetrical inductor includes pairs of half-loops (e.g., 312, 314, 316, 318), first and second terminal electrodes (e.g., 302, 304), and a center-tap electrode (e.g., 310). The half-loop pairs are in respective conductive layers (e.g., 101, 201 ) of an integrated circuit. Each half-loop pair includes a first (e.g., 312, 316) and second half-loop (e.g., 314, 318) in the respective conductive layer. The first and second terminal electrodes are in a first conductive layer, and the center-tap electrode is in a second conductive layer. The first terminal electrode and the center-tap electrode are coupled through a first series combination that includes the first half-loop of each half-loop pair. The second terminal electrode and the center-tap electrode are coupled through a second series combination that includes the second half-loop of each half-loop pair.

Inventors:
KIREEV VASSILI (US)
UPADHYAYA PARAG (US)
MARLETT MARK J (US)
Application Number:
US2011/051247
Publication Date:
April 19, 2012
Filing Date:
September 12, 2011
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
XILINX INC (US)
International Classes:
H01F17/00
Foreign References:
US20030222750A12003-12-04
US20080079527A12008-04-03
DE10261385A12004-07-22
US20040075521A12004-04-22
US20090027152A12009-01-29
Other References:
None
Attorney, Agent or Firm:
GEORGE, Thomas et al. (Xilinx, Inc.2100 Logic Driv, San Jose CA, 95124, US)
Download PDF:
Claims:
CLAIMS

What is claimed is:

1 . A symmetrical inductor, comprising:

5 a plurality of half-loop pairs in a plurality of respective conductive layers of an integrated circuit, each half-loop pair including a first and second half-loop in the respective conductive layer;

a first and second terminal electrode that are both in a first conductive layer of the plurality of respective conductive layers;

10 a center-tap electrode in a second conductive layer of the plurality of respective conductive layers; and

wherein the first terminal electrode and the center-tap electrode are coupled through a first series combination of the first half-loop of each of the plurality of half-loop pairs, and the second terminal electrode and the center-tap i s electrode are coupled through a second series combination of the second half- loop of each of the plurality of half-loop pairs.

2. The symmetrical inductor of claim 1 , wherein the plurality of respective conductive layers are a plurality of different metal layers of the integrated circuit.

20

3. The symmetrical inductor of claim 1 or 2, wherein the center-tap electrode separates the first and second half-loops of one of the plurality of half-loop pairs, and the one of the plurality of half-loop pairs is in the second conductive layer.

25 4. The symmetrical inductor of any one of claims 1 -3, wherein a respective non-conductive region separates each half-loop pair in the respective conductive layer of the half-loop pair.

5. The symmetrical inductor of claim 4, further comprising:

30 a cross-over connection between the first half-loop of a first half-loop pair of the plurality of half-loop pairs and a first half-loop of an additional half-loop pair; and wherein the cross-over connection and the additional half-loop pair are disposed on the respective conductive layer of the first half-loop pair, and the additional half-loop pair is disposed within the first half-loop pair.

5 6. The symmetrical inductor of claim 5, wherein the center-tap electrode and the cross-over connection further separate the first and second half-loops of the plurality of half-loop pairs.

7. The symmetrical inductor of claim 4, wherein, except in the respective

10 non-conductive region for the plurality of half-loop pairs, the plurality of half-loop pairs are coextensive in two lateral dimensions of the integrated circuit.

8. The symmetrical inductor of claim 1 , wherein the plurality of half-loop pairs are substantially coextensive in two lateral dimensions that are

i s perpendicular to each other, and the plurality of half-loop pairs are separated along another dimension perpendicular to both of the two lateral dimensions.

9. The symmetrical inductor of claim 1 , wherein:

each first half-loop is connected in the first series combination in a first 20 order from the first conductive layer to the second conductive layer;

each second half-loop is connected in the second series combination in a second order from the first conductive layer to the second conductive layer; and the first and second orders of the plurality of respective conductive layers are identical.

25

10. The symmetrical inductor of claim 9, wherein:

the first and second terminal electrodes are respectively on a first and second side of the symmetrical inductor;

each of the first and second half-loops of each of the plurality of half-loop 30 pairs is on one side of the first and second sides;

the first series combination with each first half-loop starts with the first side and alternates between the second and first sides; and

the second series combination with each second half-loop starts with the second side and alternates between the first and second sides.

1 1 . The symmetrical inductor of claim 1 , wherein:

the first and second terminal electrodes are respectively on a first and second side of the symmetrical inductor;

each of the first and second half-loops of each of the plurality of half-loop pairs is on one side of the first and second sides;

the first series combination with each first half-loop starts with the first side and alternates between the second and first sides; and

the second series combination with each second half-loop starts with the second side and alternates between the first and second sides.

12. The symmetrical inductor of claim 1 , wherein:

the plurality of half-loop pairs include first and second half-loop pairs; the first terminal electrode is coupled to the center-tap electrode through the first series combination of the first half-loop of the first half-loop pair and the first half-loop of the second half-loop pair, in that order;

the first half-loop of the first half-loop pair is in the first conductive layer on a first side of two sides of the symmetrical inductor, and the first half-loop of the second half-loop pair is in the second conductive layer on a second side of the two sides;

the second terminal electrode is coupled to the center-tap electrode through the second series combination of the second half-loop of the first half- loop pair and the second half-loop of the second half-loop pair, in that order; the second half-loop of the first half-loop pair is in the first conductive layer on the second side, and the second half-loop of the second half-loop pair is in the second conductive layer on the first side; and

the second and first conductive layers are respectively a lower and upper conductive layer disposed in the integrated circuit in that order. 13. The symmetrical inductor of claim 1 , wherein:

the plurality of half-loop pairs includes first, second, and third half-loop pairs;

the first terminal electrode is coupled to the center-tap electrode through the first series combination of the first half-loop of the first half-loop pair, the first half-loop of the second half-loop pair, and the first half-loop of the third half-loop pair, in that order;

the first half-loop of the first half-loop pair is in the first conductive layer on a first side of two sides of the symmetrical inductor, the first half-loop of the second half-loop pair is in the respective conductive layer on a second side of the two sides, and the first half-loop of the third half-loop pair is in the second conductive layer on the first side;

the second terminal electrode is coupled to the center-tap electrode through the second series combination of the second half-loop of the first half- loop pair, the second half-loop of the second half-loop pair, and the second half- loop of the third half-loop pair, in that order; and

the second half-loop of the first half-loop pair is in the first conductive layer on the second side, the second half-loop of the second half-loop pair is in the respective conductive layer on the first side, and the second half-loop of the third half-loop pair is in the second conductive layer on the second side.

14. A method of forming a symmetrical inductor, comprising:

forming a plurality of half-loop pairs in a plurality of respective conductive layers of an integrated circuit, each half-loop pair including a first and second half-loop in the respective conductive layer;

forming a first and second terminal electrode that are both in a first conductive layer of the plurality of respective conductive layers;

forming a center-tap electrode in a second conductive layer of the plurality of respective conductive layers;

coupling the first terminal electrode and the center-tap electrode using a first series combination of the first half-loop of each of the plurality of half-loop pairs; and

coupling the second terminal electrode and the center-tap electrode using a second series combination of the second half-loop of each of the plurality of half-loop pairs.

15. The method of claim 14, wherein the plurality of respective conductive layers are a plurality of different metal layers of the integrated circuit.

Description:
A MULTIPLE-LOOP SYMMETRICAL INDUCTOR

FIELD OF THE INVENTION

One or more embodiments generally relate to inductors, and more particularly to inductors implemented in an integrated circuit.

BACKGROUND

Inductors are useful for implementing electronic filters and resonant circuits. However, inductors in integrated circuits occupy significant area to achieve the needed inductance, and inductors with a high quality factor, Q, are difficult to implement in an integrated circuit.

One or more embodiments may address one or more of the above issues.

SUMMARY

In one embodiment, a symmetrical inductor can include half-loop pairs in respective conductive layers of an integrated circuit. Each half-loop pair can include a first and second half-loop in the respective conductive layer. In this embodiment, the symmetrical inductor can also include first and second terminal electrodes in a first conductive layer, and a center-tap electrode in a second conductive layer. The first terminal electrode and the center-tap electrode can be coupled through a first series combination that includes the first half-loop of each half-loop pair. The second terminal electrode and the center-tap electrode can be coupled through a second series combination that includes the second half-loop of each half-loop pair.

In this embodiment, the respective conductive layers can be different metal layers of the integrated circuit. The center-tap electrode can separate the first and second half-loops of one of the half-loop pairs, and the one of the half- loop pairs can be in the second conductive layer. A respective non-conductive region can separate each half-loop pair in the respective conductive layer of the half-loop pair. The symmetrical inductor can include a cross-over connection between the first half-loop of a first half-loop pair of the half-loop pairs and a first half-loop of an additional half-loop pair. The cross-over connection and the additional half-loop pair can be disposed on the respective conductive layer of the first half-loop pair, and the additional half-loop pair can be disposed within the first half-loop pair. The center-tap electrode and the cross-over connection can further separate the first and second half-loops of the half-loop pairs. Except in the respective non-conductive region for the half-loop pairs, the half-loop pairs are coextensive in two lateral dimensions of the integrated circuit.

5 In this embodiment, the half-loop pairs can be substantially coextensive in two lateral dimensions that are perpendicular to each other, and the half-loop pairs can be separated along another dimension perpendicular to both of the two lateral dimensions. Each first half-loop can be connected in the first series combination in a first order from the first conductive layer to the second

10 conductive layer; each second half-loop can be connected in the second series combination in a second order from the first conductive layer to the second conductive layer; and the first and second orders of the respective conductive layers can be identical. The first and second terminal electrodes can be respectively on a first and second side of the symmetrical inductor; each of the i s first and second half-loops of each of the half-loop pairs can be on one side of the first and second sides; the first series combination with each first half-loop can start with the first side and can alternate between the second and first sides; and the second series combination with each second half-loop can start with the second side and can alternate between the first and second sides.

20 In this embodiment, the first and second terminal electrodes can be

respectively on a first and second side of the symmetrical inductor; each of the first and second half-loops of each of the half-loop pairs can be on one side of the first and second sides; the first series combination with each first half-loop can start with the first side and can alternate between the second and first sides;

25 and the second series combination with each second half-loop can start with the second side and can alternate between the first and second sides. The half-loop pairs can include first and second half-loop pairs; the first terminal electrode can be coupled to the center-tap electrode through the first series combination of the first half-loop of the first half-loop pair and the first half-loop of the second half-

30 loop pair, in that order; the first half-loop of the first half-loop pair can be in the first conductive layer on a first side of two sides of the symmetrical inductor, and the first half-loop of the second half-loop pair can be in the second conductive layer on a second side of the two sides; the second terminal electrode can be coupled to the center-tap electrode through the second series combination of the second half-loop of the first half-loop pair and the second half-loop of the second half-loop pair, in that order; the second half-loop of the first half-loop pair can be in the first conductive layer on the second side, and the second half-loop of the second half-loop pair can be in the second conductive layer on the first side; and the second and first conductive layers can be respectively a lower and upper conductive layer disposed in the integrated circuit in that order.

In this embodiment, the half-loop pairs can include first, second, and third half-loop pairs; the first terminal electrode can be coupled to the center-tap electrode through the first series combination of the first half-loop of the first half- loop pair, the first half-loop of the second half-loop pair, and the first half-loop of the third half-loop pair, in that order. The first half-loop of the first half-loop pair can be in the first conductive layer on a first side of two sides of the symmetrical inductor, the first half-loop of the second half-loop pair can be in the respective conductive layer on a second side of the two sides, and the first half-loop of the third half-loop pair can be in the second conductive layer on the first side. The second terminal electrode can be coupled to the center-tap electrode through the second series combination of the second half-loop of the first half-loop pair, the second half-loop of the second half-loop pair, and the second half-loop of the third half-loop pair, in that order. The second half-loop of the first half-loop pair can be in the first conductive layer on the second side, the second half-loop of the second half-loop pair can be in the respective conductive layer on the first side, and the second half-loop of the third half-loop pair can be in the second conductive layer on the second side.

In this embodiment, the second conductive layer, the respective conductive layer of the second half-loop pair, and the first conductive layer can be respectively a lower, middle, and upper conductive layer disposed in the integrated circuit in that order. The respective conductive layer of the second half-loop pair, the second conductive layer, and the first conductive layer can be respectively a lower, middle, and upper conductive layer disposed in the integrated circuit in that order.

In this embodiment, the half-loop pairs can include first, second, and third half-loop pairs, the first and second half-loop pairs respectively can be an outer and inner half-loop pair, both implemented in the first conductive layer, and the third half-loop pair can be implemented in the second conductive layer; the first terminal electrode can be coupled to the center-tap electrode through the first series combination of the first half-loop of the first half-loop pair, the first half-loop of the second half-loop pair, and the first half-loop of the third half-loop pair, in that order. The first half-loop of the first half-loop pair can be in the first conductive layer on a first side of two sides of the symmetrical inductor, the first half-loop of the second half-loop pair can be in the first conductive layer on a second side of the two sides, and the first half-loop of the third half-loop pair can be in the second conductive layer on the first side. The second terminal electrode can be coupled to the center-tap electrode through the second series combination of the second half-loop of the first half-loop pair, the second half- loop of the second half-loop pair, and the second half-loop of the third half-loop pair, in that order. The second half-loop of the first half-loop pair can be in the first conductive layer on the second side, the second half-loop of the second half-loop pair can be in the first conductive layer on the first side, and the second half-loop of the third half-loop pair can be in the second conductive layer on the second side.

In this embodiment, the first half-loop of the third half-loop pair can be implemented on the first side in both the second conductive layer and a third conductive layer, and the second half-loop of the third half-loop pair can be implemented on the second side in both the second conductive layer and the third conductive layer.

Another embodiment of a symmetrical inductor can include half-loop pairs in conductive layers of an integrated circuit, each of the half-loop pairs can include a first and second half-loop in one of the conductive layers. In addition, the symmetrical inductor can include a first and second terminal electrode that are both in a first conductive layer of the conductive layers, where the first and second terminal electrodes can be respectively disposed on a first and second side of the symmetrical inductor; a center-tap electrode in a second conductive layer of the conductive layers, where the center-tap electrode can be disposed along an axis of symmetry between the first and second sides; and where the first terminal electrode and the center-tap electrode can be coupled through a first series combination of the first half-loop of each of the half-loop pairs, and the second terminal electrode and the center-tap electrode can be coupled through a second series combination of the second half-loop of each of the half-loop pairs. In this embodiment, each first half-loop in the first series combination can alternate between the first and second sides starting from the first side, and each second half-loop in the second series combination can alternate between the first and second sides starting from the second side. A position that the first half- loop of each half-loop pair appears in the first series combination can match a position that the second half-loop of the half-loop pair appears in the second series combination.

An embodiment of a method of forming a symmetrical inductor can include: forming half-loop pairs in respective conductive layers of an integrated circuit, each half-loop pair including a first and second half-loop in the respective conductive layer; forming a first and second terminal electrode that are both in a first conductive layer of respective conductive layers; forming a center-tap electrode in a second conductive layer of respective conductive layers; coupling the first terminal electrode and the center-tap electrode using a first series combination of the first half-loop of each of the half-loop pairs; and coupling the second terminal electrode and the center-tap electrode using a second series combination of the second half-loop of each of the half-loop pairs. In this embodiment, the respective conductive layers are different metal layers of the integrated circuit.

It will be appreciated that various other embodiments are set forth in the

Detailed Description and Claims which follow.

BRIEF DESCRIPTION OF THE DRAWINGS

Various aspects and advantages of the disclosed embodiments will become apparent upon review of the following detailed description and upon reference to the drawings in which:

FIG. 1 is a layout diagram of one conductive layer of a two loop symmetrical inductor in accordance with an embodiment;

FIG. 2 is a layout diagram of another conductive layer of the two loop symmetrical inductor of FIG 1 ;

FIG. 3 is a simplified perspective diagram of the two loop symmetrical inductor of FIGs. 1 and 2; FIG. 4 is a simplified perspective diagram of a symmetrical inductor having three loops on three conductive layers in accordance with an

embodiment;

FIG. 5 is a simplified perspective diagram of another symmetrical inductor having three loops on three conductive layers in accordance with an

embodiment;

FIG. 6 is a simplified perspective diagram of a three-loop symmetrical inductor having two loops on one conductive layer in accordance with an embodiment;

FIGs. 7 and 8 are simplified perspective diagrams of additional three-loop symmetrical inductors having two loops on one conductive layer in accordance with an embodiment; and

FIG. 9 is an exploded layout diagram of an embodiment of the three-loop symmetrical inductor of FIG. 6.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1 is a layout diagram of one conductive layer of a two loop symmetrical inductor in accordance with an embodiment. FIG. 1 shows a pair of half-loops on a first metal layer 101 of the symmetrical inductor and FIG. 2 shows a pair of half-loops on a second metal layer 201 of the symmetrical inductor. In one embodiment, the metal layers 101 and 201 shown in FIGs. 1 and 2 are different metal layers of an integrated circuit.

The symmetrical inductor has two terminal electrodes 102 and 104 in the first metal layer 101 shown in FIG. 1 . The first half-loop pair includes two half- loops 106 and 108, and the half-loops 106 and 108 are separated by an associated non-conductive region of absence 1 10 of the first metal layer 101 .

Another non-conductive region of absence 1 12 of the first metal layer 101 separates the terminal electrodes 102 and 104 and the two half-loops 106 and

108 of the first half-loop pair.

FIG. 2 is a layout diagram of another conductive layer 201 of the two loop symmetrical inductor of FIG 1 . The symmetrical inductor couples the half-loops

106 and 108 shown in FIG. 1 and the half-loops 202 and 204 shown in FIG. 2.

The symmetrical inductor couples the contact area 1 14 of the half-loop 106 of the first half-loop pair and the contact area 206 of the half-loop 202 of the second half-loop pair. Similarly, the symmetrical inductor couples the contact area 1 16 of the half-loop 108 and the contact area 208 of the half-loop 204.

The symmetrical inductor has a center-tap electrode 210 in the second metal layer 201 shown in FIG. 2. In one embodiment, the center-tap electrode is disposed along an axis of symmetry between the left side 120 and the right side 122 of the symmetrical inductor. In FIG. 1 , terminal electrode 102 is disposed on the left side 120 of the symmetrical inductor and terminal electrode 104 is disposed on the right side 122 of the symmetrical inductor.

A non-conductive region of absence 212 of the second metal layer 201 is associated with the second half-loop pair, and the non-conductive region of absence 212 separates the half-loops 202 and 204. The center-tap electrode 210 also separates the half-loops 202 and 204.

In one embodiment, the first half-loop pair shown in FIG. 1 and the second half-loop pair shown in FIG. 2 are substantially coextensive in two lateral dimensions of the integrated circuit. Except in the non-conductive regions of absence 1 10, 1 12, and 212 of the first and second metal layers 101 and 201 , the first and second half-loop pairs are coextensive in the two lateral dimensions through the plane of FIGs. 1 and 2. Thus, projections of the first and second half-loop pairs into the surface of the integrated circuit are identical, excluding the projections of the non-conductive regions of absence 1 10, 1 12, and 212. The two lateral dimensions are perpendicular, and the two half-loop pairs shown in FIGs. 1 and 2 are stacked and separated along a vertical dimension that is perpendicular to both of the two lateral dimensions.

In one embodiment, the pair of half-loops 106 and 108 are matching half- loops because, except in the non-conductive region of absence 1 10, they are mirror images of each other about the axis of symmetry between the left side 120 and the right side 122. Similarly, the pair of half-loops 202 and 204 are matching half-loops because they mirror each other except in the non-conductive region of absence 212.

FIG. 3 is a simplified perspective diagram of the two loop symmetrical inductor of FIGs. 1 and 2. FIG. 3 shows the overall symmetry of the inductor. Contacts making connections between conductive layers are shown with arrows having dotted lines. The symmetrical inductor includes terminal electrodes 302 and 304 on an upper conductive layer of an integrated circuit, and terminal electrode 302 is on one side 306 of the inductor and terminal electrode 304 is on the other side 308 of the inductor. The symmetrical inductor also includes a center-tap electrode 310 on a lower conductive layer centered between the sides 306 and 308.

The first half-loop pair is on the upper conductive layer and includes half- loops 312 and 314. The second half-loop pair is on the lower conductive layer and includes half-loops 316 and 318.

The first terminal electrode 302 and the center-tap electrode 310 are coupled through a first series combination of the half-loops 312 and 316 of the half-loop pairs, and the second terminal electrode 304 and the center-tap electrode 310 are coupled through a second series combination of the half-loops 314 and 318 of the half-loop pairs. Thus, the first series combination includes one half-loop of each half-loop pair, and the second series combination includes the other half-loop of each half-loop pair.

The half-loops 312 and 316 are connected in the first series combination in that order, and the half-loops 314 and 318 are connected in the second series combination in that order. Both the first and second series combinations begin with respective half-loops 312 and 314 on the upper conductive layer, and both the first and second series combinations end with respective half-loops 316 and

318 on the lower conductive layer. The sequence of conductive layers for both series combinations begins with the upper conductive layer and ends with the lower conductive layer. Thus, there are identical sequences of conductive layers for both series combinations.

The first half-loop pair contributes the initial half-loop 312 appearing in the first series combination and the initial half-loop 314 appearing in the second series combination. The second half-loop pair contributes the final half-loop 316 appearing in the first series combination and the final half-loop 318 appearing in the second series combination. Thus, the half-loops 312 and 314 of the first pair appear in matching initial positions in the first and second series

combinations, and the half-loops 316 and 318 of the second pair appear in matching final positions in the first and second series combinations.

Each of the half-loops 312, 314, 316, and 318 is on one of the sides 306 and 308 of the symmetrical inductor. The first series combination starts with half-loop 312 on the side 306 of the first terminal electrode 302, and the first series combination ends with half-loop 316 on side 308. Similarly, the second series combination starts with half-loop 314 on the side 308 of the second terminal electrode 304 and ends with half-loop 318 on side 306. Thus, the half- loops 312 and 316 in the first series combination alternate between the sides 306 and 308, and the half-loops 314 and 318 in the second series combination alternate between sides 308 and 306.

In one embodiment, the conductive layers are a lower metal layer and an upper metal layer created or disposed in the integrated circuit in that order. The first terminal electrode 302 is coupled to the center-tap electrode 310 through the first series combination of the first half-loop 312 of the first half-loop pair and the first half-loop 316 of the second half-loop pair, in that order. The first half-loop 312 of the first half-loop pair is in the upper metal layer on the first side 306 of the symmetrical inductor, and the first half-loop 316 of the second half-loop pair is in the lower metal layer on the second side 308. The second terminal electrode 304 is coupled to the center-tap electrode 310 through the second series combination of the second half-loop 314 of the first half-loop pair and the second half-loop 318 of the second half-loop pair, in that order. The second half- loop 314 of the first half-loop pair is in the upper metal layer on the second side 308, and the second half-loop 318 of the second half-loop pair is in the lower metal layer on the first side 306.

The inductor has symmetry relative to the center-tap electrode 310 because the path from either terminal electrode 302 or 304 to the center-tap electrode 310 is a series combination through respective half-loops, which alternate between sides 306 and 308 in a sequence through matching half-loop pairs on identical conductive layers.

The half-loop pairs are stacked in various embodiments. When the half- loop pairs are stacked close together and substantially coextensive in the two lateral dimensions of the integrated circuit, the magnetic flux generated by each half-loop pair is generally coupled through all the other half-loop pairs. When this occurs, the inductance generated by the inductor is proportional to the square of the number of conductive loops. Because of this, the size of the inductor can be dramatically reduced for a specified inductance, and an integrated circuit can implement many more of these inductors. Various embodiments provide stacked inductors that operate over an extended frequency range. The quality factor, Q, of an inductor is its reactance divided by its resistance. As the frequency of the signal passing through an inductor increases, parasitic elements cause the inductor Q to drop. When the inductor Q drops too low, the application circuit including the inductor operates with reduced utility, or fails to operate at all. For example, an inductor is useful to implement an LC resonant tank circuit of a variable oscillator. An inductor with high Q reduces the jitter of the variable oscillator. As the variable oscillator tunes to progressively higher frequencies, the Q drops until the jitter becomes unacceptable or the resonant tank circuit fails to oscillate. It was discovered that an inductor with symmetry coupled less noise in a differential implementation of an application circuit.

FIG. 4 is a simplified perspective diagram of a symmetrical inductor having three loops on three conductive layers in accordance with an

embodiment. The inductor has symmetry relative to the center-tap electrode 402 because the path from either terminal electrode 404 or 406 to the center-tap electrode 402 is a series combination through respective half-loops on alternating sides 408 and 410 of matching conductive layers.

The first half-loop pair is on the upper conductive layer of the terminal electrodes 404 and 406 and includes half-loop 412 on side 408 and half-loop 414 on side 410; the second half-loop pair is on a middle conductive layer and includes half-loop 416 on side 410 and half-loop 418 on side 408; and the third half-loop pair is on the lower conductive layer of the center-tap electrode 402 and includes half-loop 420 on side 408 and half-loop 422 on side 410.

The first terminal electrode 404 is coupled to the center-tap electrode 402 through the first series combination of the first half-loop 412 of the first pair, the first half-loop 416 of the second pair, and the first half-loop 420 of the third pair, in that order. The first half-loop 412 of the first pair is in the upper conductive layer on a first side 408 of the symmetrical inductor, the first half-loop 416 of the second pair is in the middle conductive layer on a second side 410, and the first half-loop 420 of the third pair is in the lower conductive layer on the first side 408.

The second terminal electrode 406 is coupled to the center-tap electrode 402 through the second series combination of the second half-loop 414 of the first pair, the second half-loop 418 of the second pair, and the second half-loop 422 of the third pair, in that order. The second half-loop 414 of the first pair is in the upper conductive layer on the second side 410, the second half-loop 418 of the second pair is in the middle conductive layer on the first side 408, and the second half-loop 422 of the third pair is in the lower conductive layer on the second side 410.

FIG. 5 is a simplified perspective diagram of another symmetrical inductor having three loops on three conductive layers in accordance with an

embodiment. FIG. 5 rearranges the conductive layers of the symmetrical inductor of FIG. 4 while maintaining symmetry relative to the center-tap electrode 502.

The first half-loop pair is on the upper conductive layer of the terminal electrodes 504 and 506 and includes half-loop 512 on side 508 and half-loop 514 on side 510; the second half-loop pair is on a lower conductive layer and includes half-loop 516 on side 510 and half-loop 518 on side 508; and the third half-loop pair is on a middle conductive layer and includes half-loop 520 on side 508 and half-loop 522 on side 510.

When a current flows through an inductor, a voltage drop occurs across the impedance of each successive half-loop 512, 514, 516, 518, 520, and 522. The complete series combination of half-loops between electrodes 504 and 506 includes half-loops 512, 516, 520, 522, 518, and 514, in that order. The voltage differential between two half-loops increases with increasing separation in this series combination.

The half-loops 512, 514, 516, 518, 520, and 522 have parasitic capacitance between them and the parasitic capacitance is predominately between half-loops on the same side of adjacent conductive layers. Thus, the predominate parasitic capacitances are between half-loop 520 and its physically adjacent half-loops 512 and 518, and half-loop 522 and its physically adjacent half-loops 514 and 516.

The detrimental effect from each parasitic capacitance is roughly a product of the parasitic capacitance and the voltage drop across the parasitic capacitance. Voltage distribution for frequencies below self-resonance is defined by inductance. The more voltage drop between adjacent layers, the more effective capacitance between them. Therefore, an arrangement with less voltage drop between layers will have less parasitic capacitance. Half-loop 520 is separated by one half-loop 516 from half-loop 512, and half-loop 520 is separated by one half-loop 522 from half-loop 518. Similarly, half-loop 522 is separated by one half-loop 518 from half-loop 514, and half-loop 522 is separated by one half-loop 520 from half-loop 516. Thus, the inductor of FIG. 5 has a detrimental effect from parasitic capacitance between the half-loops 512, 514, 516, 518, 520, and 522 that is roughly four parasitic capacitances times the voltage differential across one half-loop.

In contrast, the inductor of FIG. 4 has a detrimental effect from parasitic capacitance between half-loops 412, 414, 416, 418, 420, and 422 that is roughly four parasitic capacitances times the voltage differential across three half-loops. Thus, the arrangement of the conductive layers in the inductor of FIG. 5 is a significant improvement over the arrangement of the conductive layers in the inductor of FIG. 4.

In the illustrated embodiment of FIG. 5, the center-tap electrode 502 is on the lower conductive layer and is connected via a contact between half-loops 520 and 522 in the middle conductive layer. In another embodiment, the center- tap electrode is on the middle conductive layer directly connected between half- loops 520 and 522.

FIG. 6 is a simplified perspective diagram of a three loop symmetrical inductor having two loops on one conductive layer in accordance with an embodiment. The inductor has symmetry relative to the center-tap electrode 602 because the path from either terminal electrode 604 or 606 to the center-tap electrode 602 is a series combination through respective half-loops on alternating sides 608 and 610 of matching conductive layers.

The first half-loop pair is an outer pair on the upper conductive layer of the terminal electrodes 604 and 606. The first half-loop pair includes half-loop 612 on side 608 and half-loop 614 on side 610. The second half-loop pair is an inner pair also on the upper conductive layer inside the outer pair of half-loops 612 and 614. The second half-loop pair includes half-loop 616 on side 610 and half- loop 618 on side 608. The third half-loop pair is on a lower conductive layer and includes half-loop 620 on side 608 and half-loop 622 on side 610.

The first terminal electrode 604 is coupled to the center-tap electrode 602 through the first series combination of the first half-loop 612 of the first pair, the first half-loop 616 of the second pair, and the first half-loop 620 of the third pair, in that order. The first half-loop 612 of the first pair is in the upper conductive layer on the first side 608, the first half-loop 616 of the second pair is in the upper conductive layer on the second side 610, and the first half-loop 620 of the third pair is in the lower conductive layer on the first side 608.

The second terminal electrode 606 is coupled to the center-tap electrode 602 through the second series combination of the second half-loop 614 of the first pair, the second half-loop 618 of the second pair, and the second half-loop 622 of the third pair, in that order. The second half-loop 614 of the first pair is in the upper conductive layer on the second side 610, the second half-loop 618 of the second pair is in the upper conductive layer on the first side 608, and the second half-loop 622 of the third pair is in the lower conductive layer on the second side 610.

A cross-over connection includes a portion 624 in the upper conductive layer of both the outer pair of half-loops 612 and 614 and the inner pair of half- loops 616 and 618. Portion 624 of the cross-over connection couples half-loop 612 of the outer pair and half-loop 616 of the inner pair. The cross-over connection also includes a portion 626 in a middle conductive layer of the integrated circuit. Portion 626 of the cross-over connection couples half-loop 614 of the outer pair and half-loop 618 of the inner pair. The center-tap electrode 602 and the cross-over connection having portions 624 and 626 separate the half-loops 612 and 614 of the outer pair on the upper conductive layer, the half-loops 616 and 618 of the inner pair on the upper conductive layer, and the half-loops 620 and 622 of the pair on the lower conductive layer.

FIGs. 7 and 8 are simplified perspective diagrams of additional three-loop symmetrical inductors having two loops on one conductive layer in accordance with an embodiment. FIGs. 7 and 8 are modifications of the symmetrical inductor of FIG. 6.

The metal layers in a fabrication process of an integrated circuit are generally different. For example, the upper metal layers are generally thicker and have a lower resistance per square than the lower metal layers. Thus, when a half-loop in an upper metal layer is coextensive in two lateral dimensions with a half-loop in a lower metal layer, the half-loop in the lower metal layer generally has a higher resistance than the half-loop in the upper metal layer. To counteract this higher resistance per square of the lower metal layers, two or more of the lower metal layers are strapped together, resulting in a resistance per square of the strapped lower metal layers that approaches or is even lower than the resistance per square of the upper metal layers.

In FIG. 7, the first half-loop 704 of the third half-loop pair is implemented on the first side 706 in both the lower conductive layer of the center-tap electrode 702 and the middle conductive layer, and the second half-loop 710 of the third half-loop pair is implemented on the second side 708 in both the lower conductive layer and the middle conductive layer.

FIG. 8 similarly straps the lower metal layer and the middle metal layer of a symmetrical inductor 800.

FIG. 9 is an exploded layout diagram of an embodiment of the three-loop symmetrical inductor of FIG. 6. The three half-loop pairs are on an upper metal layer 932 and a lower metal layer 934, with a middle metal layer 936 providing connections between the upper metal layer 932 and the lower metal layer 934. The inductor has symmetry relative to the center-tap electrode 902.

The first half-loop pair is an outer pair on the upper metal layer 932 of the terminal electrodes 904 and 906. The first half-loop pair includes half-loop 912 on side 908 and half-loop 914 on side 910. The second half-loop pair is an inner pair also on the upper metal layer 932 inside the outer pair of half-loops 912 and 914. The second half-loop pair includes half-loop 916 on side 910 and half-loop 918 on side 908. The third half-loop pair is on a lower metal layer 934 and includes half-loop 920 on side 908 and half-loop 922 on side 910.

The first terminal electrode 904 is coupled to the center-tap electrode 902 through the first series combination of the first half-loop 912 of the first pair, the cross-over connection 924 on the upper metal layer 932, the first half-loop 916 of the second pair, the connection 928 on the middle metal layer 936, and the first half-loop 920 of the third pair, in that order.

The second terminal electrode 906 is coupled to the center-tap electrode 902 through the second series combination of the second half-loop 914 of the first pair, the cross-over connection 926 on the middle metal layer 936, the second half-loop 918 of the second pair, the connection 930 on the middle metal layer 936, and the second half-loop 922 of the third pair, in that order. In the illustrated embodiment, the combination of the half-loops 912, 914, 916, and 918 on the upper metal layer 932 is substantially coextensive in two lateral dimensions with the half-loops 920 and 922 on the lower metal layer 934. In another embodiment, the half-loops 920 and 922 on the lower metal layer 934 have respective slots (not shown) partially or fully coextensive with the space separating half-loops 912 and 918 on the upper metal layer 932 and a similar space separating half-loops 914 and 916.

In one embodiment, the pair of half-loops 912 and 914 are matching half- loops because they are symmetrical mirror images of each other, except near the connections 924 and 926. Similarly, the pair of half-loops 916 and 918 are matching half-loops and the pair of half-loops 920 and 922 are matching half- loops because they are substantially symmetrical.

One or more embodiments are thought to be applicable to a variety of systems that include inductors. Other aspects and embodiments will be apparent to those skilled in the art from consideration of the specification and practice of the one or more embodiments disclosed herein. The embodiments may be implemented in an application specific integrated circuit (ASIC), or in a programmable logic device. It is intended that the specification and illustrated embodiments be considered as examples only, with a true scope and spirit of the invention being indicated by the following claims.