BACKGROUND OF THE INVENTION Portable electronic applications typically require small, high-efficiency power converters. Oftentimes, such applications also require that the power converters provide multiple outputs. To date, however, multiple-output pqwer converters have typically required multiple inductors or multiple transformer windings, one for each output, wherein each inductor or transformer winding utilizes a relatively large amount of circuit area. A conflict is thus presented in providing multiple-output power converters which are small in size.

To avoid such a conflict, it would be desirable to provide a multiple-output power converter which does not require multiple inductors or multiple transformer windings.

More particularly, it would be desirable to provide a power converter which requires only a single inductor to provide multiple power outputs.

BRIEF SUMMARY OF THE INVENTION The present invention contemplates a multiplexing power converter for use with a single inductor for providing multiple power outputs. The power converter includes first switching means for providing a first low resistance path for current to flow from a power source through an inductor so as to energize the inductor, and at least one second switching means for providing at least one second low resistance path for current to flow from the inductor so as to deenergize the inductor and provide an output current.

Only one low resistance current path is provided at any one time. Thus, in accordance with the present invention, a single inductor is multiplexed between several power outputs to reduce the size and total parts count of a power converter.

In addition, the present invention includes a technique for developing a bootstrap voltage for high-side switching which allows a power converter to start-up with voltages less than or equal to one volt over temperature and circuit tolerances and to continue to operate at even lower voltages once started. Also, the present invention includes a technique for reversing inductor current and developing an output voltage of opposite polarity to the input voltage.

Hysteretic control of the output voltage serves as the basis for the present invention.

From the above descriptive summary it is apparent how the present invention overcomes the shortcomings of the above-mentioned prior art.

Accordingly, the primary object of the present invention is to provide a multiplexing power converter for use with a single inductor for providing multiple power outputs.

The above primary object, as well as other objects, features, and advantages, of the present invention will become readily apparent from the following detailed description which is to be read in conjunction with the

appended drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS In order to facilitate a fuller understanding of the present invention, reference is now made to the appended drawings. These drawings should not be construed as limiting the present invention, but are intended to be exemplary only.

Figure 1 is a simplified schematic representation of a power converter utilizing a multiplexing technique in accordance with the present invention.

Figure 2 is a timing diagram illustrating how positive output voltages are derived utilizing the power converter shown in Figure 1.

Figure 3 is a timing diagram illustrating how negative output voltages are derived utilizing the power converter shown in Figure 1.

Figure 4 is a simplified schematic diagram of a low input voltage, single inductor boost converter which incorporates the concepts of a multiplexing technique in accordance with the present invention.

Figure 5 is a detailed schematic diagram of the low input voltage, single inductor boost converter shown in Figure 4.

Figure 6 is a schematic diagram of an application circuit utilizing the low input voltage single inductor boost converter shown in Figure 4.

Figure 7 is a timing diagram illustrating the function of the low input voltage single inductor boost converter in the application circuit of Figure 6.

Figure 8 is a simplified schematic diagram of a single inductor, multiple output power converter which incorporates the concepts of a multiplexing technique in accordance with the present invention.

Figure 9 is a detailed schematic diagram of the single inductor, multiple output power converter shown in Figure 8.

Figure 10 is a schematic representation of the boost

topology for the VGD, VOUT, and VNICD connections in the single inductor, multiple output power converter shown in Figure 8.

Figure 11 is a schematic representation of the flyback topology for providing a negative voltage at the VNEG connection in the single inductor, multiple output power converter shown in Figure 8.

Figure 12 is a state diagram illustrating the control algorithm that is used by the single inductor, multiple output power converter shown in Figure 8.

Figure 13 is a schematic diagram of an application circuit utilizing the single inductor, multiple output power converter shown in Figure 8.

Figure 14 is a timing diagram illustrating the servicing of the VNICD connection of the single inductor, multiple output power converter in the application circuit of Figure 13.

Figure 15 is a timing diagram illustrating the servicing of the VNEG connection of the single inductor, multiple output power converter in the application circuit of Figure 13.

DETAILED DESCRIPTION OF THE INVENTION Referring to Figure 1, there is shown a simplified model of a power converter 10 utilizing a multiplexing technique in accordance with the present invention. The power converter 10 comprises a switch, So, for charging an inductor, L, from a power source, VIN. The power converter 10 also comprises switches, S1-SN, for controlling the flow of energy to output filter capacitors, C1-CN, and outputs, Vi- VN, respectively.

In its simplest form, the power converter 10 provides output voltage values at outputs V1-VN which are of the same polarity as that of VIN (e. g., a positive voltage value or a negative voltage value). The output voltage value at each output is compared to two reference voltages (i. e., an upper hysteretic control point and a lower hysteretic control point) to determine whether each output voltage value is within an acceptable range or additional energy must be received from the inductor L. The outputs V1-VN are prioritized to determine which output will be serviced during any given boost phase, as described in detail below. In this simplest form of the power converter 10, the outputs VIN are all given a single priority wherein output V1 is given the highest priority, output V2 is given the second highest priority, and so on down to output VN which is given the least highest priority.

Referring to Figure 2, a timing diagram is provided to illustrate how the power converter 10 functions to provide positive output voltages. At t = 0, all of the output filter capacitors Cl-C, are fully discharged (i. e., V1 = 0, V2 = 0, V3 = 0... VN = 0), all of the switches SU-SON are open, and the power source VIN is at full potential. Shortly thereafter, the power converter 10 operates by closing switch So so that power source VIN may begin charging inductor L.

After inductor L has stored a suitable amount of energy during what is termed the"charge phase", switch So opens.

At the same time, one of the other switches closes depending

upon the value of the output voltage at each output. Since all of the output voltages values were initially equal to zero, and output V1 was assigned the highest priority, switch S1 closes, thereby allowing current from inductor L to flow towards output V1 and charge output filter capacitor C1. At some later time (which may be determined by a TON timer, a peak inductor current comparator, or some other circuit as described below), switch Si opens and switch So closes, thereby terminating what is called the"boost phase".

After the boost phase has been terminated, another charge phase begins so that power source VIN may again charge inductor L for another boost phase. At the completion of the second charge phase, switch So opens and the switch associated with the highest priority output having an output voltage value that either has not yet surpassed its upper hysteretic control point or is presently below its lower hysteretic control point will close. That is, if the output voltage value at output V1 has never surpassed its upper hysteretic control point during any previous boost phase, then S1 will close. Also, if the output voltage value at output V1 has previously surpassed its upper hysteretic control point but has subsequently fallen below its lower hysteretic control point, then S1 will close. However, if the output voltage value at output V1 has previously surpassed its upper hysteretic control point and has not subsequently fallen below its lower hysteretic control point, and the output voltage value at output V2 has never surpassed its upper hysteretic control point during any previous boost phase, then S2 will close. Also, if the output voltage value at output V1 has previously surpassed its upper hysteretic control point and has not subsequently fallen below its lower hysteretic control point, and the output voltage value at output V2 has previously surpassed its upper hysteretic control point but has subsequently fallen below its lower hysteretic control point, then S2 will close. The power converter 10 operates in the above-described manner so as to

service all of the outputs V1-VN. Thus, the power converter 10 operates in a priority-based manner wherein an output is serviced based upon whether that output is the highest priority output that has an output voltage value that either has not yet surpassed its upper hysteretic control point or is below its lower hysteretic control point at the start of the next boost phase.

After all of the outputs have been serviced so that their output voltage values have initially surpassed their upper hysteretic control point and are now within an acceptable range (e. g., between an upper hysteretic control point and a lower hysteretic control point), the power converter 10 enters an idle state until the output voltage value of one or more of the outputs drop below its acceptable range. At that point, the power converter 10 will charge inductor L and service the highest priority output having an output voltage value that has fallen below its lower hysteretic control point.

As indicated above, in the example of Figure 2 all of the output voltage values are initially set to zero. In this example, three boost phases are required to bring the output voltage value of the highest priority output (output V1) to its upper hysteretic control point. The next two boost phases are required to bring the output voltage value of the second highest priority output (output V2) to its upper hysteretic control point. During the next boost phase, however, the output voltage value of the third highest priority output (output V3) is brought only to a point that is well below its upper hysteretic control point.

Before the start of the next boost phase, the output voltage value at output V1 drops below its lower hysteretic control point. Since output V1 has a higher priority than output V3, the next boost phase is used to bring the output voltage value at output V1 to its upper hysteretic control point. The next boost phase is then used to bring the output voltage value at output V3 to its upper hysteretic control

point, and the subsequent boost phase is used to bring the output voltage value at output V2 to its upper hysteretic control point due to its falling below its lower hysteretic control point. Finally, with the output voltage values at outputs V1-V3 within their acceptable ranges, the next boost phase is used to bring the output voltage value at output VN to its upper hysteretic control point. It should be noted that the output voltage values of all of the outputs V,-VN are brought to their upper hysteretic control points by charging the corresponding output filter capacitors C1-CN, respectively.

The simplified power converter 10 of Figure 1 can also be used to provide negative output voltages. For example, assume that the output voltage value at output V1 is positive and that it supplies a heavy load. Also assume that the power converter 10 operates in a discontinuous mode and that only outputs V1 and V2 are present.

Referring to Figure 3, a timing diagram is provided to illustrate how the power converter 10 functions to provide negative output voltages. At t = 0, it can be assumed that the power converter 10 has been operating for some time and that the output voltage value at output V1 is slightly below its lower hysteretic control point. The power converter 10 first acts to close switch So so that power source VIN may begin charging inductor L. The charging of inductor L is indicated by the increasing value of current IL. When a suitable amount of energy has been stored in inductor L, switch So opens and switch S1 closes thereby transferring the energy stored in inductor L to output V1 and bringing the output voltage value at output V1 to its upper hysteretic control point and beyond.

When the inductor current IL reaches zero, a different charge phase termed the"back-charge phase"begins. At this point, it is assumed that the output voltage value at output V1 is greater than the voltage value of power source VIN.

Thus, during the back-charge phase, current flows from output

capacitor C1 back to inductor L. Of course, switch S1 must remain closed during the back-charge phase. The back-charge phase has the effect of transferring from output capacitor C1 to inductor L some of the energy that was initially transferred from inductor L to output capacitor C1 in order to bring the output voltage value at output V1 to its upper hysteretic control point and beyond.

When the inductor current IL has reached its most negative value, ILNI switch S1 opens and switch S2 closes so as to begin what is termed the"negative boost phase".

During the negative boost phase, the"negative"energy stored in inductor L is transferred to output V2 via switch S2 so as to make the output voltage at output V2 negative in value.

The value of the maximum negative inductor current ILN is predetermined and controlled by the power converter 10. The negative boost phase is terminated when the value of the inductor current IL reaches zero.

The value of the output voltage at output V, may drop below its lower hysteretic control point while output V2 is being serviced. If this occurs, as indicated in Figure 3, the power converter 10 will initiate a charge phase and then a boost phase so as to bring the output voltage value at output V1 to its upper hysteretic control point and beyond.

After the output voltage value at output V1 surpasses its upper hysteretic control point and the inductor current IL reaches zero, the power converter 10 enters another back- charge phase and then another negative boost phase so as to boost the output voltage at output V2 to a more negative value.

Since the value of the output voltage at output V1 is still above its lower hysteretic control point at the end of the second negative boost phase, which occurs when the value of the inductor current IL reaches zero, the power converter 10 enters still another back-charge phase and then another negative boost phase so as to boost the output voltage at output V2 to an even greater negative value.

At this point it should be noted that the charge phases described above in both Figures 2 and 3 are maintained for a time period during which the value of the inductor current IL increases from a starting point of zero to a maximum positive value, ILp. The value of the maximum positive inductor current ILN is predetermined and controlled by the power converter 10.

It should also be noted that the inductor current waveform shown in Figure 3 is simplified. In an actual circuit, the charge and discharge portions of the waveform will not be perfectly linear due to inductor equivalent series resistance (ESR), inductor on-resistances, and other effects. Also, the slope of the inductor current IL for the charge, back-charge, boost, and negative boost phases will usually differ from one another, and vary somewhat over time, since they are all related to the voltages impressed across inductor L during each phase.

With slightly more circuitry than is shown in Figure 1, it is possible to create a power converter that can start up and operate down to extremely low voltages. Such additional circuitry includes a start-up oscillator which is used to initially drive switch So. Thereafter, one of the outputs, V1_VN/are used for a"bootstrap"voltage for pulse width modulator control circuitry. During start-up, the bootstrap voltage is produced, and then control of switch So is passed from the start-up oscillator to a pulse width modulator. If the bootstrap voltage output is assigned the highest priority, the pulse width modulator will operate until the energy available from the input power source VIN can no longer supply the energy required.

By careful selection of the value of the inductor and other circuit parameters (such as a TON timer limit or a peak inductor current comparator threshold, if applicable) it is possible to operate the power converter 10 well below the input voltage required for initial start-up. The start-up voltage can also be made very low since it is limited only

by the voltage required to turn on switch So (which will usually be a MOS or bipolar transistor) and the minimum operating voltage of the start-up oscillator.

The multiplexing technique described above may be adapted to buck, SEPIC, flyback, quasi-resonant, and resonant topologies. Also, auxiliary supplies can be designed using this technique for developing FET drive signals. It is also possible to use this technique in a power converter that operates in both continuous and discontinuous conduction modes to achieve high low-end and high-end efficiencies.

The above-described multiplexing technique can be easily realized in integrated circuit form. For example, referring to Figure 4, there is shown a block diagram schematic of a low input voltage single inductor boost converter 20 in integrated circuit form along with some associated application circuitry, all of which incorporate the concepts of the above-described multiplexing technique. The converter 20 comprises a modulator control circuit 22, start-up circuitry 24, a MOSFET charging switch 26, and a MOSFET boosting switch 28. The associated application circuitry comprises a DC power source 30, an inductor 32, a flyback diode 34, a power source storage capacitor 36, a gate drive voltage storage capacitor 38, an output voltage storage capacitor 40, and an input power limiting termination resistor 42.

The connections between the internal circuitry of the converter 20 and the external application circuitry include an input voltage connection, VIN, which supplies input voltage to the converter 20 during start-up. After the converter 20 begins to provide an acceptable output voltage, the converter 20 draws power from the VOUT and the VGD connections.

The converter 20 also has a switch connection, SW, which is connected to the input voltage connection VIN through the inductor 32, and is connected to the VGD connection through the flyback diode 34. When transferring energy to the VOUT

connection, the SW connection will first be essentially grounded through the MOSFET charging switch 26, so as to charge the inductor 32. The SW connection will then be connected to the VOUT connection through the MOSFET boosting switch 28, so as to boost the output voltage at the VOUT connection. When transferring energy to the VGD connection, after the inductor 32 has been charged via the MOSFET charging switch 26, the MOSFET boosting switch 28 stays off, thereby allowing energy from the inductor 32 to be diverted to the VGD connection through the flyback diode 34. During discontinuous periods of the inductor current, an additional MOSFET switch (see Figure 5) resistively connects SW to VIN so as to dampen excess circulating energy and thereby eliminate undesired high frequency ringing.

The gate drive connection, VGD, is coarsely regulated around 9 V and is primarily used for supplying drive current to the MOSFET switches 26 and 28 in the converter 20. The voltage value at the VGD connection can be as low as 7.5 V without interfering with the servicing of the VOUT connection. Below 7.5 V, however, the VGD connection will have the highest priority, although practically the voltage should not decay to that level if the gate drive voltage storage capacitor 38 is sized properly.

The output voltage connection, VOUT, has highest priority in the multiplexing technique of the converter 20, as long as the value of the voltage at the VGD connection is above the critical level of 7.5 V. The output voltage is typically 3.3 V, 5 V, or it can be adjustable, as will be described in detail below. The VOUT connection can typically provide over 150 mA to loads with a 1 V power source 30.

A shutdown connection, SD, is provided for putting the converter 20 into a sleep or shutdown mode when the SD connection is open. A built-in current source pulls up on this connection. When this connection is tied to ground, the converter 20 is enabled.

An input power limiting connection, PLIM, is provided

for programming the maximum input power that is allowable for the converter 20. For example, a 1 A current limit at 1 V would have a 333 mA current limit at 3 V keeping the input power constant at 1 W. The peak current at VIN = 1 V is programmed to be 1.5 A (1.5 W) when this connection is grounded. The peak power limit is given by PL (W) 14. 5 RPL + 6. 5 wherein RPL is the value of the input power limiting termination resistor 42 connected from the PLIM connection to ground. The peak current limit is given by <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> T ( = 14. 5<BR> <BR> <BR> VIN (RPL + 6. 5) Constant power gives several advantages over constant current such as lower output ripple.

The converter 20 also has a power ground connection, PGND, and a signal ground connection, SGND. The charging current for the inductor 32 flows through the PGND connection, while the circuitry in the modulator control circuit 22 and the start-up circuitry 24 utilize the SGND connection.

Referring to Figure 5, a more detailed schematic diagram of the converter 20 shown in Figure 4 is provided. In particular, the individual components of the modulator control circuit 22 are shown comprising an on-time controller 200, an off-time controller 202, a voltage reference 204, and an anti-ringing switch 206.

Referring to Figure 6, the converter 20 is shown in block diagram form and specific application circuitry is

shown connected to the converter 20 for providing a 3.3 V output at 500 mW at the VOUT connection.

Referring to Figure 7, a timing diagram is provided for the application circuit shown in Figure 6. At time tl, the voltage level at the VOUT connection drops below its lower voltage threshold, and the inductor 32 is charged with an on- time determined by <BR> <BR> <BR> <BR> <BR> <BR> TON 12 sec<BR> <BR> ON- For a 1.25 V input, and a 22 AH inductor, the resulting peak current is approximately 500 mA.

At time t2, the inductor 32 begins to discharge with a minimum off-time of 1.7 psec. Assuming that the VOUT connection is lightly loaded, the amount of energy delivered in this single energy pulse satisfies the voltage control loop, and the converter 20 does not command any more energy pulses until the voltage level at the VOUT connection again drops below its lower voltage threshold.

At time t3, the voltage level at the VGD connection has dropped below its lower voltage threshold, but the voltage level at the VOUT connection is still above its lower voltage threshold. This results in an energy pulse to the VGD connection at time t4. However, while the VGD connection is being serviced, the voltage level at the VOUT connection drops below its lower voltage threshold. Thus, at time ts, after the VGD connection has been serviced, the VOUT connection is serviced again.

The converter 20 comprises control circuitry which provides high efficiency power conversion for both light and heavy loads by transitioning between discontinuous and continuous conduction modes based upon the load conditions.

For example, at time t6, a transition occurs from the light load to a heavy load. Due to the heavy load, a single energy

pulse is not sufficient to force the voltage level at the VOUT connection above its upper voltage threshold before the minimum off-time has expired. Additional charge cycles are therefore required. Since the current through the inductor 32 does not reach zero in this charge cycle, the peak current at the end of the next charge cycle is greater than 0.5 A, which is the peak current of the discontinuous mode. The result is a continuous mode ratcheting of the current through the inductor 32 until either the voltage level at the VOUT connection reaches its upper voltage threshold, or the converter 20 reaches its programmed peak current limit.

At time t,, the voltage level at the VGD connection has dropped below its lower voltage threshold, but the converter 20 continues to service the VOUT connection because it has highest priority until the voltage level at the VGD connection drops below 7.5 V, which is its critical voltage threshold.

Between t7 and t8 the converter 20 reaches its programmed peak current limit which is determined by RPL and VIN. Once this limit is reached, the converter 20 operates in steady state continuous mode with approximately 200 mA of ripple current.

At time t8, the energy transferred from the inductor 32 to the output voltage storage capacitor 40 raises the voltage level of the VOUT connection above its upper voltage threshold. Thereafter, since the voltage level at the VGD connection has dropped below its lower voltage threshold, the converter 20 can service the VGD connection at time tg.

The converter 20 incorporates an adaptive power limit control which modifies the current limit of the converter 20 as a function of input voltage. In order to program the power limit, the output power requirements must first be determined and then an initial efficiency estimate must be made. The value of the programming resistor, RPLI is determined by

= 14.5n - 6.5#<BR> POUX<BR> POUT wherein n is the initial efficiency estimate. For 500 mW of output power, and an efficiency estimate of 0.75, the value of RPL is given by <BR> <BR> <BR> <BR> <BR> <BR> (14.5)(0.75)<BR> RPL = -6.5 = 15.25#<BR> 0.5<BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> For decreasing values of RPL, the input power limit increases. Therefore, to insure that the converter 20 can supply 500 mW of output power, a power limiting resistor of less than 15 Q must be chosen. For the application circuit shown in Figure 6, wherein the value of RPL is 6.2 Q, the input power limit of the converter 20 is given by <BR> <BR> <BR> <BR> <BR> <BR> 14.5<BR> PL = 0.67W<BR> <BR> <BR> 15# + 6.5# This input power limit supports 0.5 W of output power.

It should be noted that the input power limit equation contains an approximation which results in slightly less actual input power than the equation predicts. This discrepancy results from the fact that the average current delivered to the load will be less than the peak current set by the power limit function due to current ripple. However, if the ripple component of the current is kept low, the power limit equation can be used as an adequate estimate of input power. Furthermore, since an initial efficiency estimate is required, sufficient margin can be built into this estimate

to insure proper converter operation.

In the application circuit shown in Figure 6, the value of the inductor 32 is 22 yH. This inductor value works well in this and most applications, but values between 10 AH and 100 AH are also acceptable. Lower inductor values typically offer lower ESR and smaller physical size. In contrast, higher inductor values typically result in larger overall voltage ripple because, once the output voltage level is satisfied, the converter 20 will operate in the discontinuous mode and overshoot will result due to residual energy in the inductor 32.

It is important to keep the ESR of the inductor 32 below 0.15 Q for 500 mW applications. As an example, a Coilcraft DT3316P-223 surface mount inductor having a current rating of 1.5 A and an ESR of 84 m0 may be used.

Once the value of the inductor 32 is selected, the value of the output voltage storage capacitor 40 may be selected.

The value of the output voltage storage capacitor 40 will determine the ripple of the converter 20. More particularly, the charge storage characteristic and the ESR of the output voltage storage capacitor 40 will determine the ripple of the converter 20. The worst case ripple occurs when the inductor 32 is operating at maximum current and is expressed by <BR> <BR> <BR> <BR> <BR> <BR> Z<BR> <BR> <BR> 2 C (Vo-VI) + ICLCESR wherein AV is the output voltage ripple, ICL is the peak current through the inductor 32, L is the value of the inductor 32, C is the value of the output voltage storage capacitor 40, Vo is the output voltage, VI is the input voltage, and CESR is the ESR of the output voltage storage capacitor 40.

As an example, a Sanyo OS-CON series surface mount

capacitor, having part number 10SN100M, may be used for the output voltage storage capacitor 40. This part has a rated ESR of 90 mQ at 100 pF. If less than full output power is required, a larger inductor should be used which will result in lower peak currents, and an output capacitor with a higher ESR rating can be used.

The criteria used to select the gate drive voltage storage capacitor 38 are not nearly as severe as for the output voltage storage capacitor 40. The converter 20 does not require a large input voltage decoupling capacitor to operate properly. Thus, a 10 yF is sufficient for this and most applications. It should be noted, however, that optimum efficiency occurs when the value of the gate drive voltage storage capacitor 38 is large enough to decouple the source impedance. This usually occurs for capacitor values in excess of 100 yF.

The power source 30 used in the application circuit shown in Figure 6 may be a single or dual alkaline cell so as to provide the VOUT connection with a 3.3 V, 5. 0 V, or an adjustable output voltage at 500 mW. The VGD connection provides an auxiliary 9 V output, primarily for use in supplying drive current to the MOSFET switches 26 and 28 in the converter 20, but which also can be used for applications requiring an auxiliary output such as a 5 V supply by linear regulating. The converter 20 can start up with the VOUT connection under full load at input voltages typically as low as 0.8 V with a guaranteed maximum of 1 V. Once operating, the typical input voltage required may be as low as 0.5 V, thereby maximizing battery utilization.

The converter 20 provides demanding applications such as pagers and personal data assistants, which require high efficiency from several milli-watts to several hundred milli- watts, with efficiencies of greater than 80% over a wide range of operation. The high efficiency at low output current is achieved by optimizing switching and conduction losses with a low 60 yA quiescent current. At higher output

current, the 0.25 Q MOSFET charging switch 26 and the 0. 5Q MOSFET boosting switch 28, along with the continuous mode conduction, provide high power efficiency. Also, the wide input voltage range can accommodate other types of power sources, such as NiCd and NiMH.

Alternative embodiments of the above-described multiplexing technique can also be realized in integrated circuit form. For example, referring to Figure 8, there is shown a block diagram schematic of a single inductor, multiple output power converter 50 in integrated circuit form along with some associated application circuitry, all of which incorporate the concepts of the above-described multiplexing technique. The converter 50 comprises a modulator control circuit 52, start-up circuitry 54, a MOSFET charging switch 56, a MOSFET boosting switch 58, a voltage monitor 60, a low drop-out linear regulator 62, an external memory power output switch 64, and an external battery charge output switch 66. The associated application circuitry comprises a DC power source 70, an inductor 72, a gate drive voltage schottky flyback diode 74, a negative voltage schottky flyback diode 76, a power source storage capacitor 78, a gate drive voltage storage capacitor 80, a negative voltage storage capacitor 82, an output voltage storage capacitor 84, an input power limiting termination resistor 86, a charge current setting connection resistor 88, and an auxiliary power source 90.

Several of the connections between the internal circuitry of the converter 50 and the external application circuitry are labeled similar to several of the connections associated with the converter 20 described above. Those connections, which include the input voltage connection, VIN, the switch connection, SW, the gate drive connection, VGD, the output voltage connection, VOUT, the input power limiting connection, PLIM, the power ground connection, PGND, and the signal ground connection, SGND, perform functions which are similar to the functions described above for the similarly

labeled connections of the converter 20.

Of the other connections, the negative output voltage connection, VNEG, provides a negative output voltage which is generated according to the multiplexing technique of the present invention. As described in detail below, the VNEG connection has the third highest priority in the multiplexing technique of the converter 50, behind the VGD connection and the VOUT connection, respectively. The negative output voltage is typically held at-6 V, which is a convenient voltage value for an LCD display.

A power monitoring connection, PWROK, provides an output that is indicative of when the voltage value at the VOUT connection is not within tolerance (e. g., below its lower threshold). The PWROK connection is typically connected to a low voltage shutdown circuit in a microprocessor.

An external memory power connection, MEM, provides power from either the VOUT connection or a VNICD connection to an external memory. The external memory is supplied by the VOUT connection if the voltage value at the VOUT connection is greater 2.5 V. If the voltage value at the VOUT connection is less than 2.5 V, the external memory is supplied through the VNICD connection.

The VNICD connection provides an alternative power source for the MEM connection. The VNICD connection is connected to the auxiliary power source 90, which is typically a NiCd battery. The voltage provided by the NiCd battery 90 is regulated to 2.5 V by the linear regulator 62, which provides up to 50 yA at the MEM connection for external memory backup power.

A charge current setting connection, ISET, is used to set the charge current for the external NiCd battery 90. The value of the charge current setting connection resistor 88, which is connected between the ISET connection and the VIN connection, determines the amount of charge current that is permitted. The charge current typically ranges from 5 to 50 mA. The average charging current (when the other outputs are

not being serviced) is determined by 0. 242 CHARGECHARGE<BR> <BR> LRSET A charge enable connection, CHGEN, allows the external NiCd battery to be charged. The CHGEN connection is typically connected to the VOUT connection.

Referring to Figure 9, a more detailed schematic diagram of the converter 50 shown in Figure 8 is provided. In particular, the individual components of the modulator control circuit 52 are shown comprising a boost converter controller 100, a voltage reference 102, an external battery charger logic and timer circuit 104, and an anti-ringing switch 106.

The multiplexing technique of the converter 50 arbitrates between the four prioritized outputs (VGD, VOUT, VNEG, and VNICD) so as to insure an orderly start-up and keep the outputs within regulation. This assumes, of course, that the inductor 72 has been sized properly and that the output loads are within their limits. The thresholds that determine which output gets serviced are as follows: If VGD < 7.6 V, then VGD will get priority for service.

If VGD > 7.6 V and VOUT < 3.3 V, then VOUT will get priority for service.

If VGD < 8.7 V and VOUT > 3.3, then VGD will get priority for service.

If VGD > 8.7 V and VOUT > 3.3 V and IVNEGI < 6 V, then VNEG will get priority for service.

If VGD > 8.7 V and VOUT > 3.3 V and VNEGJ > 6 V, then

the timer for the NiCd battery charger will begin.

VNICD will be serviced if the timer expires before another output requires service.

A small amount of hysteresis has been built into the voltage thresholds to prevent erratic operation due to noise.

The three outputs providing positive output voltages (VGD, VOUT, and VNICD) use a boost topology as shown in Figure 10. The main switch, which corresponds to the MOSFET charging switch 56, turns on for a time Tcharge SO as to allow current from the power source 70, represented by VIN, to ramp up in the inductor L, which corresponds to the inductor 72.

The converter 50 then determines which output will be serviced and turns on the appropriate switch for a time Tdischarge Charge and Tdischarge times vary depending upon the output being serviced and the state of the current in the inductor 72. The anti-ringing switch 106 shorts the VIN connection to the MOSFET charging switch 56 during zero current intervals.

When the VGD connection has priority for service, the inductor 72 will be charged with current from the power source 70 for a Tcharge time of Tcharge= 12/VIN 1SeC or until the positive current limit set by RPL is met. When either of the above occur, the main switch 56 will open and the inductor 72 will discharge for a time Tdischarge with a reverse voltage given by VL = VGD + VSCHOTTKY-VIN The VGD boost switch is the gate drive voltage schottky flyback diode 74. This diode 74 will conduct during the discharge phase if the other positive output switches 58 and 66, as well as the main switch 56, are open. The inductor

72 will discharge to zero current unless the Tdischarge time is longer than 6.75 ysec.

When the VOUT connection has priority for service, the inductor 72 will be charged in a similar manner and for similar times as for the VGD connection. When the main switch 56 opens, the MOSFET boosting switch 58 closes so as to deliver energy to the output voltage storage capacitor 84.

The reverse discharge voltage on the inductor 72 is given by VL VOUT + VSWITCH ~ VIN wherein VSWITCH is the voltage drop across the switch 58. The inductor will discharge for 1.75 Hsec, or until the current goes to zero.

Since the VOUT connection is the highest power output, it has the greatest impact on efficiency. For that reason, the MOSFET boosting switch 58 is chosen to have low impedance. Also, the MOSFET boosting switch 58 is initially diode connected during the discharge phase. This prevents shoot-through current that would occur if the MOSFET boosting switch 58 and the main switch 56 were closed simultaneously while insuring proper current steering during the transition.

The VNICD connection has the lowest priority for service and is used to recharge the auxiliary power source 90 (i. e the NiCd battery). The VNICD connection does not use voltage thresholds to request service like the other outputs.

Rather, the timer circuit 104 (see Figure 9) is used to control fixed current bursts that are delivered to the external NiCd battery 90 at a fixed rate. The burst rate time, TCycle/is set by the charge current setting connection resistor 88 tied to the ISET connection. The timer circuit 104 will only be initiated if the other outputs do not require servicing. The timer circuit 104 will be reset if one of the other outputs requests service. Once the timer circuit 104 reaches the burst rate time TCyclel the inductor 72 will be charged with current from the power source 70 for

a Tcharge time of Tcharge = 2. 2/VIN psec After time Tcharge, the output switch 66 will be closed so that the inductor 72 may discharge. Since the power requirements for the external NiCd battery 90 are low, synchronous rectification is not required for the VNICD connection. The output switch 66 consists of a diode connected MOSFET.

During discharge, a reverse discharge voltage given by VL = VNICD + VDIODE - VIN is imposed across the inductor 72. Discharge continues until the inductor current goes to zero. The cycle time and the average charging current for the VNICD connection are given by the following equations <BR> <BR> <BR> <BR> <BR> <BR> (2) (10-11) RSET<BR> <BR> Tcycle =<BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> VNICD - VIn<BR> 0.242<BR> lave-<BR> LRSET With L = 22 AH and RSET = 2.2 MS, the average charging current of the external NiCd battery 90 would be 5 mA.

The external NiCd battery 90 is used to provide external memory backup power when the voltage value at the VOUT connection is insufficient and when the VOUT connection is being serviced. If the external NiCd battery 90 is not required in the application, the charging function should be disabled by tying the CHGEN connection to the PGND connection

and leaving out the charge current setting connection resistor 88.

The VNEG connection gets priority for service only if the voltage thresholds at the VOUT and VGD connections are satisfied. In order to produce a negative voltage at the VNEG connection, a flyback technique utilizing the VOUT connection is used. Figure 11 shows a flyback topology for providing a negative voltage at the VNEG connection.

While the inductor 72 is being charged, the MOSFET boosting switch 58 is closed so as to put a reverse voltage on the inductor 72 given by VL = VIN-VOUT The inductor current then ramps down until a negative current threshold is met (approximately-200 mA). The MOSFET boosting switch 58 is then opened and the voltage across the inductor 72 reverses until it is clamped by the schottky flyback diode 76. The reverse voltage on the inductor 72 is now given by VL VNEG + VDIODE-VIN The inductor current then ramps up to zero and the cycle is complete.

Referring to Figure 12, there is shown a state diagram illustrating the algorithm that is used by the converter 50 to control charge and discharge currents in the inductor 72.

If no requests are made by any of the output connections (i. e. none of the output connections require servicing), the converter 50 waits in the idle state. Once a request occurs, the inductor 72 begins to be charged (charge state). When the inductor current reaches a charge limit (for the highest priority request), the inductor 72 is discharged (discharge state) until a discharge limit is met. Due to the structure of the algorithm, it is possible to change from a lower to

a higher priority request during the charge cycle. The timer for the NiCd charger begins when the idle state is entered.

If the timer reaches Tcycle before another request occurs and the charger is enabled, the VNICD connection will be serviced.

Referring to Figure 13, the converter 50 is shown in block diagram form with specific application circuitry connected thereto for providing an 8.7 V output at the VGD connection, a 3.3 V output at the VOUT connection, a-6 V output at the VNEG connection, and a 20 mA charge current at the VNICD connection. The derivation of the output voltages at the VOUT and VGD connections for the converter 50 is similar to the derivation of the corresponding connections for the converter 20, as shown in Figure 7. However, the derivation of the output voltage and current at the VNEG and the VNICD connections, respectively, differ somewhat.

Referring to Figure 14, there is shown a timing diagram illustrating the servicing of the VNICD connection with reference to the VGD connection for the application circuit of Figure 13. It should be assumed that the VOUT and VNEG connections have little or no load. At time tl, the voltage value at the VGD connection drops below its lower voltage threshold and the inductor 72 charges for a Tcharge time of 12/VIN ysec. At time t2, the energy stored in the inductor 72 is delivered to the VGD connection. At time t3, the NiCd timer 104 expires and no requests are being made from any of the other output connections. Thus, the inductor 72 charges for 2.2/VIN ysec and the stored energy is delivered to the external NiCd battery 90. Very little ripple can be seen on VNICD voltage waveform due to the low ESR of the external NiCd battery 90. The converter 50 then continues to trickle charge the NiCd battery 90 at a rate set by TCycle. At time t4, the VGD connection again requires servicing and the NiCd timer 104 is reset until time t5. At time t6, the NiCd timer 104 expires and the NiCd battery 90 resumes charging.

Referring to Figure 15, there is shown a timing diagram

illustrating the servicing of the VNEG connection with reference to the VOUT connection for the application circuit of Figure 13. It should be assumed that the VGD connection is within regulation. At time tl, the voltage value at the VOUT connection drops below its lower voltage threshold and the inductor 72 charges for a Tcharge time of 12/VIN Hsec. At time t2, the energy stored in the inductor 72 is delivered to the VOUT connection. At time t3, the voltage value at the VNEG connection drops below its lower voltage threshold and the inductor 72 is back-charged until the inductor current reaches approximately-200 mA. At time t4, the energy stored in the inductor 72 is delivered to the VNEG connection until the inductor current reaches zero. At time t5, the VOUT connection is again serviced with a transfer of energy from the inductor 72. At time t6, the VNEG connection requires service, so the inductor current continues to flow to the VOUT connection until the inductor current reaches zero at which time the inductor current reverses direction and the inductor current begins to flow from the VOUT connection.

At time t7, the negative current threshold is met and the energy stored in the inductor 72 is delivered to the VNEG connection.

It can be clearly seen from Figure 15 that the slope of the VOUT connection voltage waveform changes between times t3 and t4, as well as between time t5 and t6. This is due to the fact that energy is being taken from the output voltage storage capacitor 84 to back-charge the inductor 72 for the VNEG connection. At time t8, the load on the VOUT connection is increased and the inductor 72 is forced into continuous conduction mode. At time tg, the VNEG connection requests service but the VOUT connection has priority. At time tio< the VOUT connection is satisfied and the load on the VOUT connection has been reduced. The inductor 72 is then back- charged so as to deliver energy to the VNEG connection. At time tll, the VNEG connection receives a second burst of energy in order to bring the voltage output at the VNEG

connection to a value above its lower voltage threshold.

The selection of the storage capacitors 80,82, and 84 is related to the amount of ripple voltage on each output.

The ripple voltage on each output is caused by inductor current flowing into each storage capacitor 80,82, and 84 and its associated ESR. Since decisions about output servicing depend upon the output voltage levels, it is important that the ripple voltages are within expected values. The ripple voltage for each storage capacitor 80, 82, and 84 can be determined by the following equation ILave Tdischarge Vripple = + #ILESR<BR> C The worst case ripple on all of the outputs occurs when the inductor current decays to zero. Thus, IPeak ILave = #IL = Ipeak<BR> 2<BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> The ripple voltage can now be rewritten as Tdischarge Vri@@@@ = I@@@@ [ + ESR]<BR> @@@<BR> rlppl e peak 2 C Because of the low current requirements of the VGD and the VNEG connections, ceramic capacitors (with almost no ESR) can be used for these outputs. For VIN = 1 V, L = 22 yH, and RPL = 6.2 Q, the resulting ripple voltages for some recommended capacitor values are given below in Table 1.

Output Voltage +8. 7V +3. 3V-6V Ripple Example worst case Imax to Imax to Discontinu- mode zero zero ous to zero Ipeak 0.74A 0.74A 0.200A Tdischarge 2.11 µsec 7.07 µsec 0.628 µsec Recommended 2xl µF 100 µF 1 µ Capacitor X7R OS-CON X7R ceramic 10SN100M ceramic Recommended 0 0.09 0 Capacitor ESR Resulting 390mV 93mV 63mV Vripple Table 1.

The selection of an appropriately sized inductor 72 is critical to the successful operation of the converter 50.

The value of 22 AH will maximize both continuous and discontinuous mode efficiency for a 150 mA load on the VOUT connection. If the current load on the VOUT connection is less than 150 mA, the size of the inductor 72 should be increased linearly to maximize efficiency.

For this particular converter 50, the amount of inductance required also depends on the desired ripple current while operating in continuous mode at the low end of the input voltage range. With the value of the input power limiting termination resistor 86 being 6.2 Q and VIN = 1 V, the peak current limit is 0.74 A. A 25% ripple current corresponds to 0.185 A. The maximum ripple component and the maximum off-time lead to a required minimum inductance given by (VOUT - VIN) (1.75µsec) (3.3-1) (1.75µsec)<BR> <BR> L = = = 21.8µH<BR> #I (0.185)

As an example, the inductor 72 may be a Coilcraft DT3316fP- 223 surface mount inductor having a current rating of 1.5 A and a DC resistance of 84 mQ.

The present invention is not to be limited in scope by the specific embodiments described herein. Indeed, various modifications of the present invention, in addition to those described herein, will be apparent to those of skill in the art from the foregoing description and accompanying drawings.

Thus, such modifications are intended to fall within the scope of the appended claims.