Title:
MULTIPLIER, DIGITAL FILTER, SIGNAL PROCESSING DEVICE, SYNTHESIS DEVICE, SYNTHESIS PROGRAM, AND SYNTHESIS PROGRAM RECORDING MEDIUM
Document Type and Number:
WIPO Patent Application WO/2007/094223
Kind Code:
A1
Abstract:
The conventional two's complement multiplier formed by a boos encoder,
a partial product generation circuit, and an adder has a problem that the circuit
scale becomes large because bit extension is performed when coping with an unsigned
multiplication. It is possible to provide a multiplier including: a first boos
encoder (1) for encoding least significant bits of a multiplier according to
a first encoding rule using a boos algorithm; and a second boos encoder (5) for
encoding most significant bits of the multiplier according to a second encoding
rule different from the first encoding rule, so that the most significant bits
of the multiplier are encoded by using a boos algorithm different from the one
for the least significant bits.
Inventors:
NAGANO, Kouichi (())
Application Number:
JP2007/052179
Publication Date:
August 23, 2007
Filing Date:
February 08, 2007
Export Citation:
Assignee:
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (1006, Oaza Kadoma Kadoma-sh, Osaka 01, 5718501, JP)
松下電器産業株式会社 (〒01 大阪府門真市大字門真１００６番地 Osaka, 5718501, JP)
松下電器産業株式会社 (〒01 大阪府門真市大字門真１００６番地 Osaka, 5718501, JP)
International Classes:
G06F7/533; G06F7/48
Attorney, Agent or Firm:
HAYASE, Kenichi (HAYASE & CO. Patent Attorneys, 4F The Sumitomo Building No.2, 4-7-28, Kitahama, Chuo-ku, Osaka-sh, Osaka 41, 5410041, JP)
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