MULTIPROCESSOR

WIPO Patent Application WO/1995/009399

A1

Data are transferred between arithmetic units 11 to 1N and local memories 21 to 2N for through data buses 61 to 6N parallel processing. The data bus 61 connected to one arithmetic unit 11 can be connected to other data buses 62 to 6N through a mutual connection network (5), and thus by operating only one arithmetic unit 11 data can be transferred through the data buses 61 to 6N and the mutual connection network (5) to and from all the local memories 21 to 2N. In this way, a plurality of arithmetic units are allowed to correspond to a plurality of local memories to execute parallel processing, and any one of the arithmetic units can easily make access to any of the local memories.

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WO/2003/034204	MICROPROCESSOR HAVING AN EXTENDED ADDRESSABLE MEMORY SPACE

OKUMURA YUKIHIKO (JP)
MIKI TOSHIO (JP)
OHYA TOMOYUKI (JP)
MIKI YOSHINORI (JP)

PCT/JP1994/001479

April 06, 1995

September 07, 1994

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NIPPON TELEGRAPH & TELEPHONE (JP)
OKUMURA YUKIHIKO (JP)
MIKI TOSHIO (JP)
OHYA TOMOYUKI (JP)
MIKI YOSHINORI (JP)

G06F9/32; G06F9/38; G06F15/173; G06F15/80; (IPC1-7): G06F15/16

JPS6332649A	1988-02-12
JPH03125252A	1991-05-28
JPH04181362A	1992-06-29
JPS60134957A	1985-07-18
JPH05189585A	1993-07-30

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