Title:
MULTIPROTOCOL COMPUTER BUS INTERFACE ADAPTER AND METHOD
Document Type and Number:
WIPO Patent Application WO2001093052
Kind Code:
A3
Abstract:
A predictive time based generator having predictive synchronizer and replica delay element coupled with the synchronizer feedback delay loop. The predictive time base generator receives a clock signal delayed by a predetermined clock delay and produces a predictive time signal advanced in time by an amount represented by the replica delay element. The replica delay element can replicate one or both of a predetermined clock delay and a predetermined data delay, substantially nullifying the respective delays in critical signal paths of a device. The replica delay element can include replicas of structure(s) found in an incoming clock path and an outgoing data path, such elements including, for example, voltage level shifters, buffers or data latches, multiplexers, wire element models, and the like. A predictive computer bus interface adapter which incorporates the aforementioned predictive time base generator is also provided. Such a predictive interface adapter can be adapted to be observant of stringent bus protocol timing budgets imposed under the PCI and PCI-X local bus protocol, and to be robust relative to variations in design and fabrication processes, and environmental operating conditions.
Inventors:
CHIAO JENNIFER Y (US)
ALVSTAD GARY A (US)
WAKAYAMA MYLES H (US)
ALVSTAD GARY A (US)
WAKAYAMA MYLES H (US)
Application Number:
PCT/US2001/040810
Publication Date:
June 20, 2002
Filing Date:
May 25, 2001
Export Citation:
Assignee:
BROADCOM CORP (US)
CHIAO JENNIFER Y (US)
ALVSTAD GARY A (US)
WAKAYAMA MYLES H (US)
CHIAO JENNIFER Y (US)
ALVSTAD GARY A (US)
WAKAYAMA MYLES H (US)
International Classes:
G06F1/04; G06F1/10; G06F1/12; G06F13/00; G06F13/38; (IPC1-7): G06F13/38; G06F1/12
Foreign References:
| US5652530A | 1997-07-29 | |||
| US6047383A | 2000-04-04 | |||
| EP0353027A2 | 1990-01-31 | |||
| JP2000099192A | 2000-04-07 |
Other References:
YONGSAM MOON JONGSANG CHOI KYEONGHO LEE DEOG-KYOON JEONG MIN-KYU KIM: "AN ALL-ANALOG MULTIPHASE DELAY-LOCKED LOOP USING A REPLICA DELAY LINE FOR WIDE-RANGE OPERATION AND LOW-JITTER PERFORMANCE", IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 35, no. 3, March 2000 (2000-03-01), pages 377 - 384, XP002185087
YONGSAM MOON JONGSANG CHOI KYEONGHO LEE DEOG-KYOON JEONG MIN-KYU KIM: "A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells", CUSTOM INTEGRATED CIRCUITS, 1999. PROCEEDINGS OF THE IEEE 1999 SAN DIEGO, CA, USA 16-19 MAY 1999, PISCATAWAY, NJ, USA,IEEE, US, 16 May 1999 (1999-05-16), pages 299 - 302, XP010340765, ISBN: 0-7803-5443-5
YONGSAM MOON JONGSANG CHOI KYEONGHO LEE DEOG-KYOON JEONG MIN-KYU KIM: "A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells", CUSTOM INTEGRATED CIRCUITS, 1999. PROCEEDINGS OF THE IEEE 1999 SAN DIEGO, CA, USA 16-19 MAY 1999, PISCATAWAY, NJ, USA,IEEE, US, 16 May 1999 (1999-05-16), pages 299 - 302, XP010340765, ISBN: 0-7803-5443-5
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