Prior Art Figure 1 is a diagram of a generic digital transceiver where a radio frequency (RF) signal is radiated/intercepted by an antenna and subsequently filtered, amplified, and upconverted/downconverted to an intermediate frequency (IF). After reception/transmission at interface 10, the signal is converted to analogue/digital signals using the D/A and A/D blocks 11,12. The digital front end block 13 performs Digital Up/Downconversion and sample rate conversion of the digital signals. The Baseband DSP block 14 performs all the data processing necessary to prepare the signal for transmission/reception.

In the remaining discussion we will concentrate on the receiver side without loss of generality.

Figure 2 is a diagram of the RF/IF block. The RF signal is filtered by an RF filter 20 and amplified using a Low Noise Amplifier (LNA). The mixer 22 downconverts the RF signal to IF. The IF filter 23 removes all the undesired signals that are produced by the mixing process.

Figure 3 is a diagram of a conventional digital front-end receiver that performs frequency Downconversion and sampling rate reduction. A radio frequency (RF) signal or an Intermediate Frequency (IF) signal is sampled by an analogue-to-digital (A/D) converter 12. The sampled signal is mixed down to baseband by digital mixers 30,31 using the outputs of a Numerically Controlled Oscillator (NCO) 32 which generates sine and cosine signals that mix the sampled signals to In-phase (I) and Quadrature-phase (Q) baseband signals. The baseband I & Q signals are then filtered by low pass filters H (z) to attenuate the out of band signals. The filtered signal is then downsampled by a factor of M in decimators 33,34 to reduce the sampling rate by retaining only one out of M samples.

The filtering and downsampling operations can be implemented using a computationally efficient polyphase structure as shown in Figure 4.

The input signal is serial to parallel converted into M subsignals in converter 37, which immediately reduces the sampling rate to 1/M of the input sampling rate. The filter N tap filter H (z) is divided into N/M tap subfilters Ho (z), Hl (z), H2 (z), HM-i (z) operating at 1/M the original sampling rate. The polyphase structure requires M times less numerical operations than the original structure. The outputs of the subfilters are recombined in adder 38.

Figure 5 is a diagram of a polyphase filter where H (z) is an N tap FIR filter and M=2.

On the left we see a standard diagram for a FIR filter 40 followed by a decimator 41.

The equivalent polyphase structure comprises serial to parallel converter 42 having two outputs for odd and even samples respectively. Even samples are processed by even filter elements ho, h2, h4 etc. and odd samples are processed by odd elements hl, h3 etc. and the result is added in adder 43 to produce a signal having half the sample rate of this input signal.

Summary of Invention The present invention addresses the computational complexity of the Digital front-end in Figure 3, and proposes a computationally efficient architecture for multi carrier signals.

The problems addressed are: The digital signal is converted to baseband using the NCO immediately after the A/D, which means operating at the A/D sampling rate.

'The digital signal is converted to a complex signal (Real and Imaginary paths), thus the following operations are duplicated for both paths.

'The NCO performs single carrier tuning only to baseband, thus the filter H (z), is a low pass filter that attenuates the other carriers, and the downsampler reduces the sampling rate as required.

To receive all the digitised carriers in a wideband signals, parallel sections of digital the digital front-end have to be implemented thus increasing the complexity considerably for multicarrier receivers.

The present invention provides a method of processing a digital signal obtained by sampling a wideband of carrier frequencies at a rate Fs, in order to obtain information from a desired channel of carrier frequencies within said wideband, said method comprising: (a) coverting the sampled input signal into M subsignals, where M is an integer greater than 1, each subsignal having a sample rate equal to Fs/M ; (b) applying the subsignals to an M-channel bank of band pass filters each having a different pass band within said wideband; (c) selecting the output from the one of said filters containing said channel of carrier frequencies; and (d) repeating steps a), b) and c) using as the input the output selected at step c) until the next repetition would exclude frequencies in said desired channel.

Thus, the invention provides a novel technique for the digital front end that reduces the computational complexity considerably by performing the multiband Decimation and Downconversion simultaneously using Multirate filter banks.

At each iteration of the steps (a), (b), and (c), the sample frequency and the bandwidth of the signals being processed are reduced by a factor of M and thus decimation and coarse downconversion are performed at the same time. The conversion of the signal to complex I and Q signals can be performed after the step (d), at which point the sampling rate has already been reduced.

In the preferred process according to the invention, the value of M is the same for each repetition of steps (a), (b) and (c), and preferably 2 whereby each of the two filters in the bank may pass half of the band of frequencies applied to the filter bank.

The filters may be Quadrature mirror filters.

The invention also provides apparatus for processing digital signals according to claim 7, as well as a receiver incorporating this apparatus. Preferred features of this apparatus are listed in claims 8 to 11.

The method described above can be applied to the processing of signals for transmission. Thus another aspect of the invention provides a method of processing a digital signal for transmission comprising the steps of : (a) applying the signal to an M channel filter bank; (b) parallel to serial converting the signals output from the M filters in the filter bank to produce an interpolated signal whose sample rate is M times the sample rate of the input signal and from which images produced by the interpolation process have been rejected; and (c) repeating steps (a) and (b) until a desired sample rate and/or signal bandwidth is achieved.

The invention also provides apparatus for processing digital signals for transmission as claimed in claim 20 as well as a radio transmitter incorporating this apparatus.

Preferred features of this apparatus are listed in claims 21 to 25.

An embodiment of the invention will now be described by way of example only and with reference to the accompanying drawings in which: Figure 1 is a block diagram of a generic digital transceiver of the type currently in use; Figure 2 is a block diagram showing the typical components of an r. f. block used in the transceiver of Figure 1; Figure 3 illustrates a conventional digital front-end receiver; Figure 4 illustrates an example of a polyphase structure for carrying out filtering and downsampling operations; Figure 5 illustrates a specific polyphase structure of the general type shown in Figure 4 with a decimation factor of 2; Figure 6 (a) and (b) show the analogue frequency spectra of uniform and multi standards wideband signals; Figure 7 shows the digital frequency spectrum of the signal shown in Figure 6 (b) after digitisation; Figure 8 is a block diagram of a polyphase structure for use in carrying out the method of the invention; Figure 9 illustrates the characteristics of quadrature mirror filters (QMF); Figure 10 illustrates a polyphase half band QMF filter bank; Figure 11 (a), (b), and (c) show a typical input spectrum and the output spectra of the respective filters; Figure 12 is a schematic diagram of an iterated two channel filter bank; Figure 13 is a block diagram of multirate receiver architecture; and Figure 14 is a diagram of a conventional digital front-end transmitter that performs upsampling and frequency upconversion; Figure 15 shows a polyphase implementation of interpolation; Figure 16 is a diagram of a two channel synthesis filter bank; Figure 17 shows a polyphase implementation of the circuit of figure 16; Figure 18 shows a polyphase filter bank as in figure 17 in which the filters are constrained to be half band filters; Figure 19 is a further simplification of figure 18; Figure 20 is a diagram of a complete transmitter section incorporating the filter bank of figure 20; and Figure 21 shows graphs of signals input to and output from the circuit of figure 18.

Referring back to figure 3 the A/D 12 samples a multicarrier IF signal that may be comprised of a number of equal bandwidth signals uniformly spaced centred around the IF frequency, or a number of unequal bandwidth signals for a multi standard radio representing differing symbol rates as shown in figure 6.

The signals in figure 5 are produced by a wideband RF section comprising one or more serial or parallel sections as in figure 2 that are capable of downconverting the required bands to the specified IF frequency To simplify the architecture we need to ensure that the digitised signals are centred around quarter of the sampling rate, a fixed IF frequency is imposed equal to odd multiples of quarter of the sampling frequency.

After digitisation the entire band is centred between 0 and Fs/2 and periodically repeated as in figure 7.

In the prior art the multicarrier signal is converted to a baseband complex signal operating at the same high sampling frequency as the A/D before decimation (Fig 3).

In the new design to be described below, the signal passes through a real coefficient Multirate filter bank after digitisation to decimate the required bandpass signals simultaneously and also perform coarse Downconversion without going to DC thus remaining a real signal which reduces the complexity of having to filter the signal on the real and complex paths.

The filter bank is implemented using a polyphase structure. Figure 8 shows a polyphase two channel filter bank structure that will be the building block of our design, where hO and gO are low pass and high pass filters respectively satisfying the Quadrature Mirror Filter (QMF) relationship : gO (H) = (-1)"M Go (#) = Ho(-#) the filters form mirror symmetry around quarter of the sampling rate as shown in figure 9.

Input signals x (n) are applied to serial to parallel converter 60 to provide two signal paths bearing alternate samples. All samples are applied to both filters ho and go and the filter out puts are added at adders 61,62 to provide output signals xo (n) from filter ho and x (n) from filter go.

The filter bank is determined once the required prototype filter is designed. The structure in figure 8 can be further simplified by constraining the prototype filter hO to be a half band filter.

A half band FIR low pass filter H(z) = # h(n)z-n, where N is odd has an impulse response that satisfies: h(2n)={# #}, where c is a constant zu otherwise in polyphase form the filter becomes: H (z) = c + z-lHodd (Z2) following these principles figure 8 reduces to figure 10 which is completely determined by the prototype low pass filter hO. Like parts in figures 8 and 10 have like reference numerals.

Filter response shape required to design the polyphase prototype filter is dictated by the guard frequency band (separating adjacent channels) to channel centre frequency spacing, filter passband gain uniformity, channel attenuation requirements, and the number of channels. The basic filter design can be stored in memory and simply re configured by changing the coefficients for a particular application.

The signal x (n) enters a parallel to serial converter that immediately reduces the sampling rate by a factor of two where its filtered to produce the decimated signals xo (n) and xl (n).

Figure 11 shows an example multicarrier Multirate signal that has been processed by the structure of figure 10.

The signal is downsampled to a new sampling frequency Fsl, at the same time the signals above Fs/4 are folded back (i. e. downconverted). Thus the two differing signals representing two data rates (standards) are now separated into parallel signals with lower overall sampling rates.

The structure of figure 11 can be iterated as shown in figure 12 to further separate the required channel (s) to be further processed.

After performing the required decimation using the filter bank, the real-to-complex conversion to produce baseband I & Q signals centred at DC can be carried out for the individual channels at the lowest possible sampling rate. Further fine tuning of the sample rates for the I&Q signals to match the symbol rates for the particular standard can be performed by the DSP.

Figure 13 shows the new Multirate architecture in receiver mode. Thus, the digital front end, already shown in figure 1, includes a multirate filter bank of the type shown in figure 10 whose outputs are supplied to channel selection means 70. Channel selection means 70 determines which channel or frequency band is to be selected and how many iterations of the filtering process are needed. The final output converted to complex signals I and Q for subsequent processing.

Figure 14 is a diagram of a conventional digital front-end transmitter that performs upsampling and frequency upconversion. The baseband I & Q signals are first upsampled by a factor of M by upsamplers 133,134 by inserting M-1 zeros between each sample. In the frequency domain this creates M-1 images of the baseband spectrum. The filter H (z) is an interpolation filter which is also called an image rejection filter. The NCO mixes up (upconverts) the interpolated signals to the Digital-to-Analogue (D/A) converter IF frequency.

As in the receiver section all the computationally intensive operations are carried out at the higher sampling rates on both the I & Q branch. The aim is to replace this by a computationally efficient Multirate filter bank to simultaneously perform the upsampling and frequency upconversion.

Figure 15 shows the polyphase implementation of the interpolation operation. The filter H (z) is decomposed into M parallel filters, here the filtering is carried out at the lower sampling rate and then the parallel signals are combined using the parallel to serial converter 137 to form the upsampled signal. The output sampling rate is M times the input sampling rate.

For the remaining part we concentrate on the case where M=2, and the filters are FIR filters with N number of coefficients (taps).

Figure 16 shows a 2 channel synthesis filter bank, where two different signals xl and x2 are combined to form the signal x with twice the sampling rate. The filters hl, and gj are low pass and high pass filters respectively related as in figure 9. They are equivalent to the filters ho, and go.

The polyphase implementation of figure 16 is shown in figure 17.

The two signals xl (n) and x2 (n) are two separate baseband signals to be transmitted in separate frequency bands so as not to interfere with each other, enabling them to be recovered by a receiver. Thus, the signals are applied to respective filters hn and gn whose outputs are applied to parallel to serial converters 140,141 to produce a signal xn with a higher sampling rate.

By constraining the filters to be half band filters as in the receiver section, figure 17 reduces to Figure 18 As we can see the lower branch filters are simply inverted versions of the upper branch filters. As shown in figure 18 each sample goes through filters c and h thus creating two samples from one to produce the upsampled signal Figure 18 can be reduced to figure 19 as a recursive 2 channel filter bank, where the channel selection box 150 determines the number of iterations required to upconvert the selected input signal and the branch it is going to be placed by selecting the sign of the coefficients (i. e. inverted or not) Figure 20 shows the complete transmitter diagram with the digital IF section. This is similar to figure 13 with signals following reverse paths.

The baseband I & Q signals are complex to real upconverted to a near zero frequency fi and the channel selection box decides where to place the signal lower or upper frequency and the number of iterations required to upconvert the signal to IF before the D/A.

Figure 21 shows a diagram of the signals xl (n), x2 (n) and x (n) as applied to Figure 18.

The bandwidth is doubled and both the input signals are stacked together and simultaneously upsampled and upconverted. If only one channel is selected then only one of the signals is upsampled and upconverted.

Referring back to figure 20, if the signal output from parallel serial converter 160 fed back to channel selection block 150 has insufficient bandwidth/sampling rate, the signal is again applied to the filters h and c to be upsampled and upconverted.