INCORPORATION BY REFERENCE

[01 ] This application claims the benefit under 35 USC 120 and priority to, as a continuation-in-part of patent application No.: 16/375,059, titled “Multiple Window, Multiple Mode Image Sensor,” filed: April 4, 2019, which claimed the benefit under 35 USC 120 and priority to, as a continuation-in-part of, US application No. 16/175,662, titled “Extended dynamic range imaging sensor and operating mode of the same,” filed on October 30, 2018, which claimed the benefit as a continuation application of U.S. Patent Application Serial No. 15/238,063 titled “Extended dynamic range imaging sensor and operating mode of the same,” filed on August 16, 2016, which claimed the benefit under 35 USC 119 of U.S. provisional patent application serial No. 62/206,417, filed on August 18, 2015 and entitled “Extended dynamic range (XDR) CMOS pixel and operating mode.” All of the applications are incorporated mentioned in this specification are herein incorporated by reference in their entirety to the same extent as if each individual publication was specifically and individually indicated to be incorporated by reference.

GOVERNMENT RIGHTS

[02] This invention was made with government support under the Other

Transaction Agreement W909MY-18-9-0001 awarded by the U.S. Army Contracting Command. The government has certain rights in the invention.

BACKGROUND

[03] The field of the invention relates generally to imaging devices. More particularly, an embodiment of the present disclosure is directed to complementary

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SUBSTITUTE SHEET RULE 26 metal-oxide-semiconductor ("CMOS")-based imaging sensors capable of a wide range of operation.

[04] Imaging sensors typically include an array of pixels that contain lightsensitive elements commonly known as photodetectors, such as CMOS or charge- coupled device ("CCD") sensors. In general, photodetectors accumulate charge in accordance with the incident light during what is known as an integration period.

[05] A previous quad pixel imager had a sense node that needed to be large enough so four photodiodes can sequentially transfer signal charge through four transfer gates directly into that sense node. This geometry can result in a higher capacitance sense node than non-quad pixel imagers partially because of the four sequential transfers and their transfer gates coupling to the sense node. In addition, the sense node needs be large in order to directly receive charge from the photodiodes. Therefore, read noise can be higher than non-quad pixels.

[06] A rolling shutter can image capture a still picture or a single frame of a video, which is not captured by taking a snapshot of the entire scene at a single instant in time (e.g. a global shutter) but rather by scanning rapidly across the rows of pixels, and then performing a readout operation.

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SUBSTITUTE SHEET RULE 26 SUMMARY

[08] A machine, a process, and a system are discussed for a multiresolution imager that is capable of night vision. An image sensor has a set of pixels making up the image sensor to capture an image. Two or more pixels in the set of pixels each have an architecture that includes multiple photodiodes that can be formed by the controller into an individual pixel. The control system is configured to cooperate with the multiple photodiodes in the individual pixel, including a first photodiode and a second photodiode of the multiple photodiodes. Each photodiode can have a transfer gate electrically coupled to that photodiode. A common region can hold or transfer charge at least during or after an integration time. A read gate electrically coupled to the common region and a sense node can supply charge from the common region through the read gate to the sense node. Thus, the common region can be operated as a charge transfer channel to move charge from the transfer gate output to the sense node. Each pixel can have at least one of 1 ) the common region electrically coupled to the sense node, 2) one or more read gates electrically coupled to the sense node, and 3) any combination of both, to hold or transfer charge received from at least the first photodiode, at least during or after an integration time. [09] These and other features of the design provided herein can be better understood with reference to the drawings, description, and claims, all of which form the disclosure of this patent application.

BRIEF DESCRIPTION OF THE DRAWINGS

[010] Figure 1 illustrates an embodiment of a block diagram of an example pixel with multiple photodiodes simultaneously collecting charge to be moved through an associated photodiode transfer gate, into a common region, during or

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SUBSTITUTE SHEET RULE 26 after an integration time, as well as a read gate electrically coupled to the common region to transfer the binned charge from the common region through the read gate to the sense node during a read operation.

[011] Figure 2 illustrates an embodiment of a block diagram of an example pixel with multiple photodiodes simultaneously collecting charge transferred through each transfer gate into multiple common regions during an integration time, and then supplying the charge in each common region through a read gate coupled to that common region to be binned together in a sense node.

[012] Figure 3 illustrates an embodiment of a block diagram of an example image sensor having a set of pixels making up the image sensor to capture an image.

[013] Figure 4 illustrates an embodiment of a block diagram of a control system and pixel array for an image sensor having a set of pixels making up the image sensor to capture the image, where each pixel has an architecture that includes multiple photodiodes forming the individual pixel similar to the example pixels shown in Figures 1 -2.

DETAILED DISCUSSION

[014] As will be discussed in much detail later, the control system for the pixel and its components can send control signals to change the way these components operate via changing their imaging modes of operation. The architecture of the pixel and its components support an example imaging mode of operation, which is a low light mode using a rolling shutter process that incorporates some aspects of a global shutter process. The low light mode using a rolling shutter process using the pixel and its components allows the imager to trade resolution for

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SUBSTITUTE SHEET RULE 26 low light level sensitivity as well as provides an extended dynamic range. The low light mode using a rolling shutter process with the pixel and its components uses charge binning from multiple photodiodes, at a same time, in the rolling shutter mode, during the integration time, to improve the dynamic range and the low light level sensitivity. A baseline imager pixel for a night vision camera with reduced read noise and longer detection range at the lowest of light levels can use the low light mode using a rolling shutter process with the pixel and its components charge binning from multiple photodiodes at a same time during the integration time. Again, other imaging modes of operation with this pixel architecture are possible and will be discussed later but the pixel architecture and how the control system will operate these components in the low light mode using a rolling shutter process, to bin charge from multiple photodiodes at a same time, during the integration time will be initially discussed.

[015] Figure 1 illustrates an embodiment of a block diagram of an example pixel with multiple photodiodes simultaneously collecting charge to be moved through an associated photodiode transfer gate, into a common region, during or after an integration time, as well as a read gate electrically coupled to the common region to transfer the binned charge from the common region through the read gate to the sense node during a read operation.

[016] Each pixel in the image sensor has an architecture that can include multiple photodiodes and other components forming the individual pixel 100.

[017] The pixel 100 is a ‘detector’ of light for the image sensor. These can be individual photodiode readouts through a common output stage. In addition, charge from multiple photodiodes can be readout through the common output stage. The controller can send control signals to the photodiodes such that without binning,

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SUBSTITUTE SHEET RULE 26 one photodiode can be within one pixel, but with binning, up to, for example, four photodiodes can have their charge binned to form one pixel. Thus, with no binning one photodiode and the other components making up a pixel 100 can be one pixel in the display. This is how a simple camera would see this. Also, the image sensor in an example video camera may be listed as a 24 megapixel image sensor. The measure of pixels in the image sensor typically refers to the minimal displayable unit, so this refers to the unbinned case, where each “pixel” is operated to be a photodiode. However, as discussed in different modes of operation of a more advanced camera or a video camera, the controller may operate those, for example, 24 mega pixels in different ways to form each pixel detecting light. If the controller bins all four photodiodes, then the four photo diodes and the other components making up a pixel 100 can form one pixel in the display. Therefore, in essence, four photo diodes would to be a single pixel in the display. There are photo diodes and displayed pixels. The common output stage does not always define a pixel. A pixel is how the photo diodes appear in an output to form the image. An imager sensor with N pixels (in this case N is the individual photo diodes) has the capability of, for example, 4 to 1 or 2 to 1 charge binning of these photodiodes. The group of binned pixels does become the displayed pixel.

[018] Again, in a mode of operation controlled by the controller, the multiple photodiodes making up a pixel 100 are readout through a common output stage. For example, a quad pixel has all four photo diodes converted from charge to voltage and sent to a signal line by the common output stage. The photo diodes can be binned or not binned but will all pass through the common output stage. The common output stage can be considered to consist of: the sense node SN, a source follower buffer SF, a row select transistor SEL and a reset transistor RST which is

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SUBSTITUTE SHEET RULE 26 integrated with the sense node. All these components are related to reading out the signal.

[019] The individual pixel 100 can have multiple photodiodes, e.g. PD1-PD4, which each have an associated transfer gate TG1-TG4 electrically coupled to that photodiode. The multiple photodiodes PD1-PD4 can form the individual pixel 100, during integration time, collect photons to create charge and then can direct the charge signals through its own transfer gate (respectively TG1-TG4) associated with that photodiode. The charge from two or more of the photodiodes PD1-PD4 can be essentially ‘noiselessly’ binned simultaneously in the common region SR during a phase of the integration time.

[020] Two or more pixels in the set of pixels each have an architecture that includes multiple photodiodes that can be formed by the controller into an individual pixel 100. The control system is configured to cooperate with the multiple photodiodes in the individual pixel 100 to include at least a first photodiode PD1 and a second photodiode PD2 of the multiple photodiodes. The multiple photodiodes are readout through a common output stage that includes the sense node SN. The pixel 100 further can include at least one of 1 ) a common region SR electrically coupled to the sense node SN to hold or transfer charge received from at least a photodiode, at least during or after an integration time, 2) one or more read gates TX electrically coupled to the sense node SN to hold or transfer charge received from at least a photodiode, at least during or after the integration time, and 3) any combination of both 1 ) and 2) to hold or transfer charge received from at least a photodiode, at least during or after the integration time.

[021] This common region SR electrically couples to each transfer gate TG1-TG4. This common region SR also couples, via a read gate TX, to the sense

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SUBSTITUTE SHEET RULE 26 node SN. One or more common regions SR can be implemented and each is configured to i) temporarily transfer thru the charge during a clock cycle or so e.g. see Figure 2; or ii) hold charge for a long duration such as capable of storing a charge for many clock cycles e.g. see Figure 1 . The common region SR generally bins/sums the charge from the multiple photodiodes PD1-PD4, at the same time, during the integration time, when in the low light mode using the rolling shutter process. A read gate TX electrically couples to the common region SR and a sense node SN in order to supply charge from the common region SR through the read gate TX to the sense node SN during a read operation.

[022] The common region SR is used for binning charge from two or more of the photodiodes PD1-PD4 in the integration time and transferring charge during a read out operation. In a first case, when charges passes through the common region SR ultimate binning occurs at the sense node SN. Some binning will occur in the common region SR when operated this way. In a second case, when charge is stored in common region SR then all of the binning occurs in the common region SR. Note, in other modes of operation, the common region SR is also used for a single photo diode readout for high resolution. In this case there is no binning, but the signal follows the same path as binning multiple diodes. Reading a single pixel is different from global shutter. Charge is held in the common region SR for a fraction of a row time. For global shutter operation, charge is held in the common region SR at least a full row time but more likely multiple row times.

[023] The sense node SN is used to read out charge during a read out operation. The sense node SN can achieve a high conversion gain and lower readout noise by converting charge to a voltage signal when the sense node SN has a lower capacitance. A size of the sense node SN can be set small enough to

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SUBSTITUTE SHEET RULE 26 accommodate to connect merely to, in this example, the one read gate TX verses all four of the transfer gates TG1-TG4 in order to lower a noise threshold required during a read operation. Note, to complete the read operation, a sense node reset occurs, after a readout, when the reset gate RST is turned on.

[024] During the readout operation, the charge in the sense node SN is readout using the source follower transistor SF and the row select transistor SEL, producing a voltage signal on the column bus (which has a current source load). The readout transistors that cooperate for the read operation are labeled: read gate (TX), Source Follower (SF), Row Select (SEL), and Reset (RST).

[025] A first step of a read operation can be to transfer the charge being held in the common region SR to the sense node SN for has been broken into two distinct steps (e.g. 1 ) the transfer gates TG1-TG4 are switched off and then 2) the read gate TX is turned on.

[026] Thus, charge is binned in a potential well-formed preferably by a buried channel well. The charge is transferred from multiple photodiodes to the common region SR with its potential well. In the common region SR more than one photodiode can be summed/bin in the well. Next, a second transfer from the potential well to the sense node SN generates the voltage output. This low light mode allows a smaller sense node so charge conversion of Volts/electron is higher; and therefore, read noise lower.

[027] In an example low light operation, at least the top two photodiodes PD1-PD2 and their associated transfer gates TG1-TG2 are sent control signals by the control system to have these transfer gates to ‘switch on’ in order to simultaneously supply their charge to the common region SR during the integration time. In the common region SR, the charge from at least these two photodiodes

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SUBSTITUTE SHEET RULE 26 PD1-PD2 is binned during the integration time. For the even lowest noise and most extended range imaging mode of operation, all four photodiodes PD1-PD4 and their associated transfer gates TG1-TG4 are sent control signals to simultaneously ‘switch on’ in order to transfer their charge to the common region SR during the integration time in order for the common region SR to bin the charge from all four photodiodes PD1-PD4 simultaneously. When all four photodiodes have their charge binned in the common region simultaneously, then merely one read operation on the sense node SN occurs to read that binned charge; whereas, typically the noise associated with four sequential read operations is required to obtain the total charge from all four photodiodes PD1-PD4. Noise is thus reduced by three read operations compared to some other quad pixel designs. In addition, the common region holds (potentially storing) charge from the multiple photodiodes PD1-PD4 and then transfers the binned/summed charge to the sense node SN in order to keep a size dimension of the sense node SN small and any parasitic transfer gate capacitance also small in order to reduce readout noise. The common region SR transferring charge during a read operation allows the sense node SN and its read gate TX to be small and have less capacitance. Merely one read gate TX (in some architectures two read gates) couples to the area making up the sense node SN rather than four transfer gates TG1-TG4 that each add parasitic capacitance to the sense node SN. The lower capacitance allows better noise levels during a read operation, which allows detection in low light conditions (e.g. a moonless night with merely starlight), and lowers the noise threshold level at which no useable signal can be detected. [028] Structurally, each transfer gate TG1-TG4 has its own channel formed under each of the transfer gates TG1-TG4 to feed charge to the common region. At least a portion of a well forming the common region SR is located underneath each

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SUBSTITUTE SHEET RULE 26 transfer gate TX if more than one are implemented. The potential well is formed preferably by a buried channel well. The transfer gates TG1-TG4, such as a transistor, metal oxide device, etc., for each photodiode have control signals going to them from the control system to control the integration time for that particular photodiode; and thus, how long that associated photodiode e.g. PD1-PD4 collects photons before its associated transfer gate TG1-TG4 allows the accumulated charge from the photodiode to move to the common region SR.

[029] Note, in an embodiment, the common region SR is constructed with a well that is built to store charge over many cycles. The common region can be a well that stores charge potential which can be formed by a virtual gate or a poly gate. A challenge with the pixel architecture in Figure 1 is that because charge is stored in the common region, then the area needs to be a large enough to hold the desired maximum charge. This reduces space available for photodiodes PD1-PD4 and lowers quantum efficiency. Without the inspiration that this architecture could result in lower noise, this approach might not seem logical. Also, if the common region SR becomes too large, transferring charge to the sense node SN can take a longer time than desired/allowed in the operational mode. Therefore, in an embodiment, charge capacity of the common region SR can be set to small enough to allow for the required charge transfer time to the sense node SN and then merely to a minimum needed to support actually storing the anticipated amount of charge.

[030] The common region SR can have charge channels. The common region SR can have charge channels from a photodiode output from each of the photodiodes PD1-PD4 and that run beneath the transfer gate TG1-TG4 associated with its photodiode, through the well of the common region SR, and to the read gate TX. Note, the too large of a sense node SN problem can be solved by adding these

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SUBSTITUTE SHEET RULE 26 charge channels from the photodiode output and under the transfer TG gate, through the well, and to the read gate TX, which allows the sense node SN to be remote from the four photodiodes PD1-PD4, but still in the pixel. With the addition of the channel spanning from the output of the photodiode to the well of the sense node SN and onto the read gate, allows the well to no longer need to be large enough to accommodate a direct transfer of charge from all the four photodiodes PD1-PD4 simultaneously. Again, this approach can reduce noise to or near to the noise threshold level for imager that do not use a quad pixel architecture.

[031] The common region SR between the transfer gates TG1 -TG4 and the sense node can be a charge binning region with a read gate to hold/store that charge in the common region SR. The common region SR is where charge from the four photodiodes PD1-PD4 are binned and then transferred to the sense node SN through one read gate TX1 . This charge binning region can hold/store charge for a frame time to allow global shutter operation, and this charge binning region can also hold charge for less than a row time for rolling shutter operation.

[032] The image sensor containing the pixels has a control system that can implement a rolling shutter, a global shutter, as well as operate in different imaging modes of operation. The control system can send control signals to operate the image sensor in a hybrid global shutter and rolling shutter operational mode. In this rolling shutter mode with some global shutter aspects, the control system starts an integration time by sending control signals to simultaneously collect charge from multiple photodiodes, and by sending another signal to transfer the accumulated in the multiple photodiodes through an associated transfer gate TG coupled to that photodiode into a common region SR. The common region SR sums/bins charge supplied by the two or more photodiodes PD1-PD4 during the integration time.

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SUBSTITUTE SHEET RULE 26 During a read operation, the control system sends control signals to transfer the binned charge in the common region SR through a read gate TX to a sense node SN. The image sensor with the rolling shutter reads out a row of photodiodes in the image sensor on row of photodiodes by row of photodiodes basis instead of all of the rows being read at a same time.

[033] An advantage of the pixel architecture in Figure 1 is the 4X binned pixel can be operated in either a global shutter mode simultaneous binning of all of the photodiodes with all rows read at the same time or preferably in a rolling shutter mode with an aspect of simultaneous binning of multiple photodiodes, but on a row by row basis, which provide less geometric distortion in the displayed image for moving objects.

[034] The quad pixel architecture may be a CMOS pixel with four photodiodes PD1-PD4 in the pixel 100 on a substrate.

[035] Figure 2 illustrates an embodiment of a block diagram of an example pixel with multiple photodiodes simultaneously collecting charge transferred through each transfer gate into multiple common regions during an integration time, and then supplying the charge in each common region through a read gate coupled to that common region to be binned together in a sense node. Note, as shown the common region is actually part of each read gate TX1-TX2. Thus, the one or more read gates include at least a first read gate TX1 and a second read gate TX2 as well as are configured to function as the common region. The common region (SR from Figure 1 ) is thus split into a first common region (TX1 as shown in Figure 2) to transfer the charge from the first photodiode PD1 and the second photodiode PD2 during the integration time, and a second common region (TX2 as shown in Figure 2) to transfer charge from a third photodiode PD3 and a fourth photodiode PD4 during

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SUBSTITUTE SHEET RULE 26 the integration time. The read gates TX1 -TX2 here act as a conduit leading charge to sense node. They can only transfer charge but not store charge.

[036] The pixel architecture of Figure 2 has two read gates, TX1 and TX2. Each read gate TX1 or TX2 couples to two transfer gates TG1-TG2 or TG3-TG4 and then to the sense node SN. Unlike the common region SR in Figure 2 which can store charge until slowly and securely being transferred to the sense node SN, a portion of the transfer gate TG1-TG4, here merely temporarily holds onto charge. The two read gates TX1 -TX2 serve as charge transfer gates to the sense node SN. The charge from the four photodiodes PD1-PD4 is actually binned in the sense node. Thus, the charge binning of 2, 3, or all 4 photodiodes simultaneously can be performed by this architecture but in the sense node SN instead of in a common region. Note, the common regions can act as channel to the sense node SN directly from the associated TG gate output TG1-TG4.

[037] Read gates TX1 and TX2 can be implemented by using a poly gate. The small size of read gates TX1 and TX2 also permits larger photodiodes PD1- PD4 within a given quad area resulting in higher quantum efficiency. The sense node SN area is still much smaller than previous designs. Merely two small read gates TX couple to the area of the sense node SN rather than four transfer gates TG1-TG4 that each add parasitic capacitance to the sense node SN. The overlap capacitance is further reduced by the small size of the sense node SN.

[038] In Figure 2, in an embodiment, the architecture needs no read gate TX. Instead, the architecture could have a common region coupled to the sense node and one or more transfer gates (TG). The common region can be configured to transfer and move charge to the sense node during integration time. The common region need not hold the charge but merely transfer the charge.

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SUBSTITUTE SHEET RULE 26 [039] Referring to Figure 1 , the example pixel with multiple photodiodes simultaneously collects charge transferred through each transfer gate into multiple common regions for summing/binning charge supplied by two or more photodiodes during an integration time, and then supplying the binned charge in each common region through a read gate to a sense node during a read operation.

[040] The pixel 100 has four transfer gates TG1-TG4 each on an edge of its associated photodiode PD1-PD4. A center channel between the top two transfer gates TG1 - TG2 acts as a common region SR1 to store charge of two photodiodes PD1-PD2 as well as bins the charge from these two photodiodes PD1 - PD2.

Likewise, a center channel between the top two transfer gates TG3 - TG4 acts as a common region SR2 to store charge of two photodiodes PD3-PD4 as well as bins the charge from these two photodiodes PD3 - PD4. All four of the transfer gates TG1-TG4 electrically couple to a read gate TX through their channel. The read gate TX couples to the sense node SN. The sense node SN also has a gain capacitor GC electrically coupled to the sense node SN.

[041] In an embodiment, the first storage region SR1 is a well formed by the long and deep center channel between the top two transfer gates TG1 - TG2. The second storage region SR 2 is a well formed by the long and deep center channel between the bottom two transfer gates TG3 - TG4.

[042] The read gate TX1 transfers the charge from the first common region SR1 and the second common region SR2 through the read gate TX1 to the sense node SN during the read operation.

[043] Figure 3 illustrates an embodiment of a block diagram of an example image sensor having a set of pixels making up the image sensor to capture an image. The image sensor has an array 500 with columns and rows of pixels. In this

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SUBSTITUTE SHEET RULE 26 example, the image sensor is configured to capture an image, and has five rows and columns of pixels (rows 1 -5) including an example pixel 100.

[044] Figure 4 illustrates an embodiment of a block diagram of a control system and pixel array for an image sensor having a set of pixels making up the image sensor to capture the image, where each architecture includes photodiodes similar to the example pixels shown in Figures 1 -2. The control system may include components such as a controller having two or more decoders implemented in Analog/ADC circuits, a column and row control circuit for each transfer gate of the photodiodes in the quad pixel array of pixels 500, the MIM gain capacitor, the read gates, the Reset switch, and the Row select switch, column logic drivers, and a timing circuit.

[045] The control system can use two or more decoders. The two or more decoders cooperate with a timer to direct control signals to control i) frame rate, ii) integration times of the multiple photodiodes, and iii) binning of the multiple photodiodes on a per pixel basis to allow multiple pixels in the array 500 of pixels to operate in the different imaging-modes of operation. Again, the control system is configured to cooperate with the multiple photodiodes to configure the multiple photodiodes to form the detector of the individual pixel and/or a single photodiode to form the detector of the individual pixel.

[046] The control system in night vision/low light mode can be configured to send a first control signal for the multiple photodiodes to simultaneously collect charge during an integration time and the associated transfer gates to switch off.

Next, the associated transfer gates upon receiving a second control signal to move the charge accumulated in at least two or more of the multiple photodiodes at a same time through their associated transfer gate coupled to that photodiode into one or more common regions for holding the charge for a subsequent read operation. In

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SUBSTITUTE SHEET RULE 26 many of the architectures, the one or more common regions bin charge supplied by the two or more photodiodes during the integration time. The read gates are also switched off to keep the charge in the common regions until the read operation occurs. The control system then sends a third control signal during a read operation to transfer the binned charge in the common region through the read gate, by switching the read gate on, to the sense node. The transfer gates can also receive a signal to make sure no charge leaks back into the photodiodes. The control system when operating in a rolling shutter mode is configured to do the above sequence a on row of photodiodes by row of photodiodes basis doing all of the rows within a time frame of one image frame. The control system can send a control signal to the rest of the set of read transistors (discussed earlier) and the gain capacitor to finish off the read operation.

[047] The control system is configured to analyze the scene being captured in an image. The control system selects different imaging-modes of operation for two or more pixels in a row based on imaging conditions in the scene content, such as different light intensities and frame rate needed, within the scene being captured by the plurality image pixels. The controller may operate the imaging sensor by: selecting a different imaging-mode of operation for at least two pixels based on imaging conditions captured in the pixel 100; and assembling an image using collected data signals reflective of the accumulated charge and other imaging conditions obtained from a plurality of pixels from the readout.

[048] All of the pixel architectures in Figures 1 -2 can include an extra MIM capacitor GC to allow switchable capacitance to sense node SN to alter the capacitance; and, resulting gain.

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SUBSTITUTE SHEET RULE 26 [049] The control system can be configured to transfer charge to a common region, store the charge there more than a row time, and then readout with a readout gate TX. The control system can also be configured to transfer charge to a common region in order to bin there and store charge there only for a fraction of row. The purpose is completely different.

[050] The image sensor routes the wire traces/conductor paths for the control signals to allow different modes of operation with the example quad pixel/electrical circuit. The controller may control the timing of control signals to each pixel in each row of the imager in order to achieve the envisioned imaging-modes of operation that include:

[051] 1 .) An unbinned photodiode readout of photodiodes PD1-PD4 sequentially in order, each potentially with a different integration time for a high resolution. Each transfer gate associated with its photodiode is sequentially switch on in order to transfer charge from the photodiode through the associated transfer gate into the common region. For the highest resolution readout mode, the control system during an integration time sends signals to sequentially collect charge from a single photodiode and transfers the charge using the associated transfer gate to the common region potential well. Charge in the common region is then transferred to the sense node using the transfer gate. Alternatively, charge is transferred to the sense node by merely using the transfer gate. Again, the control system repeats this process sequentially in order for the other three photodiodes.

[052] 2.) For the highest sensitivity mode, all four photodiodes can have their charge noiselessly binned in one common region sequentially to form a super pixel with 4X signal. Next, during the read operation, the binned charge stored in storage region is transferred so to sense node using the read gate.

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SUBSTITUTE SHEET RULE 26 [053] 3.) A binned photodiode readout of multiple photodiodes simultaneously or with each in one or more storage regions. For example, 1 ) all of the photodiodes, e.g. PD1-PD4, are simultaneously binned in one common region or 2) each pair e.g. PD1 - PD2, and then e.g. PD3 - PD4 having their accumulated charge from their integration times binned together in their own common regions during integration time. When all of the charge from the photodiodes is not binned in one common storage region during the integration time, a binned photodiode readout mode can have multiple photodiodes having their accumulated charge from their integration times binned together at the sense node. The controller can bin any combination, for example, of two, three, or four photodiodes e.g. PD1-PD4 to collect and read out charge/signal level. The controller and the timer cooperate to have the transfer gates of the binned photodiodes switched on and the read gate for the common region switched off, via pulsed all at a same time. The binning of charge from multiple photodiodes in a common region and then to the sense node, increases the effective exposure, sensitivity; and thus, a better resolution.

[054] 4.) A high frame rate imaging mode of operation for motion adaptive signal integration (MASI) and/or short integration time with high gain for motion blur reduction. A high frame rate for motion adaptive signal integration (MASI) can be an imaging-mode of operation using a readout of photodiodes from a pixel 100 with multiple photodiodes. The high frame rate MASI algorithm achieves a high dynamic range by combining high frame rate images of varying exposures. The high frame rate mode can still implement binning, unbinned, and extended dynamic range in a given pixel 100. Note, a high frame rate could also cut out a certain amount of rows or even individual pixels from being read to match a data throughput of the image sensor. Thus, the first decoder can select a subset of the rows, such as 60 rows,

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SUBSTITUTE SHEET RULE 26 which will have their charge readout from a total amount of rows, such as 80 rows, making up that image sensor.

[055] 4) Extended dynamic range from low lighting conditions up to sunny conditions. The extended dynamic range imaging-mode of operation can be an imaging-mode of operation using a readout of multiple photodiodes from a pixel 100. The dynamic range can be a metric of how well a sensor can measure an accurate signal at low light intensities all the way up until it reaches full well capacity. The extended dynamic range can be achieved by adjusting the effective integration time of the four photodiodes.

[056] In an embodiment, the quad pixel design discussed herein are capable of providing 2X (or more) read noise reduction when compared to some other prior designs. In one embodiment, the system consists of a quad design where four, 8x8 urn pixels are either individually read out or their charge is combined/binned to form a 16x16 urn super pixel. The 16 x 16 urn pixel collects 4X more signal for the lowest light levels. This design reduces read noise by 2X while allowing improved imaging with merely starlight illumination.

[057] The present invention has been described in terms of one or more embodiments, and it should be appreciated that many equivalents, alternatives, variations, and modifications, aside from those expressly stated, are possible and within the scope of the invention.

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SUBSTITUTE SHEET RULE 26