Title:
MULTITHREAD CENTRAL PROCESSING DEVICE AND SIMULTANEOUS MULTITHREADING CONTROL METHOD
Document Type and Number:
WIPO Patent Application WO/2006/129767
Kind Code:
A1
Abstract:
The prediction accuracy of the thread execution time by a CPU capable of carrying out simultaneous multithreading is improved. The priority of each thread is set in the CPU, and the processing order/frequency of the instructions of threads is controlled so that a thread of high priority is preferentially processed before a thread of low priority in principle. Thus, competition for resources between the threads simultaneously processed is arbitrated. Further, the target value of the number of execution instructions of each thread is set in the CPU, the execution instructions per cycle of each thread are counted cyclically. The instruction processing order/frequency using priority is corrected by feedback control on the basis of comparison of the number of execution instructions and the target value. In such a way, even if any combination of threads are simultaneously processed, the execution time (or IPC) of each thread is stably kept near a desired value.
Inventors:
YAMASAKI NOBUYUKI (JP)
Application Number:
PCT/JP2006/311022
Publication Date:
December 07, 2006
Filing Date:
June 01, 2006
Export Citation:
Assignee:
UNIV KEIO (JP)
YAMASAKI NOBUYUKI (JP)
YAMASAKI NOBUYUKI (JP)
International Classes:
G06F9/50
Foreign References:
| JP2004532444A | 2004-10-21 | |||
| JP2004287883A | 2004-10-14 | |||
| JP2882475B2 | 1999-04-12 | |||
| JPH10124316A | 1998-05-15 |
Attorney, Agent or Firm:
Willfort International (3-2 Kajicho 2-chome, Chiyoda-k, Tokyo 44, JP)
Download PDF:
Previous Patent: SEMICONDUCTOR IMAGE SENSOR MODULE AND METHOD FOR MANUFACTURING SAME
Next Patent: STACKED PORTABLE TERMINAL
Next Patent: STACKED PORTABLE TERMINAL