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Title:
NANO EMISSION DEVICES, INTEGRATED CIRCUITS USING NANO EMISSION DEVICES, AND RELATED METHODS
Document Type and Number:
WIPO Patent Application WO/2008/051300
Kind Code:
A3
Abstract:
Embodiments of the present invention are generally directed towards nano emission devices. Nano emission devices can include, for example, diodes (1200), N-type transistors (100, 200, 250, 500, 600, 900), P-type transistors (250, 300, 500, 600, 800, 900, 1500), and combined N- and P- type nano emission transistors (400). Nano emission devices can include multiple emitters, collectors, gates and the like to form more complex nano emission devices (1600, 1900, 2200). Nano emission devices may be connected together to form various circuits, including for example, logic gates (1402, 1404, 1408), memory cells (1406), amplifiers, and the like. Nano emission devices may be fabricated in two- and three-dimensional integrated circuits (1700, 2300, 2400). Methods of fabricating (700, 750, 1100, 2500, 2600) nano emission devices and electronic circuits are also described.

Inventors:
SUMMERS, David (808 East 1910 South, Provo, UT, 84604, US)
BROWN, Phil (808 East 1910 South, Provo, UT, 84604, US)
Application Number:
US2007/009829
Publication Date:
October 02, 2008
Filing Date:
April 19, 2007
Export Citation:
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Assignee:
KANZEN INC. (808 East 1910 South, Provo, UT, 84604, US)
SUMMERS, David (808 East 1910 South, Provo, UT, 84604, US)
BROWN, Phil (808 East 1910 South, Provo, UT, 84604, US)
International Classes:
H01J1/30
Foreign References:
US5204588A1993-04-20
US6864162B22005-03-08
Attorney, Agent or Firm:
NORTH, Vaughn, W. et al. (Thorpe North & Western, LLPPO Box 121, Sandy UT, 84091-1219, US)
Download PDF:
Claims:

CLAIMS

What is claimed is:

1. A nano emission device (100) comprising: an insulating body (112) having a channel cavity (110) formed therein; an emitter terminal (102) disposed within the body and extending into the channel cavity at a first position within the channel cavity; a collector terminal (104) disposed within the body and extending into the channel cavity opposite the emitter terminal at a second position within the channel cavity; and a gate terminal having at least two gate portions (106a, 106b), the gate portions disposed at opposite sides of the channel cavity between the first position and the second position of the channel cavity, a portion (114, 116) of the insulating body interposed between the gate portions and the channel cavity. 2. A nano emission device (200) comprising: an insulating body (112) having a channel cavity (110) formed therein; an emitter terminal (102) disposed within the body and extending into the channel cavity at a first terminal position within the channel cavity; a collector terminal (104) disposed within the body and extending into the channel cavity opposite the emitter terminal at a second terminal position within the channel cavity; and a gate terminal (206) extending circumferentially around the channel cavity at a first gate position between the first terminal position and the second terminal position, a portion of the insulating body extending between the gate terminal and the channel cavity.

3. A device as in claim 2, further comprising at least a second gate terminal (206b) extending circumferentially around the channel cavity positioned at a second gate position between the first terminal position and the second terminal position, a portion of the insulating body interposed between the second gate terminal and the channel cavity.

4. A nano emission device (300) comprising: an insulating body (312) having a channel cavity (310) formed therein, the insulating body having an insulating extension (318) protruding into an interior of the channel cavity; an emitter terminal (302) disposed within the insulating body and extending into the channel cavity at a first position; a collector terminal (304) disposed within the insulating body and extending into the channel cavity at a second position on an opposite side of the insulating extension from the emitter terminal; and a gate terminal (306) disposed at a side of the channel cavity between the first position and the second position, the gate terminal being separated from the channel cavity by a portion (316) of the insulating body so that a voltage applied to the gate terminal can deflect electrons around or into the insulating extension depending on the voltage applied thereto. 5. A device as in claim 4, wherein the insulating extension intercepts a straight path from the emitter terminal to the collector terminal.

6. A device as in claim 4, wherein the voltage applied to the gate terminal can influence electrons emitted from the emitter terminal so that electrons accumulate at a position (310) adjacent to the insulating extension to inhibit current flow from the emitter terminal to the collector terminal.

7. A device as in claim 4, wherein the voltage applied to the gate terminal can influence electrons emitted from the emitter terminal so that electrons are deflected around the insulating extension to enable current flow from the emitter terminal to the collector terminal. 8. A device as in claim 4, wherein a positive voltage applied to the gate terminal relative to the emitter inhibits current flow from the emitter to the collector.

9. A device as in claim 4, further comprising a plurality of gate terminals (206a, 206b, 206c) positioned between the first position and the second position, each gate terminal configured such that a voltage applied thereto can influence the path of electrons within the channel cavity.

10. A device as in claim 4, wherein the gate further comprises a gate portion (2209) extending into the insulating extension.

11. A nano emission device (400) comprising: an insulating body (412) having a channel cavity (410) formed therein, the channel cavity having an insulating extension (418) protruding into an interior of the channel cavity; an emitter terminal (402) disposed within the body and extending into the channel cavity at a first position within the channel cavity; a collector terminal (4040) disposed within the body and extending into the channel cavity at a second position within the channel cavity on an opposite side of the insulating extension from the emitter terminal; a first gate terminal (406) disposed at a side of the channel cavity between the first position and the second position, the first gate terminal being separated from the channel cavity by the insulating extension (418) and a portion (416) of the insulating body; and a second gate terminal (408) disposed at an opposite side of the channel cavity from the insulating extension, the second gate terminal being separated from the channel cavity by a portion (414) of the insulating body.

12. A device as in claim 11, wherein the insulating extension intercepts a straight path from the emitter terminal to the collector terminal.

13. A device as in claim 11, wherein a voltage applied to the first gate affects current flow in an opposite manner from a voltage applied to the second gate.

14. A device as in claim 11, wherein the first gate further comprises a gate portion (2209) extending into the insulating extension. 15. A nano emission device (1600) comprising: a channel cavity (1602) within an insulating body (1604); an emitter terminal (1606) supported by the insulating body and having a portion extending into the channel cavity; a plurality of collector terminals (1808a, 1608b) supported by the insulating body and extending into the channel cavity; and at least one gate terminal (1610a, 1610b) disposed within the insulating body at a position between the emitter terminal and the plurality of collector terminals, the

at least one gate terminal being separated from the channel cavity by a portion of the insulating body and being configured so that a voltage applied to the at least one gate terminal can direct current flow from the emitter to substantially one of the plurality of collector terminals. 16. A nano emission device (1408) comprising: a first emitter terminal; a first collector terminal located opposite the first emitter terminal; a first gate terminal located between the first emitter terminal and the first collector terminal; a first channel cavity between the first emitter terminal and the first collector terminal, the first channel cavity including a first charge accumulation location within the first channel cavity wherein a positive voltage on the first gate terminal encourages charge accumulation at the first location to impede current flow through the channel cavity; a second collector terminal electrically connected to the first emitter terminal to form an output terminal; a second emitter terminal located opposite the second collector terminal; a second gate terminal located between the second emitter terminal and the second collector terminal, the second gate terminal being electrically connected to the first gate terminal to form a control terminal; and a second channel cavity between the second emitter terminal and the second collector terminal, wherein a positive voltage on the second gate terminal encourages current flow through the second channel cavity.

17. A device as in claim 16, wherein the voltage applied to the control terminal switches substantially all current either (i) to flow in a direction from the output terminal to the first collector or (ii) to flow in a direction from the second emitter to the output terminal, the direction being dependent on the voltage applied to the control terminal.

18. A device as in any one of claims 1 - 17, wherein the emitter terminal(s) and collector terminal(s) are disposed in a common plane. 19. A device as in any one of claims 1 - 17, wherein the emitter terminal(s), collector terminal(s), and gate terminal(s) are disposed in a common plane.

20. A device as in any one of claims 1 - 17, wherein the emitter terminal, collector terminal, and gate terminal are each formed of Tungsten.

21. A nano emission device (800) comprising: a first conductive terminal (802a); a second conductive terminal (804b) located adjacent to the first conductive terminal; a gate terminal (806) located between the first conductive terminal and the second conductive terminal; and a channel cavity (808) between the first conductive terminal and the second conductive terminal, the channel cavity including at least one charge accumulation location (810, 812) within the channel cavity wherein a positive voltage on the gate terminal encourages charge accumulation to impede current flow through the channel cavity.

22. A device as in claim 21, wherein the gate terminal is separated from the channel cavity by an insulating region (809).

23. A device as in claim 21, wherein the charge accumulation location is defined by an insulating region (809) protruding into the channel cavity.

24. A device as in claim 23, wherein the insulating region intercepts a straight path between the first conductive terminal and the second conductive terminal. 25. A device as in claim 21, wherein the first conductive terminal has at least one pointed portion (803) extending into the channel cavity to serve as an emitter.

26. A device as in claim 21, wherein the first conductive terminal and the second conductive terminal each have a pointed portion (803) extending into the channel cavity to function alternatively as an emitter and a collector. 27. A device as in claim 21, wherein a first voltage applied between the first conductive terminal and the second conductive terminal causes current flow between the first conductive terminal and the second conductive terminal, and a second voltage applied to the gate terminal controls an amount of current flow.

28. A device as in claim 21, wherein the gate terminal is located adjacent to the charge accumulation location.

29. A device as in claim 21, further comprising a plurality of gate terminals (206a, 206b, 206c) positioned between the first conductive terminal and the second conductive terminal.

30. A device as in claim 21, further comprising a second gate terminal (408) positioned opposite the cavity from the charge accumulation location.

31. A device as in any one of claims 21 - 30, wherein the conductive terminals are disposed within a common plane.

32. A device as in any one of claims 21 - 30, wherein the conductive terminals are each formed of Tungsten. 33. A device as in any one of claims 1 - 17 or 21 - 32, wherein the channel cavity is substantially evacuated.

34. A device as in any one of claims 1 - 17 or 21 - 32, wherein the channel cavity contains a gas.

35. A device as in any one of claims 1 - 17 or 21 - 32, wherein a longitudinal dimension (end to end) of the channel cavity is greater than a lateral (side to side) dimension of the channel cavity.

36. A device as in any one of claims 1 - 17 or 21 - 32, wherein a length of the channel cavity is in the range of about 0.1 to 10 micrometers.

37. A device as in claim 36 wherein the length of the channel cavity is about 2 micrometers.

38. A device as in any one of claims 1 - 17 or 21 - 32, wherein a width of the channel cavity is about 0.5 micrometers

39. A device as in any one of claims 1 - 17 or 21 - 32, wherein the channel cavity is encapsulated by silicon dioxide glass. 40. A device as in any one of claims 1 - 17 or 21 - 32, wherein the nano emission device is formed on an amorphous substrate (502).

41. A device as in any one of claims 1 - 17 or 21 - 32, wherein the nano emission device is formed on a polycrystalline substrate (502).

42. A device as in any one of claims 1 - 17 or 21 - 32, further comprising a heating element (2304) coupled to the device.

43. A device as in any one of claims 1 - 17 or 21 - 32, wherein the device is operable at a temperature greater than 200 degrees Celsius. 44. A device as in any one of claims 1 - 17 or 21 - 32, wherein the device is operable at a temperature greater than 500 degrees Celsius.

45. A device as in any one of claims 1 - 17 or 21 - 32, wherein the device is operable at a temperature greater than 1000 degrees Celsius.

46. A nano emission device as in any one of claims 1 - 17 or 21 - 32, wherein the insulating body comprises a first substrate surface on top of which the emitter terminal, the collector terminal, and the gate terminal are disposed; and the insulating body comprises a second substrate surface disposed above the emitter terminal, the collector terminal, and the gate terminal, the second substrate surface providing similar properties to the first substrate surface so that a second nano emission device can be formed on top the second substrate surface.

47. A nano emission device as in claim 46, wherein the properties of the first substrate surface and the second substrate surface include being amorphous.

48. An electronic circuit formed (1402, 1404, 1406, 1408) from a plurality of nano emission devices, the nano emission devices being any of the types described in claims 1 - 17 or 21 - 32.

49. An electronic circuit formed from a plurality of nano emission devices, the nano emission devices being any of the types described in claims 1 - 17 or 21 - 32 and disposed in a substantially planar arrangement on a substrate.

50. An electronic circuit formed from a plurality of nano emission devices, the nano emission devices being any of the types described in claims 1 - 17 or 21 - 32 and disposed in a substantially vertical arrangement on a substrate.

51. An electronic circuit (1000) formed from a plurality of nano emission devices, the nano emission devices being any of the types described above in claims 1 - 17 or 21 - 32 and disposed in a substantially three dimensional arrangement on a substrate.

52. An electronic circuit (1402, 1404, 1406, 1408) formed from a plurality of nano emission devices, the nano emission devices being any of the types described above in claims 1 - 17 or 21 - 32, the nano emission devices being disposed on a substrate and further comprising a heating element (2304) coupled to the substrate. 53. The electronic circuit of claim 52, wherein the heating element can be turned on and off under the control of at least one of the nano emission devices.

54. A programmable electronic circuit device formed from a plurality of nano emission devices, the nano emission devices being any of the types described above in claims 1 - 17 or 21 - 32, and arranged in an interconnected array, wherein the interconnected array includes at least one programmable element.

55. A programmable electronic circuit device as in claim 54 wherein the programmable element is chosen from the group consisting of a fuse, an antifuse, a memory element, a static random access memory (SRAM) element, an erasable programmable read-only memory (EPROM) element, an electrically erasable programmable read-only memory (EEPROM) element, and a flash EEPROM element.

56. A programmable electronic circuit device as in claim 54 wherein the programmable element is defined by a conductive interconnect layer applied during fabrication of the programmable electronic circuit device.

57. An electronic circuit (2400) comprising: a nano emission device (2410) as in any one of claims 1 - 17 or 21 - 32; and a semiconductor device (2404) electrically interconnected to the nano emission device, wherein the nano emission device and semiconductor devices are disposed on a common substrate (2402).

58. A memory cell (1406) comprising: two N-type nano emission devices; two P-type nano emission devices, the two N-type nano emission devices and the two P-type nano emission devices being interconnected to form a set-reset latch having an input/output port; and a bi-directional nano emission switch having a first conductive terminal coupled to the input/output port, a second conductive terminal configured to function as a memory cell bit line, and a gate configured to function as a select line.

59. A three-dimensional integrated circuit (1000) comprising: a plurality of horizontal layers of two-dimensional electrically interconnected arrays of nano emission devices as in any one of claims 1 - 17 or 21 - 32, wherein the multiple horizontal layers are fabricated in a vertically stacked arrangement and electrically interconnected to provide a three-dimensional interconnected array of devices.

60. A device as in claim 59, wherein the horizontal layers comprise an amorphous insulating layer.

61. A device as in claim 60, wherein the amorphous insulating layer comprises a plurality of electrically conductive vias to provide vertical interconnection between different horizontal layers.

62. A device as in claim 61, wherein the electrically conductive vias are arranged in a predefined two-dimensional arrangement according to a predefined pattern.

63. A method of operating a nano emission device comprising: providing a nano emission device having a first terminal and a second terminal, portions of the first terminal and the second terminal being exposed to each other within a channel cavity, and having a gate terminal disposed adjacent to the channel cavity at a position between the first terminal and the second terminal; applying a positive voltage to the second terminal relative to the first terminal so that electrons flow from the first terminal to the second terminal; and applying a positive voltage to the gate terminal relative to the first terminal so that electron flow from the first terminal to the second terminal is reduced.

64. The method of claim 63, further comprising placing the gate terminal at the same voltage as the first terminal so that electrons flow from the first terminal to the second terminal.

65. The method of claim 63, further comprising placing the gate terminal at the same ' voltage as the second terminal so that no electrons flow from the first terminal to the second terminal.

66. The method of claim 63, further comprising reversing the polarity of the voltage at the first terminal relative to the second terminal so that electrons flow from the second terminal to the first terminal.

67. A method (700) of making a nano emission device comprising: providing (702) a substrate; depositing (704) a sacrificial layer on the substrate; patterning (706) the sacrificial layer to define at least one channel cavity; depositing (708) a first insulating layer over the substrate and sacrificial layer; etching (710) the first insulating layer to define at least one emitter location and at least one collector location and to expose the at least one channel cavity; removing (712) the sacrificial layer from the at least one channel cavity; depositing (714) a conductive layer over the first insulating layer in vacuum to evacuate and seal the at least one channel cavity; patterning (716) the conductive layer to define at least one emitter, at least one collector, and at least one gate, wherein i.) the at least one emitter and the at least one collector extend into the at least one channel cavity and ii.) the at least one gate is separated from the at least one channel cavity by a portion of the first insulating layer to form a nano emission device; and depositing (718) a second insulating layer over the conductive layer and the first insulating layer.

68. A method as in claim 67, further comprising: etching the second insulating layer to expose portions of the emitter, the collector, and the gate; depositing a second conductive layer over the second insulating layer; and patterning the second conductive layer to form interconnections between a plurality of nano emission devices. 69. A method (750) of making a nano emission device comprising: providing (752) a substrate; depositing (754) a conductive layer on the substrate; patterning (756) the conductive layer to define at least one emitter, at least one collector, and at least one gate, depositing (758) a sacrificial layer on the substrate; patterning (760) the sacrificial layer to define at least one chamber a portion of the at least one emitter and a portion of the at least one collector extending into the chamber;

depositing (762) a first insulating layer over the at least one emitter, at least one collector, at least one gate, and the sacrificial layer; and removing (764) the sacrificial layer from the at least one chamber to define at least one channel cavity. 70. A method as in any one of claims 67 - 69, wherein the method is performed on a semiconductor processing line.

71. A method as in any one of claims 67 - 69, further comprising forming at least one semiconductor device on the substrate.

72. A method (1100) of making a three-dimensional integrated circuit comprising: providing ( 1110) a substrate ; forming (1120) a first plurality of nano emission devices on the substrate using a sequence of patterning, etching, and depositing steps wherein at a topmost layer of the first plurality of nano emission devices is an amorphous layer; forming (1130) a planar surface on the amorphous layer; and forming (1150) a second plurality of nano emission devices on the amorphous layer.

73. A method as in claim 72, further comprising forming (1140) a plurality of vias extending through the amorphous layer.

74. A method as in claim 73, wherein at least one of the first plurality of nano emission devices is interconnected to at least one of the second plurality of nano emission devices through at least one of the plurality of vias.

75. A method as in claim 72, wherein providing a substrate comprises forming a plurality of semiconductor devices on the substrate.

76. A method as in claim 72, further comprising forming a plurality of semiconductor devices supported by the substrate.

77. A method (2500) of making a three-dimensional integrated circuit comprising: forming (2502) a first integrated circuit layer on a substrate, the first integrated circuit layer having a plurality of interconnected electronic devices and having a plurality of interconnect vias on an uppermost surface;

forming (2504) at least one interconnect layer on top of the first integrated circuit layer to electrically connect to at least one connection to the plurality of interconnect vias; and forming (2506) a second integrated circuit layer on top of the interconnect layer, the second integrated circuit layer having a plurality of interconnected nano emission devices and at least one electrical connection to the interconnect layer.

78. A method as in claim 77 wherein forming the first integrated circuit layer and forming the second integrated circuit layer are performed by different business organizations.

79. A method as in claim 77 wherein at least one of the electronic devices is a nano emission device.

80. A method as in claim 77 wherein forming the first integrated circuit layer comprises forming at least one semiconductor device and forming the second integrated circuit layer comprises forming at least one nano emission device.

81. A product formed by any of the methods in any one of claims 67 - 69 or 72- 80. 82. A computer readable medium having computer readable instructions embodied thereon for controlling fabrication of a nano emission device, comprising: computer readable instructions for defining a channel cavity within an insulating body; computer readable instructions for defining an emitter terminal and a collector terminal disposed within the insulating body and extending into the channel cavity; and computer readable instructions for defining a gate terminal separated from the channel cavity by an insulating extension so that a voltage applied to the gate terminal can deflect electrons around or into the insulating extension depending on the voltage applied to the gate terminal.

83. A computer readable medium as in claim 82, wherein the computer readable medium is selected from the group of computer readable medium consisting of a floppy disk, a compact disk (CD-ROM), a digital video disk (DVD), a flash memory, a read only memory, a propagated signal, and combinations thereof. 84. A method (2600) of customizing integrated circuit wafers comprising:

a) defining (2602) a base circuit functionality and interface map by a first organization; b) fabricating (2604) a customizable integrated circuit wafer by a second organization, wherein the step of fabricating comprises i) obtaining a substrate, and ii) forming a plurality of nano emission devices on the substrate in at least one layer to implement the base circuit functionality and define a top surface having a plurality of connection points corresponding to the interface map; c) providing (2606) the customizable integrated circuit wafer to a third organization; and d) modifying (2608) the customizable integrated circuit by a third organization by forming a plurality of second devices on the top surface, the second devices interconnected to the plurality of connection points to provide an electronic system. 85. The method of claim 84, wherein the first organization and the second organization are the same organization.

86. The method of claim 84, wherein the first organization is a recognized standards setting body.

Description:

NANO EMISSION DEVICES, INTEGRATED CIRCUITS USING NANO EMISSION DEVICES AND RELATED METHODS

This application claims the benefit of U.S. Provisional Patent Application Serial No. 60/793,343 filed April 19, 2006, entitled "Nano Emission Device," U.S. Provisional Patent Application Serial No. 60/832,320 filed July 21, 2006, entitled "Nano Emission Devices, Integrated Circuits Using Nano Emission Devices, and Related Methods," and U.S. Provisional Patent Application Serial No. 60/901,561 filed February 14, 2007, entitled "Nano Emission Devices, Integrated Circuits using Nano Emission Devices, and Related Methods."

BACKGROUND

The semiconductor transistor revolutionized the electronics industry. First, small transistors replaced bulky and complex vacuum tubes. Later, multiple transistors were integrated into single packages, allowing an unprecedented scale of electronics integration. Easily and cheaply mass produced, transistors have become ubiquitous, with most electronics devices including thousands or millions of transistors in their integrated circuits.

The electronics industry seems to have an unquenchable thirst for faster devices. There are several factors that have tended to limit the speed of semiconductor devices.

One factor is that current flow in a semiconductor transistor is through the semiconductor material. The time it takes charge carriers (holes and electrons) to move through the semiconductor material tends to set a limit on the switching speed. Resistance and defects in the semiconductor material can also cause loss of efficiency and heating. Another factor limiting switching speed is the load capacitance. Two-dimensional arrays of semiconductor devices use a large amount of interconnect wiring relative to the size of the devices. This interconnect wiring has relatively large capacitance and thus further reduces the speed with which devices can be switched. Management of the interconnect capacitance can be a major issue in the design of large, high-speed integrated circuits. As semiconductor transistors have been made to run faster and faster, they also tend to generate increasing amounts of heat. Most of this heat is caused by the need to switch large currents to charge and discharge the capacitance of the interconnect wiring. Removing heat from these devices has proven to be another challenge facing the

electronics industry. In some cases, achievable integrated circuit densities are limited by the ability to remove heat.

Three-dimensional integrated circuits (using a three-dimensional array of semiconductor devices) are desired for their potential advantages in increased circuit density. Unfortunately, three-dimensional integrated circuits are currently difficult to build. Virtually all known three-dimensional integrated circuits use individual two- dimensional layers on individual die that are stacked and bonded together to form a multilayer semiconductor structure. The die can include a supporting substrate, or may be layers which have been peeled off of the supporting substrate after manufacturing. Due to the small size and fragility of the die, this process is tedious and expensive.

Alternate approaches to fabricating three-dimensional integrated circuits include fabricating layers of semiconductor devices on top of each other. Unfortunately, semiconductor devices are usually formed on a single crystal layer; hence the fabrication process typically includes forming a single crystal layer on top of the first layer of devices. Forming a single crystal layer on a partially fabricated device is also difficult and tedious. Defects in the single crystal layer can cause devices fabricated in subsequent layers to perform poorly or not at all, lowering yield of the finished devices.

Accordingly, the electronics industry continues its search for better semiconductor devices and alternatives to semiconductor devices.

SUMMARY

Embodiments of the present invention are generally directed towards nano emission devices. Nano emission devices can include, for example, diodes, N-type transistors, P-type transistors, and combined N- and P- type nano emission transistors. Nano emission devices can also include combinations of multiple nano emission devices. Nano emission devices may be connected together to form various circuits, including for example, logic gates, amplifiers, and the like. Nano emission devices may be fabricated in two- and three-dimensional integrated circuits.

BRIEF DESCRIPTION OF THE DRAWINGS

Various features and advantages of the invention will be apparent from the detailed description which follows, taken in conjunction with the accompanying

drawings, which together illustrate, by way of example, features of the invention; and, wherein:

FIG. 1 (a) is a top view of an N-type nano emission transistor in accordance with an embodiment of the present invention; FIG. l(b) is a cross section view of the N-type nano emission transistor of FIG.

Ha);

FIG. 2(a) is a cross section view of an N-type nano emission transistor in accordance with an alternate embodiment of the present invention;

FIG. 2(b) is an end cross section view of the N-type nano emission transistor of FIG. 2(a);

FIG. 3 is a cross section view of a P-type nano emission transistor in accordance with an embodiment of the present invention;

FIG. 4 is a cross section view of a combined N-type and P-type nano emission transistor in accordance with an alternate embodiment of the present invention; FIG. 5 is a side cross section view of a nano emission transistor in accordance with an embodiment of the present invention;

FIG. 6 is a side cross section view of a nano emission transistor in accordance with an alternate embodiment of the present invention;

FIG. 7 is a flow chart of a method of fabricating a nano emission device in accordance with an embodiment of the present invention;

FIG. 8 is a top cross section view of a bi-directional nano emission transistor in accordance with an embodiment of the present invention;

FIG. 9 is a side cross section view of a nano emission transistor using a two layer construction in accordance with an embodiment of the present invention; FIG. 10 is a side cross section view of a three-dimensional integrated circuit using nano emission transistors in accordance with an embodiment of the present invention;

FIG. 11 is a flow chart of a method of fabricating a three-dimensional integrated circuit in accordance with an embodiment of the present invention;

FIG. 12 is a cross section view of a diode using nano emission technology in accordance with an embodiment of the present invention;

FIG. 13 is an illustration of schematic symbols for various nano emission devices in accordance with an embodiment of the present invention;

FIG. 14 is a schematic of various components using nano emission devices in accordance with an embodiment of the present invention;

FIG. 15 is a cross section view of a pressure sensor using a nano emission device in accordance with an embodiment of the present invention; FIG. 16 is a cross section view of a current shifting nano emission device in accordance with an embodiment of the present invention;

FIG. 17 is a cross section view of a stacked integrated circuit in accordance with an embodiment of the present invention;

FIG. 18 is a schematic diagram of the flow of information and devices within the electronics industry in accordance with an embodiment of the present invention;

FIG. 19 is a cross section view of a nano emission transistor in accordance with another embodiment of the present invention;

FIG. 20 is a cross section view of a nano emission device in accordance with another embodiment of the present invention; FIG. 21 is a flow chart of a method of fabricating a nano emission device in accordance with another embodiment of the present invention;

FIG. 22 is a top view of a complementary pair of nano emission devices in accordance with an embodiment of the present invention;

FIG. 23 is a side view of a nano emission device having a heating element in accordance with an embodiment of the present invention;

FIG. 24 is a side view of an electronic circuit having semiconductor devices and nano emission devices in accordance with an embodiment of the present invention;

FIG. 25 is a flow chart of a method of fabricating a three-dimensional integrated circuit in accordance with another embodiment of the present invention; and FIG. 26 is a flow chart of a method of customizing integrated circuit wafers in accordance with another embodiment of the present invention.

DETAILED DESCRIPTION

Reference will now be made to the exemplary embodiments illustrated in the drawings, and specific language will be used herein to describe the same. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended. Alterations and further modifications of the inventive features illustrated herein, and additional applications of the principles of the inventions as illustrated herein,

which would occur to one skilled in the relevant art and having possession of this disclosure, are to be considered within the scope of the invention.

In the drawings, similar components and/or features may have the same numerical reference label. Further, various components of the same type may be distinguished by following the numerical reference label by an alphabetical label that distinguishes among the similar components. If only the numerical reference label is used in the specification, the description is applicable to any one of the similar components having the same numerical reference label irrespective of the alphabetical reference label.

Definitions

The singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a gate" includes reference to one or more of such gates, and reference to "an emitter" includes reference to one or more of such emitters. As used herein, a plurality of items, structural elements, compositional elements, and/or materials may be presented in a common list for convenience. However, these lists should be construed as though each member of the list is individually identified as a separate and unique member. Thus, no individual member of such list should be construed as a de facto equivalent of any other member of the same list solely based on their presentation in a common group without indications to the contrary.

As used herein, the terms "about" and "substantially" means that dimensions, sizes, formulations, parameters, shapes and other quantities and characteristics are not and need not be exact, but may be approximated and/or larger or smaller, as desired, reflecting tolerances, conversion factors, rounding off, measurement error and the like and other factors known to those of skill in the art. When used in reference to a quantity or amount of a material, or a specific characteristic thereof, "substantially" refers to an amount that is sufficient to provide an effect that the material or characteristic was intended to provide. The exact degree of deviation allowable may in some cases depend on the specific context. Similarly, "substantially free of or the like refers to the lack of an identified element or agent in a composition. Particularly, elements that are identified as being "substantially free of are either completely absent from the composition, or are included only in amounts which are small enough so as to have no measurable effect on the composition.

Concentrations, amounts, and other numerical data may be expressed or presented herein in a range format. It is to be understood that such a range format is used merely for convenience and brevity and thus should be interpreted flexibly to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited.

As an illustration, a numerical range of "about 1 micrometer to about 5 micrometers" should be interpreted to include not only the explicitly recited values of about 1 micrometer to about 5 micrometers, but also include individual values and sub- ranges within the indicated range. Thus, included in this numerical range are individual values such as 2, 3, and 4 and sub-ranges such as from 1-3, from 2-4, and from 3-5, etc. This same principle applies to ranges reciting only one numerical value and should apply regardless of the breadth of the range or the characteristics being described.

N-Type Nano Emission Device

FIG. l(a) and FIG. l(b) illustrate a nano emission device, shown generally at 100, in accordance with an embodiment of the present invention. This device is referred to herein as an N-type device. The device is constructed within an insulating body 112. For example, the insulating body can be silicon dioxide glass or similar insulator. As another example, the device can be constructed on a substrate using the semiconductor processing steps described further below. Disposed within the insulating body is a channel cavity 110. The device includes an emitter terminal 102 and a collector terminal 104 extending into the channel cavity at first and second positions, respectively. For example, the emitter and collector can be disposed at opposite ends of the channel cavity. The emitter terminal may include a pointed tip 103. The device includes a gate terminal having at least two gate portions 106 disposed at opposite sides of the channel cavity between the first position and the second position. The gate portions are separated from the channel cavity by interposed portions 114, 116 of the insulating body. The channel cavity can be evacuated, but absolute vacuum is not required. For example, vacuum levels of about 10 " 2 torr (1.3 pascals) can typically be achieved in semiconductor processing and packaging and are expected to prove adequate. Alternately, the channel cavity can be filled with a gas. For example, a gas which provides similar properties as vacuum with respect to the

emission and flow of electrons may be used. Noble gasses, such as argon, neon, krypton, xenon, and radon may prove useful.

The nano emission device 100 can be constructed on a substrate, where the gate portions 106a, 106b, emitter terminal 102, and collector terminal 104 are all positioned in a common plane and formed on a substrate surface, using techniques described in further detail below. Alternately, the nano emission device can be constructed in other orientations. For example, the device can be constructed by forming one gate portion in one layer, the emitter terminal and collector terminal in another layer, and the other gate , portion in yet another layer. A side view of the device would thus appear similar to that shown in FIG. 1 (a).

Operation of the N-type nano emission device is as follows. Electrons are emitted from the emitter 102 through field emission (also known as quantum tunneling or Fowler- Nordheim tunneling) or thermionic emission, or combinations of these types of emission and possibly other emission modes (including, for example, photoemission). Emitted electrons are attracted toward the collector (when the collector is positively charged relative to the emitter), and the electrons will normally pass through the channel cavity 110 to the collector 104, providing a current through the device. Because the current flow is through a vacuum, rather than through semiconductor, increased electron mobility is obtained enabling increased switching speed relative to semiconductor devices. When a negative voltage is applied to the gate(s) 106 relative to the emitter it repels the electrons in the emitter, restricting the flow of current through the device. Emitted electrons tend to be repelled by the gate, and accumulate a space charge near the emitter, inhibiting further emission of electrons. In contrast, when a positive voltage is applied to the gate it helps to pull electrons out of the emitter, allowing them to flow through to the collector. Accordingly, the device may operate as a switch, with current flowing from emitter to collector controlled by the voltage applied to the gate. The device may also operate as an amplifier, where a small change in voltage applied to the gate causes a large change in current flow from the emitter to the collector.

Insulating the gate from the channel helps to limit the amount of current which flows into the gate. The insulation is therefore not essential, but helps to provide devices which have high input impedance at the gate terminal.

An alternate embodiment of an N-type device is shown in FIG. 2(a) and FIG. 2(b) in accordance with an embodiment of the present invention. In the alternate embodiment,

the N-type device, shown generally at 200, includes a gate terminal 206 which is circumferentially wrapped around the channel cavity 110 between emitter 102 and collector 104. The gate terminal is separated from the channel cavity by a portion of the insulating body, insulating the gate terminal from the channel cavity. The alternate embodiment can provide improved switching characteristics, as the circumferentially wrapped gate exerts greater influence on the emission of electrons from the emitter. As with the device shown in FIGS. l(a) and IQa), the N-type device of FIGS. 2(a) and 2Qb) can be constructed in differing orientations on a substrate

The pointed tip 103 of the emitter terminal 102 may help to concentrate electric field gradient in the vicinity of the pointed tip, helping to improve the efficiency of the field emission from the emitter. The pointed tip is not essential and a flat emitter (similar in appearance to the collector 104) can be used. Alternately, both the emitter and collector can include a pointed tip if desired. Thus, devices may be constructed so they are symmetric or substantially symmetric to support current flow in either direction. In other words, a symmetric or substantially symmetric device can provide current in either direction (e.g., from "emitter" to "collector" or from "collector" to "emitter") by reversing the bias voltages applied to the terminals. Alternately, devices may be constructed to they are asymmetric. An asymmetric device may provide asymmetric current versus voltage characteristics, providing higher level of currents for a given bias voltage in one polarity versus the opposite polarity.

P-Tvpe Nano Emission Device

FIG. 3 illustrates a nano emission device, shown generally at 300, in accordance with an embodiment of the present invention. This device is referred to herein as a P-type device. The device is constructed within an insulating body 312. Disposed within the insulating body is a channel cavity 310. The channel cavity includes an insulating extension 318 protruding into an interior of the channel cavity. The device includes an emitter terminal 302 and a collector terminal 304 extending into the channel cavity at first and second positions, respectively. The collector terminal is on an opposite side of the insulting extension from the emitter terminal. For example, the emitter and collector can be disposed at opposite ends of the channel cavity, with the insulating extension at a middle of the channel cavity. The insulating extension need not be exactly centered between the emitter and collector, and can be placed closer to either the emitter or the

collector. The device includes a gate terminal 306 disposed at a side of the channel cavity between the first position and the second position, separated from the channel cavity by a portion 316 of the insulating body.

Operation of the P-type nano emission device 300 is as follows. Electrons are emitted from the emitter 302 through field emission, thermionic emission, or both. The electrons will normally be inhibited from passing through the channel cavity 310 to the collector 304 because of the presence of the insulating extension 318. Emitted electrons thus pile up on the insulating extension, raising the potential to the point where electrons no longer leave the emitter. When a negative voltage is applied to the gate 306 relative to the emitter, the path of the electrons is altered so they flow around the insulating extension, reaching the collector so that current flows through the device. The negative voltage on the gate deflects the electrons away from the insulating extension, forcing them into the open portion of the cavity where they can be attracted to the collector. In contrast, when a positive voltage is applied to the gate, it helps to block current flow through the device, as electrons are attracted toward the gate, and increase the space charge The P-type device may also operate as a switch or amplifier.

It should be appreciated that the operation of the P-type device is quite different than previous field emission devices, since there is normally no direct path from the emitter to the collector. Current flow is thus established by applying gate voltages to help deflect or guide the electrons through a curved or bent path to enable them to reach the collector. In general, the insulating extension intercepts a straight path from the emitter to the collector, inhibiting electron flow in the absence of gate voltage. A gate is positioned adjacent to the channel cavity in a position so that electrical voltage applied to the gate terminal can influence the path of electrons emitted from the emitter. For example, a voltage can be applied such that electrons accumulate at a position adjacent to the insulating extension to inhibit current flow from the emitter terminal to the collector terminal. Alternately, a voltage can be applied so that electrons are deflected around the insulating extension to enable current flow from the emitter terminal to the collector terminal. For sufficient voltage, current flow through the device may either be stopped entirely or a saturation current reached.

Alternate arrangements of a P-type device can also be used. For example, the gate 306 may include portions that extend up into the insulating extension 314, for example as illustrated in FIG. 22 and described further below.

Combined N- and P-Type Nano Emission Device

A combined device that can be used for either P or N-type operation is illustrated in FIG. 4 in accordance with an embodiment of the present invention. The device, shown generally at 400, is constructed in an insulating body 412 and includes an emitter 402 and collector 404 extending into a channel cavity 410 as described above. Two gates are provided, an N-gate 408 and a P-gate 406. The N-gate is located at a side of the channel cavity, separated by a portion of the insulating layer 414 The P-gate is located at another side of the channel cavity, separated from the channel cavity by an insulating extension 418 which protrudes into the channel cavity. The N-gate provides N-type control, where negative bias on the gate (relative to the emitter) tends to reduce current and positive bias on the gate tends to increase current. The P-gate provides P-type control, where negative bias on the gate (relative to the emitter) tends to increase current and positive bias on the gate tends to decrease current. The device may be wired for use in a circuit as either an N-type or P-type device.

Alternately, both gates may be used for combined N-type and P-type operation. For example, bias voltages may be applied to either gate to assist in defining a desired switching point for the device when controlled by the other gate. For example, a small bias can be applied to the N-gate to control what voltage applied to the P-gate corresponds to the threshold between switching current flow on and off. This represents an additional advantage over conventional field effect transistors (FET) which generally have a fixed switching threshold.

Various ways of using the combined N- and P-type nano emission device are possible. The device can be used as a four terminal device, where voltages on the N- and P-gate are coordinate to achieve desired affects. As another example, the device can be used as a four terminal device, where a fixed bias voltage is applied to one of the gates to control switching threshold, and the other gate is used for active switching. As yet another example, the device can be used as a three terminal device, and wired into circuitry as desired to provide fixed N- or P-type operation. For example, the combined device may prove useful in programmable logic arrays as discussed further below.

It will be appreciated that the geometry of the nano emission device will also influence the gate voltage(s) required to switch the device on or off. For example, if the insulating extension 418 only partially obstructs the path from the emitter 402 to the

collector 404, the device may be in a normally-on state, allowing current to flow from the emitter to collector without an applied gate voltage. Such a device therefore provides capabilities somewhat similar in function to a depletion mode FET. On the other hand, if the insulating extension mostly blocks the path from the emitter to the collector, the device may be in a normally-off state, somewhat similar in functional capability to an enhancement mode FET. Accordingly, great flexibility in the design parameters of the devices is obtained.

Distance between the emitter and collector will also affect the voltages and currents achieved during operation of the device. For example, the threshold voltage to initiate current between the emitter and collector is lowered as the emitter and collector are more closely spaced. Similarly, the closer the gate is positioned relative to internal structures (e.g., emitter, collector, insulating extension, etc.) of the device, the greater the effect of the gate upon that structure. Accordingly, the distance between the emitter and collector and positioning of the gate relative to the emitter and collector may be adjusted to provide a desired set of electrical characteristics.

It will be appreciated that providing a switching threshold which is less than the emitter to collector voltage allows devices to be chained together without intermediary buffers or bias circuits.

In general, smaller scale devices can provide for smaller switching voltages. For example, field emission may occur when a voltage gradient in excess of 10 9 V/m is present. For a fixed bias voltage, a smaller emitter to collector gap will therefore result in a higher voltage gradient. In addition, voltage gradients can be enhanced by geometry, such as pointed tips. Surface irregularities may also provide for enhancement of field emission. Geometric and other enhancement factors can provide for field emission at voltage gradients 10 to 100, or even 1000 times lower than 10 9 V/m. Accordingly, for emitter to collector gaps on the order of 1 micrometer or less, current flow may occur at voltages of less than 200 volts, less than 100 volts, or even less than 50 volts.

In general, however, with smaller scale devices, lower current carrying capability is provided. Currents in the picoampere range can easily be achieved using emitter/collector geometries on the order of micrometers. Higher currents in the microampere range may also be obtained. For integrated circuit applications, on-chip switching currents may be maintained at very low levels (e.g. microamperes) for internal interconnections. For example, as described further below, in a three-dimensional

integrated circuit, interconnect length, and hence capacitance, can be kept very small, enabling very small currents to provide adequate switching speeds. Accordingly, devices may be scaled to provide switching currents of about one microampere or even smaller. As generally higher currents are used to drive off-chip components, amplifiers and buffers can be included to translate to suitable off-chip voltage and current levels. Amplifiers and buffers may be implemented using nano emission devices with larger scale geometry or using conventional semiconductor devices on the same substrate, as described further below.

P -type Bi- or Uni-Directional Devices

A bi-directional device which can support current flow in either direction through the device is illustrated in FIG. 8 in accordance with an embodiment of the present invention. The device, shown generally at 800, includes a first conductive terminal 802a and a second conductive terminal 802b located opposite the first terminal. The conductive terminals can include pointed portions 803. A gate terminal 806 is located between the first conductive terminal and the second conductive terminal. A channel cavity 808 is between the first conductive terminal and the second conductive terminal. The channel cavity includes a charge accumulation location wherein a positive voltage on the gate terminal encourages charge accumulation at the location to impede current flow through the channel cavity. For example, an insulating extension 809 can define charge accumulation locations 810, 812.

Applying a sufficient voltage between the conductive terminals 802 causes current flow between the conductive terminals. A voltage applied to the gate terminal controls the amount of current flow. For example, if the voltage applied to the second conductive terminal 802b is higher than the voltage applied to the first conductive terminal 802a, the first conductive terminal will act as an emitter and the second conductive terminal will function as a collector. Electrons will flow from the first conductive terminal to the second conductive terminal (by convention, current flow is defined in the opposite direction from electron flow, hence current flow is from the second conductive terminal to the first conductive terminal). If a sufficiently large positive voltage is applied to the gate 806 relative to the first conductive terminal this will tend to deflect electrons toward the charge accumulation location 810. Electrons will accordingly accumulate at the charge

accumulation location, raising the local potential, and eventually cause electron emission (and thus current flow) to stop. Conversely, if a zero or sufficiently small positive voltage is applied to the gate, current flow will be allowed to continue to flow.

The device 800 can also conduct current in the opposite direction. If a positive voltage is applied to the first terminal 802a relative to the second terminal 802b, the second terminal will function as an emitter and the first terminal will function as a collector. Operation is similar to the previous example, except that a different charge accumulation location 812 is defined. By providing bi-directional current flow, the device can operate as a bidirectional switch (replacing a two transistor bidirectional switches as used in conventional CMOS technology).

The symmetric device 800 is expected to have symmetric switching properties. It will be appreciated, however, that an asymmetric device can also be constructed by varying the geometry and/or spacing of the conductive terminals 802, gate 806, and/or insulating extension 809. For example, by varying the geometry of the insulating extension, it may be possible to produce a device with characteristics similar to a zener diode. Switching threshold and gain of a three terminal device may also be adjusted.

An alternate device configuration can include multiple emitters, as illustrated in

FIG. 19. The device 1900 includes two emitters 1902a, 1902b disposed on opposite sides of the cavity 1906 and a collector 1908 positioned between the emitters. Two gates 1910a, 1910b separately control current flow from the emitters to the common collector.

Complementary Pairs

Nano emission devices in accordance with embodiments of the present invention can be formed into complementary pairs. For example, as illustrated in FIG. 22, a complementary pair can be formed from the combination of an N-type device 2202 and a

P-type device 2204. The gates 2206, 2208 of the devices can be connected together, e.g. through interconnect metal 2210, to form a control terminal 2212. The emitter 2214 of the P-type device can be connected to the collector 2216 of the N-type device to form an output terminal 2220. Connections to the collector 2218 of the P-type device and emitter 2222 of the N-type device may be made through interconnect metal to other devices to form integrated circuits.

Electron flow is either in or out of the output terminal 2220 (i.e., out of the N-type collector 2216 to the output terminal 2220 or into of the P-type emitter 2214 terminal

from the output terminal) depending on the voltage applied to the control terminal. Switching thresholds of the devices may be adjusted so that substantially only the N-type device 2202 or substantially only the P-type device 2204 conduct current at any given time. The switching threshold of the device is a function of the relative spacing and geometry of the emitter, collector, and gate terminals. For example, a larger insulating protrusion 2224 will tend to block more of the channel cavity, increasing the gate voltage required to switch the device.

Although shown here as though the N-type device 2202 and P-type device 2204 each have their own respective cavities 2226, 2228, the devices may be constructed in a common cavity.

If desired, the P-type device gate can include a portion 2209 that extends into the insulating extension 2224, although this is not essential. Extending the gate into the insulating extension may help to increase the efficiency of the gate in affecting electron flow.

Alternate Configurations and Benefits of Nano Emission Devices

Nano emission devices in accordance with embodiments of the present invention can be constructed as substantially planer devices, where the device is constructed in layers on a substrate. For example, the emitter and collector can be disposed within a common plane, formed on the substrate. The gate can also be disposed within the common plane, or the gate may be disposed in a different plane, for example raised above the substrate by an insulating material as described further below.

FIG. 9 illustrates a side view of a device, where the emitter and collector are formed in one layer, and the gate is formed in a second layer. The device, shown generally at 900, is made on a substrate 902, for example, of amorphous glass. The emitter 904 and collector 906 are supported by the substrate. An insulating layer 908 formed over the emitter and collector includes a void 910 to serve as the channel cavity, and supports a gate 912 positioned over the channel cavity. One advantage of the device of FIG. 9 is that the gate provides a self shielding effect, helping to shield the device from stray fields. For example, devices can be stacked vertically, as described further below, in which case the gate helps to avoid crosstalk between devices on different vertical layers. As an alternative, additional conductive layers can be deposited to provide shielding between vertically stacked devices. It will be appreciated that the insulating

layer provides a roof over the void, which helps to facilitate vertical stacking of devices. Various ways of establishing the void in the insulating layer are described further below.

Additional gate elements can also be included, positioning the gates at various positions around channel cavity. For example, gates can be distributed around a circumference of the channel cavity at a substantially constant distance between the emitter and collector. As another example, gates can be distributed along a side of the channel cavity, some positioned closer to the emitter and others positioned closer to the collector position. For example, FIG. 20 illustrates a nano-emission device 250 having multiple gate elements 206a, 206b, 206c positioned between an emitter terminal 102 and collector terminal 104. Multiple gate elements can be applied to N-type, P-type, combined N-type and P-type, and other nano emission devices.

Generally, the longitudinal dimension (end-to-end length) of the channel cavity between the emitter and collector can be greater than the lateral dimension (side-to-side width) of the channel cavity. Unlike semiconductor devices, the length of the channel cavity does not appreciably affect the switching speed, since the speed of the electrons outside bulk semiconductor material is very high. The length of the channel cavity has a greater effect on the voltage required to produce current through the device. Accordingly, channel cavities may have various dimensions, including for example, a length between the emitter and collector of about 0.1 micrometers to about 10 micrometers, and as a more particular example, a length of about 2 micrometers, and for example a width of about 0.5 micrometers.

While the above discussion has principally illustrated single devices, multiple devices can be constructed within a common channel cavity. For example, it will be appreciated that the device illustrated in FIG. 19 is essentially two nano emission devices sharing a common collector 1908 within a single channel cavity 1906. In general, multiple nano emission devices may share a common channel cavity. For example, multiple nano emission devices may be fabricated on an insulating substrate by forming the emitters, collectors, and gates of the devices by patterning metal onto the insulating substrate. The insulating substrate may be, for example, glass. As another example, the insulating substrate may be a conductive material (e.g. copper) with an insulating layer placed on top (e.g. glass). The channel cavity may then be formed by placing a covering over the nano emission devices. The channel cavity may be evacuated.

It will be appreciated that the overall dimensions of the nano emission devices can be relatively small as compared to conventional MOS transistors. In part, this is because the nano emission devices do not require an n-well or p-well. The n-well or p-well in a MOS transistor extends approximately three times the extent of the gate area in each dimension. In contrast, using similar size lithography, it is expected that a nano emission device can be constructed that is comparable in size to the gate area, or about one-ninth the overall size of a MOS transistors. Accordingly, it is expected that nano emission devices can provide approximately an order of magnitude increase in circuit density relative to CMOS devices. A diode can be constructed using nano emission technology as illustrated in FIG.

12. The diode 1200 includes a cathode 1202 and an anode 1204 exposed to each other within a common vacuum chamber 1206. Electron emission from the cathode can occur readily because the pointed portion 1208 helps to achieve a high electric field gradient. In contrast, emission from the anode is more difficult. Consequently, electron flow from the cathode to anode is easier than electron flow from the anode to cathode, and the device provides the functionality of a diode. A three terminal transistor device can also be constructed similarly to the diode, where a pointed portion of the cathode and/or anode is included to enhance emission.

As discussed above, electron emission from the emitter can occur by means of field emission, thermionic emission, or both. For example, for small devices having dimensions on the order of micrometers, field emission can occur at relatively low voltages (e.g. less than 100 volts). For example, devices where the distance between the emitter terminal and collector terminal is between about 0.1 and 10 micrometers may provide operation at desirable voltages. Of course, shorter spacing may also be used, with even lower operating voltages.

Alternately, thermionic emission can be enhanced by heating the device. A nano emission device in accordance with embodiments of the present invention may operate at significantly higher temperatures than conventional semiconductor devices. For example, a device can be constructed using materials such as silicon dioxide glass and tungsten which are less subject to degradation at high temperatures which would destroy silicon, doped silicon, and similar materials. Unlike silicon, which is subject to damage and reliability reduction at low temperatures of about 250 degrees C, nano emission devices may be operated at substantially higher temperatures without harming reliability. Hence,

nano emission devices may require less cooling (or even no cooling at all) than that of semiconductor circuits. This can help to simplify thermal management in electronic systems using nano emission devices.

While heat may affect the resulting switching thresholds of a nano emission device, it is expected that the increased current caused by heat will result in higher currents and faster switching speeds. Conversely, cooler temperatures may result in lower current, lower speed, and commensurate lower power consumption. Accordingly, operation of digital devices may be altered by including heating or cooling elements to adjust the temperature of the devices as illustrated in FIG. 23. For example, an electronic circuit 2300 may include a heating element 2304 integrated into a supporting substrate 2306 and positioned in a layer below the nano emission device 2302 to allow the heating element to increase the operating temperature of the nano emission device. As other examples, the heat element may be positioned above the nano emission device, or even be a separate element mechanically bonded to the substrate, for example, using a thermally conductive adhesive. The heating element may heat the device for operation at temperatures greater than 200, 500, or even 1000 degrees Celsius. Multiple heating elements may be included and positioned underneath one or more nano emission devices. Control of heating (or cooling) can allow optimization of device performance for different operational configurations. For example, a memory array may include a heating element which can be turned on and off. By turning the heating element on, speed of the memory may be increased, allowing high speed operation. By turning the heating element off, although the memory may operate more slowly, reduced current and power consumption may be obtained. For example, such a memory can be used advantageously in a laptop or other device which operates off of battery power. Because nano emission devices do not rely on semiconductor materials and their relatively narrow energy band gaps, it is believed that nano emission devices may provide improved radiation hardening and EMP resistance relative to semiconductor devices. Accordingly, nano emission devices may prove highly desirable for military and space applications. Nano emission devices can also be made to operate at high voltages. For example, silicon dioxide is an excellent insulator, and thus devices can be designed which can operate at high voltages. For example, devices which can operate directly from line

voltage of 110 or 220 volts may be constructed. Improved power efficiency may therefore be obtained in building power supply systems using nano emission devices.

Logic Devices and Other Components Various specific applications for nano emission transistors will now be described.

These applications are not meant to be exhaustive, and many other applications will occur to one of ordinary skill in the art from this disclosure, and are intended to be included within the scope of the present invention.

Combinations of N-type and P-type nano emission transistors can be used to construct various logic functions. For simplicity of illustration, the logic functions are shown schematically, as various different physical arrangements of the nano emission devices as described herein can be used. FIG. 13 illustrates schematic symbols for an N- type nano emission transistor 1302, P-type nano emission transistor 1304, a nano emission diode 1306, and a bidirectional nano emission switch 1308. These symbols, while schematic, are suggestive of a particular structure of nano emission devices discussed herein. It will be understood, however, that devices using any of the various structures illustrated, described, or suggested herein for the individual nano emission transistors may be used in implementing the logic devices.

Using these schematic symbols, various types of logic gates that can be constructed from nano emission devices are illustrated. For example, FIG. 14 illustrates several logic functions, such as a NAND gate 1402, a NOR gate 1404, a static memory cell 1406, and an inverter 1408. As alluded to above, many different arrangements of the individual nano emission devices on a substrate can be used. Some arrangements may provide advantages in layout density. In general, techniques applied to layout of logic devices based on semiconductor transistors can be applied to layout of logic devices based on nano emission devices.

Logic gates constructed from nano emission devices are expected to obtain the benefits of high speed operation, fewer layers required in construction compared to semiconductor devices, less sensitivity to heat, and lower power consumption as discussed above. Moreover, circuit density is expected to be higher as a result of the generally smaller geometry of a nano emission device as compared to a comparable semiconductor device.

With respect to the static memory cell 1406, one additional advantage is that the number of devices can be reduced from 6 transistors conventionally required for a CMOS memory cell to 5 nano emission transistors by using bidirectional capability of the nano emission switch. This may help to increase density and reduce the complexity of memory arrays constructed using nano emission devices.

Nano emission devices can be combined into a variety of other logic devices, such as AND, OR, XOR, XAND, adders, encoders/multiplexers, decoders/demultiplexers, latches, flip flops, shift registers, counters, complex logic functions, processors, memory arrays, switching systems and the like. Nano emission devices can also be used to construct components such as linear circuits, amplifiers, logarithmic amplifiers, voltage comparators, analog multipliers, mixers, analog to digital converters, digital to analog converters, voltage multipliers, power conditioners and the like. For example, the inverter 1408 (FIG. 14) can be biased (e.g., with negative feedback) to operate as a linear amplifier. Complex electronic circuits can be constructed from nano emission devices similarly as is currently done using semiconductor transistors.

Nano emission devices can also be used as sensors. For example, emission from the emitter can be enhanced when the emitter is illuminated, making a naturally photosensitive device. Accordingly, nano emission devices may be used as photodetectors.

Other types of sensors can also be fabricated using nano emission devices, including for example accelerometers, magnetic sensors, voltage sensors, temperature sensors, pressure/acoustic sensors, and the like. For example, a P-type nano emission device can be used as a pressure sensor. FIG. 15 illustrates a side view of a P-type nano emission device 1500. Bias voltages are applied to the device so that a current is flowing through the device, e.g. from an emitter 1510 to a collector 1512. The top surface 1502 or bottom surface 1504 of the device, or both, are coupled to an environment for which pressure is to be measured. When the pressure changes, this results in a change in the channel cavity 1506, for example causing the insulating protrusion 1508 to block more or less of the channel. This change in turn causes a corresponding change in the current flowing through the device. This current can be amplified by other devices to provide a desired level of sensitivity. Of course, multiple devices can be used and configured in various arrangements to help enhance or diminish sensitivity such as differential pair

arrangements and the like. Depending on the application, the device may be biased using a gate 1514, so the device is not in saturation, or it may be possible to omit the gate entirely.

Use of a nano emission device as a magnetic or electric field sensor is also possible. Because the electrons within the channel are free electrons they can be affected by external electric or magnetic fields. Accordingly, a device can be arranged to help enhance its sensitivity to an applied field.

Because the electrons within the channel are free electrons the device may also function as an accelerometer. For example, when the device is moved, electrons currently in transit from the emitter to the collector will tend to continue on the same trajectory as when they were emitted. Hence, when the device of FIG. 15 is accelerated upward, more electrons may pass around the insulating protrusion, causing the current to increase.

Conversely, when the device is accelerated downward, more electrons may crash into the insulating protrusion, causing the current to decrease. While this effect is expected to be quite small, amplification of these current differences may be provided to provide a useful level of sensitivity.

Current Switching

The preceding discussion has focused mainly on nano emission devices which operate as switches or gain elements. Accordingly, known techniques for designing digital and analog circuits using semiconductor devices can be applied to circuits using nano emission devices. Nano emission devices can also be used as always-on current directing switches as will now be explained. This type of operation is less analogous to that of existing semiconductor devices, and accordingly may present new circuit design approaches.

FIG. 16 illustrates a nano emission device which provides a current shifting capability. The device includes a channel cavity 1602 which can be formed in an insulating body 1604, for example as described above. An emitter 1606 is exposed to the channel cavity. As described above, the emitter can include a pointed portion (not shown). A plurality of collectors 1608 are also exposed to the channel cavity. At least one gate 1610 is positioned adjacent to the channel cavity, insulated from the channel cavity. When a voltage is applied to the at least one gate, the current flow is directed

from the emitter to substantially one of the plurality of collectors. Accordingly, the applied voltage steers the current towards a particular one of the collectors.

In one embodiment, a current shifting nano emission device can be used to fabricate an analog to digital converter. A number of gates corresponding to the number of possible digital levels to be detected are included. The input voltage is applied to one or more gates of the device. Based on the input voltage, the emitted current is directed towards substantially one of the collectors. The output of the collectors can then be encoded into a desired digital representation.

Electronic Circuits

As discussed above, multiple nano emission devices can be fabricated on a common substrate to create an integrated circuit. Accordingly, integrated circuits using a plurality of N-type, P-type, both types, and other devices as described above can be constructed. An integrated circuit in accordance with an embodiment of the present invention can include a planar arrangement of nano emission devices, interconnected through patterned conductive interconnects as for silicon integrated circuits. Alternately, an integrated circuit in accordance with another embodiment of the present invention can include a vertically stacked arrangement of nano emission devices, interconnected through vias and conductive interconnects. As yet another embodiment of the present invention, an integrated circuit can include a three dimensional arrangement of nano emission devices.

Because the nano emission devices can operate at very high temperatures, heat dissipation is less critical than for silicon devices. This enables devices to be stacked with fewer adverse affects caused by heating. The use of multilayer construction also allows interconnect between devices to be shorter. The shorter interconnect leads to reduced capacitance, which allows higher switching speeds and lower power dissipation. Accordingly, it is anticipated that integrated circuit constructed in accordance with the present invention may be able to use large numbers of layers (e.g. 2, 3, 4, 5 or even more) to help reduce required substrate area. Hence, nano emission devices of the present invention may be able to produce orders of magnitude improvement in density over existing silicon devices.

Removal of heat from an integrated circuit using nano emission devices can be enhanced by using highly heat-conductive substrates. For example, because the nano

emission devices need not be constructed on semiconductor substrates, a metal substrate can be used. A metal substrate can be helpful because high heat conductivity is provided, allowing for heat to be conducted away from (or towards, if desired) the integrated circuit. A thin insulating layer (e.g., a few micrometers of glass) can be deposited on top of the metal substrate to provide a surface for fabrication of the nano emission devices thereon.

One application for nano emission devices is programmable logic. A programmable electronic circuit can be formed from a plurality of nano emission devices in an interconnected array, where the interconnected array includes at least one programmable element. For example, programmable elements can include a fuse, an antifuse, a memory element, a static random access memory (SRAM) element, an erasable programmable read-only memory (EPROM) element, an electrically erasable programmable read-only memory (EEPROM) element, a flash EEPROM element, or combinations thereof. Various architectures for programmable logic are known which can be used. For example, an array of nano emission devices can be fabricated on a substrate, and programmable interconnect defined by a conductive interconnect layer (or layers) applied during fabrication of the programmable electronic circuit device, as for gate arrays.

Fabrication

Fabrication of nano emission devices will now be described. A method of fabricating devices is illustrated in FIG. 7. FIGS. 5 and 6 provide side views of two alternative device arrangements fabricated by the method of FIG. 7.

The method of fabrication, shown generally at 700 (FIG. 7), includes providing 702 a substrate. For example, a substrate 502 (FIGS. 5 and 6) may be a glass substrate. Other substrates may also be used, including for example, semiconductor substrates (e.g. silicon, gallium arsenide, indium phosphide, cadmium zinc telluride and the like), quartz, sapphire, metal, glass, etc. If the substrate is not an insulating material, it may be helpful to deposit an insulating layer on the substrate. It should be appreciated from the above discussion that operation of the nano emission devices does not rely on doping of semiconductor layers to provide the desired electronic properties. Accordingly, it is not necessary that the devices be constructed on single crystal semiconductor as is the case for more conventional electronic devices and

integrated circuits. Hence, although nano emissions devices may be constructed on a single crystal substrates (e.g. a silicon wafer), the devices may also be constructed on an amorphous or polycrystalline substrate. For example, the substrate may be glass, ceramic, or similar materials. This can help to make nano emission devices in accordance with the present invention more economical. For example, the high costs associated with procuring single crystal silicon wafers may be avoided.

The method includes depositing 704 a sacrificial layer on the substrate. The sacrificial layer is then patterned 706 to define areas which will become channel cavities 516 of the finished devices. For example, the sacrificial layer may be a resist or poly layer.

In general, depositing materials can be performed by any process that grows, coats, or otherwise transfers a material onto the device under construction. For example depositing materials can be performed by spin coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), and similar processes.

Patterning can be performed by lithographic processes. For example, a layer of material can be deposited, a photoresist layer applied and exposed through a mask, exposed (positive photoresist) or unexposed (negative photoresist) portions of the photoresist washed away by a developer solution to reveal portions of the material layer, and the revealed portions of the material removed using etching or other processing.

The next step is depositing 708 a first insulating layer 504 over the substrate and sacrificial layer. The first insulating layer helps to define the boundary of the channel cavity. The insulating layer can be, for example silicon dioxide glass. Other materials may be used for the insulating layer, including for example spun-on glass, ceramic materials, transition metal oxides (e.g. hafnium oxide), and the like.

The next step is etching 710 the first insulating layer to define emitter locations and collector locations. Note that an emitter and a collector extend into each channel cavity, so this etching step also exposes the channel cavities. Optionally, the first insulating layer can also be etched to define gate location(s) as shown in FIG. 6. Note that, if the first insulating layer is etched to define the gate location(s), some insulator portion is left between the gate location(s) and the sacrificial layer so the finished gate will be separated from the finished channel cavity. Alternately, the gate can be deposited on top of the first insulating layer as shown in FIG. 5.

Etching can be performed, for example, by wet etching or dry etching, such as reactive ion etch (RIE).

The channel cavities are then emptied by removing 712 the sacrificial layer. Various ways of removing the sacrificial layer are possible, while leaving the first insulating layer portions in place. For example, the sacrificial layer may be removed by heating which burns or vaporizes the sacrificial layer. As another example, the sacrificial layer may be removed by etching, using an etchant which attacks the sacrificial layer without substantially attacking the insulating layer. As an example, the sacrificial layer may be formed using photoresist which is etched away using a solvent. The next step is depositing 714 a conductive layer over the first insulating layer in vacuum to evacuate and seal the channel cavities. The emitter 510, collector 512, and gate 514 are then defined by patterning 716 the conductive layer. The conductive layer can be, for example a metal, including, for example, tungsten, gold, aluminum, thorium, or other metals, or alloys thereof. The conductive layer may be deposited in multiple steps, providing for layering or patterning of different metals in the terminals. If desired, the emitter, collector, and gate may be formed in separate steps, for example, using different materials.

Since metal deposition is conveniently performed in vacuum, evacuation of the channel cavity can occur automatically during the deposition 714 of the conductive layer. Various other ways of evacuating the channel cavity, however, may also be used. For example, the channel cavity may be evacuated at a later step of the fabrication and sealed using deposition of insulating material.

Patterning includes changing the shape of deposited materials, for example by using lithography. In lithography, the device is coated with a photoresist, the photoresist exposed through a mask, unexposed regions washed away by a developer solution, and etching or other processing used to remove the deposited material from the unexposed regions. Various lithography techniques are known and used in the semiconductor processing arts and can vary from the above sequence.

After the above steps, the nano emission device is functional, however it is desirable to also include depositing 718 a second insulating layer 508 over the conductive layer and the first insulating layer. The second insulating layer helps to avoid undesired electron emission and/or conduction between portions of the emitter and collector not exposed to each other within the channel cavity.

In accordance with another embodiment of the present invention, the method can further include etching the second insulating layer to expose portions of the emitter, the collector, and the gate for electrical interconnection, for example through vias 520. In accordance with another embodiment, the method can further include depositing a second conductive layer over the second insulating layer and patterning the second conductive layer to form interconnections between a plurality of nano emission devices. For example, multiple N-type, P-type, combined N- and P-type, and combinations thereof can be included on a common substrate and interconnected to form complex electronic circuits. One advantage of nano emission devices as disclosed herein is that in some embodiments, the emitter and collector terminals may be simultaneously formed using a common set of processing steps. In some embodiments, the emitter, collector and gate terminals may be simultaneously formed using a common set of processing steps. This is in contrast to conventional semiconductor devices which typically require separate ion implantation steps or the like to form different portions of the devices. Accordingly, nano emission devices may use fewer processing steps, resulting in faster fabrication time and reduced capital equipment requirements.

Nano emission devices may be manufactured using a semiconductor processing line. Accordingly, embodiments of the present invention can be economically produced using existing manufacturing facilities. Moreover, as the number of processing steps used to make a nano emission device can be fewer than that of typical semiconductor devices, the nano emission devices may be less expensive than semiconductor devices. In particular, fabricating a nano emission device can be performed without including ion implantation steps or using pure silicon crystal substrates. For fabrication of conventional semiconductor devices, "front end" processing steps associated with forming the doped regions in the substrate can consume about two-thirds of the total processing steps and resulting device cost. Hence, it is expected that integrated circuits using nano emission devices may cost approximately one third of comparable CMOS circuits while increasing throughput of manufacturing. Furthermore, it is expected that yield for integrated circuits made from nano emission devices may be higher than comparable circuits made using semiconductor technology since less complex processing is required. "Back end" processing to form interconnect between nano emission devices in an integrated circuit can use the same or similar techniques as for semiconductor devices.

Because a nano emission device can be constructed using semiconductor processing steps, it is possible to combine nano emission devices and semiconductor devices on a common substrate. Hence, in accordance with another embodiment of the present invention, fabrication of a nano emission device can include forming a semiconductor device on the substrate.

As another exemplary embodiment, the second insulating layer can be flattened, for example, using chemical-mechanical polishing to provide a flat surface for constructing additional vertically stacked devices. For example, a first device (or devices) can be constructed, forming the emitter, collector, gate, and channel cavity in one or more layers. An insulating layer can be disposed above the emitter, collector, gate, and channel cavity to provide a second substrate surface with similar properties as the first substrate surface, so that a second nano emission device can be formed thereon. More particularly, since the nano emission devices can be constructed on an amorphous substrate, the substrate surface can be an amorphous layer. Accordingly, a first nano emission device can include an upper amorphous surface which serves as a supporting surface for second nano emission device fabricated on top of the first nano emission device. Because the nano emission devices need not be constructed on a single crystal semiconductor substrate, fabrication of vertically stacked devices is simplified as compared to silicon devices. For example, glass substrates can be used which are less expensive than single crystal silicon.

Various other sequences of processing can be used to form a nano emission device in addition to those described above. The processing steps may be performed in a different order, and features of the nano emission devices fabricated in a different order. For example, one alternate method 750 of fabrication, shown in FIG. 21, can include depositing 754 a conductive material on a substrate, patterning 756 emitter, collector, and gate terminals, and forming a channel cavity, for example, by depositing 758 and patterning 760 a sacrificial layer and depositing 762 an insulating layers to define the channel cavity and other features of the device. Fabrication steps may be performed in alternate orders or using alternate techniques which will occur to one of ordinary skill the art based on the above disclosure.

As described above, fabrication may be performed using semiconductor processing equipment. Typically, the features of an integrated circuit are defined by photolithography steps using so-called masks. Photolithography may be performed using

optical, ultraviolet, extreme ultraviolet, or similar techniques. A number of different masks may be used in the fabrication of an integrated circuit to define different features, such as emitters, gates, cavities, insulator regions, conductor regions, and the like. Masks can be formed using mask making machinery, for example, controlled by a computer and driven by computer readable instructions which define the various features of the integrated circuit. Alternately, features of an integrated circuit may be defined using a resist which is directly written using a laser, electron beam, or ion beam. Control of the writing can be via a computer driven by computer readable instructions. The computer readable instructions cause the computer to implement the instructions, thereby controlling the fabrication process.

Accordingly, an embodiment of the invention can include a computer readable medium having computer readable instructions embodied thereon for controlling fabrication of a nano emission device. For example, the computer readable medium can include instructions for defining a channel cavity within an insulating body. The computer readable medium can also include computer readable instructions for defining an emitter terminal and a collector terminal disposed within the insulating body and extending into the channel cavity. The computer readable medium can also include computer readable instructions for defining a gate terminal separated from the channel cavity by an insulating extension so that a voltage applied to the gate terminal can deflect electrons around or into the insulating extension depending on the voltage applied thereto.

Various types of computer readable medium are known in the art which can be used to control production of masks or fabrication of a nano emission device. For example, the computer readable medium can be a floppy disk, compact disk (CD-ROM), digital video disk (DVD), flash memory (e.g., a flash drive or USB drive), read only memory, or a propagated signal (e.g. Internet communications using the Internet Protocol), or the like. New types of computer readable medium may also be developed in the future and may also be used to distribute computer readable instructions.

Stacking Devices

As has been mentioned above, nano emission devices in accordance with the present invention can be stacked into vertical layers to provide a three-dimensional integrated circuit. FIG. 10 illustrates stacked nano emission devices in accordance with

an embodiment of the present invention. An integrated circuit 1000 can be constructed using multiple horizontal layers 1002 of planar arrangements of two-dimensional horizontally interconnected 1008 arrays of devices 1004. Multiple horizontal layers can be stacked vertically and vertically interconnected 1010 to provide a three-dimensional interconnected array of devices. For example, the horizontal layers can include an amorphous insulating layer 1006 as described above. The amorphous insulating layer can serve as both the top of the devices in one layer and the substrate for the devices in the next vertical layer. The amorphous insulating layer separates individual layers of devices. Vertical interconnection 1010 between layers 1002 can include a plurality of electrically conductive vias 1012 which extend through the amorphous insulating layers 1006. The vias can be arranged in a pre-defined two-dimensional arrangement according to a predefined pattern to allow predictable interconnect between the layers.

Making a three-dimensional integrated circuit using nano emission devices can proceed similarly as making a single two-dimensional integrated circuit. Starting with a substrate (e.g., an amorphous material), a first plurality of nano emission devices can be formed on the substrate using a sequence of patterning, etching, and depositing steps, wherein the deposited layers are substantially amorphous. The processing steps, for example as described above, can be performed using typical semiconductor processing equipment. Following completion of the devices the amorphous upper surface of the first plurality of devices can be planarized, for example by performing a chemical mechanical polish operation. Providing a planar upper surface is helpful because it makes it easier to retain focus during subsequence lithographic processing steps, and also helps to control the resulting device geometries. A second layer having a plurality of nano emission devices can then be formed on the amorphous upper surface, using a similar sequence of patterning, etching, and depositing steps. Between forming the first and second layers, etching to expose vias and metallization may also be performed to provide interconnect between the layers. For example, a flow chart of a method 1000 of fabricating a three-dimensional integrated circuit is illustrated in FIG. 1 1. An alternate method 2500 of fabricating a three-dimensional integrated circuit is illustrated in FIG. 25. The processing steps described above can be performed repeatedly to form two, three, four, or even more layers. By stacking devices into a three-dimensional array, several benefits are obtained relative to conventional two-dimensional integrated circuits. As alluded to earlier, interconnect lengths can be substantially shortened. As a simple

example, consider a single layer, two-dimensional arrangement of a complex circuit which occupies a 1 centimeter squared area. This complex circuit may be rearranged into a stacked three-dimensional array of nano emission devices using approximately 250 layers on about a 4 millimeter squared area substrate. Layers may be about 1 micrometer in height, so the overall circuit height will be about 0.25 millimeters. The three- dimensional arrangement results in a significant shortening of average and maximum interconnect lengths. For example, a trace which runs from one extreme corner to the other extreme corner of the circuit can have a length of about 20 millimeters in the two- dimensional circuit. In the three-dimensional circuit, a similar trace is shortened in length to about 4.25 millimeters, a savings of about 79%. Since switching time and power consumption is proportional to the interconnect length being driven, significant (e.g., orders of magnitude) increase in switching speed may thus be accomplished using a stacked arrangement. Of course, the actual improvements obtained will be dependant on a number of application dependent factors including, for example, interconnect complexity, average interconnect length, actual devices, and heat dissipation considerations.

While it is expected that the yield of nano emission devices and integrated circuits formed using nano emission devices will be quite high, when producing complex three- dimensional circuits, yield may drop to undesirable levels. Accordingly, integrated circuits using nano emission devices can include redundant circuitry which can be alternatively selected for use in the overall integrated circuit.

One problem with stacking of conventional semiconductor devices is dealing with heat, as it is difficult to extract heat from the stacked layers. In contrast, since nano emission devices are relatively unaffected by high temperatures as compared to semiconductor devices, heat is much less of a concern. Moreover, as noted above, heat may enhance the switching speed of the devices, in which case heat from lower layers may enhance the performance of higher layers in the vertical stack.

Another benefit of three-dimensional devices is the extremely high integration levels that may be achieved. Current die sizes are limited to about 1 centimeter on a side, which translates to about one hundred million transistors in conventional two-dimensional CMOS technology. In contrast, three-dimensional nano emission devices are expected to enable integration levels having billions of transistors on comparably sized die. These

increased density levels may also allow the economic life of existing semiconductor facilities to be extended.

Applications of Stacked Devices A variety of interesting applications are made possible by the ability to stack nano emission devices into three-dimensional arrays.

For example, nano emission devices can provide sensors as described further below. An array of sensor devices can be disposed on an uppermost layer of a three- dimensional integrated circuit, and processing for the sensors implemented in lower layers. An integrated sensing/processing device as just described may achieve higher performance than currently known devices. For example, reduced interconnect length between analog sensors and analog to digital conversion can help to reduce noise pickup. Increased interconnection between the sensors and processing is possible, so processing can be more tightly coupled to the sensing. For example, one application can include a single chip which includes imaging (e.g., similar to the function of a charge coupled device), distortion correction, image processing effects (e.g., digital zoom), and image encoding (e.g., JPEG). Such a device may significantly reduce the cost and complexity of a digital camera.

Another device can include an entire computer system on a chip. For example, one layer (e.g. a base layer) can be the processor circuitry, another (e.g. next) layer can provide the memory, another layer the video processing, etc. Such extensive integration can significantly reduce the cost of computer systems, as interconnection, busses, and the like can be eliminated. As noted above, devices compatible with high voltages can be produced using the same process steps, so the chip can even include power supply components. Such high integration in conventional semiconductors is not currently feasible due to problems of needing single crystal substrates for high performance devices, heating, and yield. As noted above, nano emission devices ameliorate many of these problems.

When such high levels of integration are considered, new paradigms for the electronic industry are expected to emerge. For example, the current interface point for integrated circuit technology from different vendors is typically the pinout arrangement of packaged devices. Pinout may be provided, for example, by bonding the chip to a lead frame in packages such as a pin grid array, land grid array, ball grid array, leadless chip

carrier, dual inline package, or the like. Circuit designs using integrated circuits from different vendors typically interface the packaged integrated circuits using a printed circuit board. For some integrated circuit devices, pinouts are highly standardized, with multiple vendors offering pin-compatible integrated circuits with similar or identical functionality (e.g., memory).

With the ability to stack integrated circuits using nano emission technology, a shift to interfacing at the chip or wafer level may occur. For example, the two- dimensional arrangement of vias on the top layer of an integrated circuit may be defined and published. This can enable different business organizations to fabricate additional circuitry on top of a completed device. In other words, one organization may fabricate one integrated circuit on a wafer or substrate, and a second organization may fabricate a second integrated circuit onto the same wafer or substrate, interfacing the second integrated circuit to the first integrated circuit to provide a functional system. Many different integrated circuits may be vertically stacked in such a manner, providing an entire complex system on a single device. Thus, rather than interfacing different integrated circuit devices through a printed circuit board, integrated circuit devices may be interfaced directly by fabricating them on top of each other.

For example, interconnect layers can be included between different devices, or devices designed to interface directly to the published two-dimensional via arrangements. Standard via position placements on the top layer of a processor integrated circuit can be defined and published, somewhat analogous to the pinouts for current integrated circuits. As an example, a business organization can fabricate its own customized layer of nano emission devices on top of a completed processor device.

FIG. 17 illustrates a side view of an exemplary three-dimensional integrated circuit 1700 as can be cooperatively fabricated by multiple business organizations. A substrate 1702 and integrated circuit processor layer 1704 are fabricated by a first business organization. The processor layer includes a top surface 1706 with a published via arrangement (analogous to the processor pinout). On top of the processor layer is a first interconnection layer 1708 (or layers) to provide interconnection from the published via arrangement of the processor to a published via arrangement for a memory layer 1710. The first interconnection layer and memory layer may be fabricated by a second business organization. On top of the memory layer is a second interconnection layer 1712 (or layers) and a custom circuitry layer 1714. The second interconnection layer and

custom circuitry layer may be fabricated by a third business organization. The memory layer may include various pass-through vias, which allow connection between processor layer and the custom circuitry layer. The completed three-dimensional integrated circuit may provide complex system functionality, such as the electronics for a computer system. Standardization of the interface arrangements (both top and bottom) of devices may occur to improve the economy of stacked integrated circuits. For example, a first organization may define base circuit functionality and interface map, and a second organization may fabricate a customizable integrated circuit wafer. The customizable integrated circuit wafer may include a plurality of nano emission devices having interconnect vias on a top surface corresponding to the interface map. A third organization may take the customizable integrated circuit wafer and fabricate a second layer of devices on the top surface, the second layer of devices interconnected to the interconnect vias to form an electronic system. FIG. 26 illustrates an example of a method 2600 of customizing integrated circuit wafers. For example, a processor vendor can manufacture processors on base substrates, finishing the devices by providing electrical interconnection vias in a predefined two- dimensional arrangement on the upper surface. The wafers, each having an array of completed processors, may then be sold as units, rather than being diced up and packaged as for conventional integrated circuits. Different vendors may then acquire completed wafers and manufacture different electronic circuits on top of the processors. For example, one vendor can implement customized circuitry on top of the processor to produce unique devices. As another example, a computer may be fabricated by the cooperation of several vendors, each fabricating a layer with their own unique circuitry. Of course, the same organization may define interface maps, base circuit functionality, and fabricate customizable wafers. In addition, recognized standards setting bodies may define functionality and interface maps. Business organizations may also license their technology, allowing organizations to fabricate multiple layers having different organization's integrated circuit designs. For example, FIG. 18 illustrates one exemplary flow of via definition information, design layout information, wafers, and completed devices within the electronics industry. It is expected that other new business arrangements may also be enabled by the nano emission technology.

Mixed Semiconductor and Nano Emission Devices

In another embodiment, nano emission devices can also be constructed on top of a conventional semiconductor wafer already having a plurality of semiconductor devices as illustrated in FIG. 24. For example, an electronic circuit 2400 can include both semiconductor devices and nano emission devices. A conventional semiconductor wafer 2402 which already has a plurality of semiconductor devices 2404 can be prepared for fabrication of nano emission devices by depositing an insulating layer 2406 (e.g., silicon dioxide, silicon nitride, or other insulating material), etching for vias, metallization deposit to " form the electrical interconnection vias 2408, and a chemical mechanical polishing to planarize. The nano emission devices 2410 can then be formed on top of the wafer, and interconnected to the semiconductor devices underneath through the vias. Such an arrangement can obtain the benefits of both semiconductor devices and nano emission devices.

Conclusion

It is expected that nano emission devices may be used in virtually any electronic system where conventional semiconductor devices are currently used, as well as opening up new potential uses for electronics. Nano emission devices in accordance with embodiments of the present invention can be constructed from simple materials including for example as tungsten for conducting elements and silicon dioxide glass for insulating elements. Accordingly, costs associated with growing single crystal semiconductor and doping may be avoided making nano emission device based integration circuits less expensive to produce. Ability to easily stack devices may overcome the barriers that have heretofore limited the use of three-dimensional integrated circuits. Various advantages in speed, power consumption, and heat resistance for nano emission devices may make possible new levels of performance in electronic systems, revolutionizing the electronics industry.

It is to be understood that the above-referenced arrangements are only illustrative of the application for the principles of the present invention. Numerous modifications and alternative arrangements can be devised without departing from the spirit and scope of the present invention. While the present invention has been shown in the drawings and fully described above with particularity and detail in connection with what is presently deemed to be the most practical and preferred embodiment(s) of the invention, it will be

apparent to those of ordinary skill in the art that numerous modifications can be made without departing from the principles and concepts of the invention as set forth herein.